TW201714208A - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TW201714208A
TW201714208A TW104132992A TW104132992A TW201714208A TW 201714208 A TW201714208 A TW 201714208A TW 104132992 A TW104132992 A TW 104132992A TW 104132992 A TW104132992 A TW 104132992A TW 201714208 A TW201714208 A TW 201714208A
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hard mask
gate structure
gate
contact plug
disposed
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TW104132992A
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TWI675406B (zh
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洪慶文
吳家榮
李怡慧
劉盈成
黃志森
林俊賢
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聯華電子股份有限公司
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Priority to US14/935,456 priority patent/US9455227B1/en
Priority to US15/243,986 priority patent/US9685337B2/en
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Abstract

本發明揭露一種製作半導體元件的方法。首先提供一基底，然後形成一第一閘極結構於基底上，形成一第一接觸插塞於第一閘極結構旁，以及進行一金屬閘極置換製程將第一閘極結構轉換為金屬閘極。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，尤指一種於金屬閘極置換製程前形成接觸插塞的方法。
近年來，隨著場效電晶體(field effect transistors, FETs)元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor, Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。由於鰭狀場效電晶體元件的立體結構可增加閘極與鰭狀結構的接觸面積，因此，可進一步增加閘極對於載子通道區域的控制，從而降低小尺寸元件面臨的汲極引發能帶降低(drain induced barrier lowering, DIBL)效應，並可以抑制短通道效應(short channel effect, SCE)。再者，由於鰭狀場效電晶體元件在同樣的閘極長度下會具有更寬的通道寬度，因而可獲得加倍的汲極驅動電流。甚而，電晶體元件的臨界電壓(threshold voltage)亦可藉由調整閘極的功函數而加以調控。
一般而言，半導體製程在進入10奈米世代後接觸插塞的接觸面積會大幅降低，造成阻值的增加。除此之外，接觸插塞的製作也需伴隨更多的光罩來完成。而隨著光罩數量的提升，一點點主動區域的偏移又會再次造成阻值的提升，影響整個元件的運作。因此如何在現今場效電晶體的架構下改良此問題即為現今一重要課題。
本發明較佳實施例揭露一種製作半導體元件的方法。首先提供一基底，然後形成一第一閘極結構於基底上，形成一第一接觸插塞於第一閘極結構旁，以及進行一金屬閘極置換製程將第一閘極結構轉換為金屬閘極。
本發明另一實施例揭露一種半導體元件，包含一基底，一鰭狀結構設於基底上，一第一閘極結構設於鰭狀結構上，一第一接觸插塞設於第一閘極結構旁以及一第一硬遮罩設於第一接觸插塞上。
請參照第1圖至第13圖，第1圖至第13圖為本發明較佳實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板。基底12上具有至少一鰭狀結構14及一絕緣層，其中鰭狀結構14之底部係被絕緣層，例如氧化矽所包覆而形成淺溝隔離16，部分的鰭狀結構14上另分別設有複數個閘極結構18、20，淺溝隔離16上設有閘極結構24，而閘極結構22則同時設於鰭狀結構14與淺溝隔離16上。
鰭狀結構14之形成方式可以包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中。接著，對應三閘極電晶體元件及雙閘極鰭狀電晶體元件結構特性的不同，而可選擇性去除或留下圖案化遮罩，並利用沈積、化學機械研磨(chemical mechanical polishing, CMP)及回蝕刻製程而形成一環繞鰭狀結構14底部之淺溝隔離16。除此之外，鰭狀結構14之形成方式另也可以是先製作一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出半導體層，此半導體層即可作為相對應的鰭狀結構14。同樣的，另可以選擇性去除或留下圖案化硬遮罩層，並透過沈積、CMP及回蝕刻製程形成一淺溝隔離16以包覆住鰭狀結構14之底部。另外，當基底12為矽覆絕緣(SOI)基板時，則可利用圖案化遮罩來蝕刻基底12上之一半導體層，並停止於此半導體層下方的一底氧化層以形成鰭狀結構14，故可省略前述製作淺溝隔離16的步驟。
閘極結構18、20、22、24之製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先閘極介電層(high-k first)製程以及後閘極製程之後閘極介電層(high-k last)製程等方式製作完成。以本實施例之先閘極介電層製程為例，可先於鰭狀結構14與淺溝隔離16上形成包含介質層26、多晶矽材料28及硬遮罩30所構成的閘極結構18、20、22、24，然後於閘極結構18、20、22、24側壁形成側壁子32、34、36、38。接著於側壁子34兩側的鰭狀結構14以及/或基底12中形成一源極/汲極區域40及/或磊晶層42。
然後如第2圖所示，形成一金屬層44於閘極結構18、20、22、24上並覆蓋磊晶層42與淺溝隔離16表面，其中金屬層44可選自由鈦、鉭、氮化鈦及氮化鉭所構成的群組，但不侷限於此。之後可再選擇性覆蓋一由氮化鈦所構成的遮蓋層(圖未示)於金屬層44上，並接著進行一快速升溫退火(rapid thermal process, RTP)製程，使金屬層44與磊晶層42中的矽反應以形成一矽化金屬層46。需注意的是，由於與磊晶層42接觸的金屬層44較佳於加熱過程中完全轉換為矽化金屬層52，因此剩餘的金屬層44，即矽化金屬製程中未反應的金屬仍殘留於側壁子32、34、36、38表面、硬遮罩30表面以及矽化金屬層46表面。
接著如第3圖所示，形成一金屬層48於金屬層44上並填滿閘極結構18、20、22、24之間的所有空間，其中金屬層48較佳選自由鋁、鈦、鉭、鎢、鈮、鉬以及銅所構成的群組，但不侷限於此。然後進行一平坦化製程，例如以化學機械研磨(chemical mechanical polishing, CMP)製程去除部分金屬層48與金屬層44以形成接觸插塞50、52與接觸插塞54。其中成接觸插塞50、52、54上表面均與硬遮罩30上表面齊平，接觸插塞50、52較佳設於鰭狀結構上而接觸插塞54則設於淺溝隔離16上。
隨後如第4圖所示，形成一硬遮罩56於閘極結構18、20、22與接觸插塞50上，並利用硬遮罩56進行一蝕刻製程去除未被硬遮罩56所覆蓋的接觸插塞，即所有設於淺溝隔離16上的接觸插塞54。至此形成一開口58暴露出淺溝隔離16表面與側壁子36、38側壁。在本實施例中，硬遮罩56較佳由氧化物所構成，例如可選自由二氧化矽與氮氧化矽所構成的群組。
然後如第5圖所示，進行一可流動式化學氣相沉積(flowable chemical vapor deposition, FCVD)製程沉積一層間介電層60於閘極結構18、20、22、24、硬遮罩56以及淺溝隔離16上並填滿開口58，其中層間介電層可由其他氧化物等之絕緣材料所構成，例如四乙氧基矽烷(Tetraethyl orthosilicate, TEOS)，但不侷限於此。
由於在本較佳實施例中，硬遮罩56與層間介電層60皆係由氧化物所構成，故如第6圖所示，接著可利用一平坦化製程，例如以CMP方式來同時去除部分層間介電層60與全部的硬遮罩56，藉此暴露出接觸插塞50、52表面並使剩餘的層間介電層60表面與接觸插塞50、52表面齊平。
然後如第7圖所示，利用閘極結構18、20、22、24與層間介電層60為遮罩進行一蝕刻製程，去除部分接觸插塞50、52並使剩餘的接觸插塞50、52上表面略低於閘極結構18、20中的多晶矽材料28上表面。至此於剩餘的接觸插塞50、52上以及閘極結構18、20、22之間形成開口62。
如第8圖所示，隨後先形成一遮罩層(圖未示)於閘極結構18、20、22、24與層間介電層60上並填滿開口62，然後進行一平坦化製程，例如利用CMP去除部分遮罩層、部分側壁子32、34、36、38、部分層間介電層60與所有的硬遮罩30，以於剩餘的接觸插塞50、52上分別形成硬遮罩64，且硬遮罩64上表面與閘極結構18、20、22、24中的多晶矽材料28上表面齊平。在本實施例中，硬遮罩64較佳由氧化物，例如二氧化矽所構成，但不侷限於此。
隨後進行一金屬閘極置換製程，例如再利用硬遮罩64與層間介電層60為遮罩進行一蝕刻製程，去除閘極結構18、20、22、24中的所有多晶矽材料28與介質層26，以於鰭狀結構14與淺溝隔離16上形成開口66、68、70。然後如第9圖所示，形成一高介電常數介電層72、一功函數金屬層74以及一低阻抗金屬層76於開口66、68、70內。
在本實施例中，高介電常數介電層72包含介電常數大於4的介電材料，例如係選自氧化鉿(hafnium oxide，HfO2 )、矽酸鉿氧化合物(hafnium silicon oxide，HfSiO4 )、矽酸鉿氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化鋁(aluminum oxide，Al2 O3 )、氧化鑭(lanthanum oxide，La2 O3 )、氧化鉭(tantalum oxide，Ta2 O5 )、氧化釔(yttrium oxide，Y2 O3 )、氧化鋯(zirconium oxide，ZrO2 )、鈦酸鍶（strontium titanate oxide， SrTiO3 ）、矽酸鋯氧化合物(zirconium silicon oxide，ZrSiO4 )、鋯酸鉿(hafnium zirconium oxide，HfZrO4 )、鍶鉍鉭氧化物(strontium bismuth tantalate, SrBi2 Ta2 O9 , SBT)、鋯鈦酸鉛(lead zirconate titanate , PbZrx Ti1-x O3 , PZT)、鈦酸鋇鍶(barium strontium titanate, Bax Sr1-x TiO3 , BST)、或其組合所組成之群組。
功函數金屬層74較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層74可選用功函數為3.9電子伏特(eV)～4.3 eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC (碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層74可選用功函數為4.8 eV～5.2 eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層74與低阻抗金屬層76之間可包含另一頂部阻障層(圖未示)，其中頂部阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層76則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。由於依據金屬閘極置換製程將虛置閘極轉換為金屬閘極乃此領域者所熟知技藝，在此不另加贅述。
接著利用平坦化製程，例如以CMP去除部分低阻抗金屬層76、部分功函數金屬層74以及部分高介電常數介電層72以形成金屬閘極78、80、82、84。其中金屬閘極78、80設於鰭狀結構14上，金屬閘極84設於淺溝隔離16上，而金屬閘極82則同時設於鰭狀結構14與淺溝隔離16上，且金屬閘極78、80、82、84均與硬遮罩64上表面齊平。
如第10圖所示，隨後利用硬遮罩64與層間介電層60為遮罩進行一蝕刻製程，去除部分金屬閘極78、80、82、84以形成複數個凹槽(圖未示)，然後形成一遮罩層(圖未示)填滿各凹槽並搭配進行一平坦化製程，例如以CMP去除部分遮罩層，以於金屬閘極78、80、82、84上形成硬遮罩86、88、90，且硬遮罩86、88、90的上表面較佳與硬遮罩64及層間介電層60上表面齊平。在本實施例中，硬遮罩86、88、90的材料較佳不同於硬遮罩64，例如硬遮罩86、88、90較佳由氮化矽所構成，但不侷限於此。
之後如第11圖所示，先形成一介電層92於硬遮罩86、88、90、硬遮罩64以及層間介電層60上，然後進行一接觸插塞製程，以於介電層92中形成複數個接觸插塞94分別連接並接觸接觸插塞50、52、硬遮罩64與金屬閘極84。在本實施例中，各接觸插塞94包含一阻隔層96與一金屬層98，其中阻隔層96較佳選自由鈦、鉭、氮化鈦、氮化鉭以及氮化鎢所構成的群組，金屬層98較佳選自由鋁、鈦、鉭、鎢、鈮、鉬以及銅所構成的群組，但不侷限於此。
值得注意的是，本實施例所形成接觸插塞94時較佳僅去除部分硬遮罩64暴露出下面的接觸插塞50、52與金屬閘極84，因此接觸插塞94除了接觸接觸插塞50、52與金屬閘極84外又同時接觸硬遮罩64。請同時參照第12圖至第13圖，第12圖揭露設於金屬閘極78、80之間的接觸插塞94電連接硬遮罩64之上視圖，第13圖則為第12圖沿著切線AA’之剖面示意圖。如第12圖與第13圖所示，當接觸插塞94電連接底下的接觸插塞50時由於僅部分硬遮罩64被去除，使剩餘的硬遮罩64仍設於接觸插塞94兩側，因此所形成的接觸插塞94同時接觸接觸插塞50與硬遮罩64，或更具體而言接觸插塞94的底部接觸接觸插塞50而接觸插塞94側壁則接觸剩餘的硬遮罩64。至此即完成本發明較佳實施例之半導體元件的製作。
請再參照第11圖，其另揭露本發明較佳實施例之一半導體元件結構。如第11圖所示，本發明之半導體元件主要包含至少一鰭狀結構14設於基底12上，一淺溝隔離16環繞該鰭狀結構14，複數個金屬閘極78、80設於鰭狀結構14上，一金屬閘極84設於淺溝隔離16上，一金屬閘極82同時設於鰭狀結構14與淺溝隔離16上，複數個側壁子32、34、36、38分別設於金屬閘極78、80、82、84旁，複數個接觸插塞50、52設於鰭狀結構14上，一硬遮罩64設於各接觸插塞50、52上，一硬遮罩86、88、90設於各金屬閘極78、80、82、84上，一層間介電層60設於金屬閘極84旁之淺溝隔離16上，一介電層92設於金屬閘極78、80、82、84上以及接觸插塞94設於介電層92中並接觸接觸插塞50、52與金屬閘極84。
更具體而言，例如以接觸插塞50所設置的位置來看，接觸插塞50較佳設於金屬閘78極與金屬閘極80之間並同時接觸側壁子32與側壁子34，或側壁子32與側壁子34之間除了接觸插塞50之外不具有任何其他物件，例如介電層。
其次，如上所述，由於本實施例所形成接觸插塞94時較佳僅去除部分硬遮罩64並暴露出下面的接觸插塞50、52與金屬閘極84，因此所形成的接觸插塞94較佳同時設於介電層92與硬遮罩64中，且同時接觸接觸插塞50、52、金屬閘極84以及硬遮罩64。
另外在本實施例中，硬遮罩86、88、90上表面較佳與硬遮罩64以及層間介電層60上表面齊平，硬遮罩64與硬遮罩86、88、90較佳包含不同材料，例如硬遮罩64較佳由氧化矽所構成，硬遮罩86、88、90較佳由氮化矽所構成，但不侷限於此。介電層92與硬遮罩64較佳包含相同材料，例如兩者均由氧化物所構成，但不侷限於此。
綜上所述，本發明主於金屬閘極置換製程之前先於多晶矽所構成的閘極結構旁形成接觸插塞並使接觸插塞直接接觸兩側的側壁子，如此除了可提升接觸插塞的接觸面積，又可避免習知製作接觸插塞時產生偏移的情況。   以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12‧‧‧基底
14‧‧‧鰭狀結構
16‧‧‧淺溝隔離
18‧‧‧閘極結構
20‧‧‧閘極結構
22‧‧‧閘極結構
24‧‧‧閘極結構
26‧‧‧介質層
28‧‧‧多晶矽材料
30‧‧‧硬遮罩
32‧‧‧側壁子
34‧‧‧側壁子
36‧‧‧側壁子
38‧‧‧側壁子
40‧‧‧源極/汲極區域
42‧‧‧磊晶層
44‧‧‧金屬層
46‧‧‧矽化金屬層
48‧‧‧金屬層
50‧‧‧接觸插塞
52‧‧‧接觸插塞
54‧‧‧接觸插塞
56‧‧‧硬遮罩
58‧‧‧開口
60‧‧‧層間介電層
62‧‧‧開口
64‧‧‧硬遮罩
66‧‧‧開口
68‧‧‧開口
70‧‧‧開口
72‧‧‧高介電常數介電層
74‧‧‧功函數金屬層
76‧‧‧低阻抗金屬層
78‧‧‧金屬閘極
80‧‧‧金屬閘極
82‧‧‧金屬閘極
84‧‧‧金屬閘極
86‧‧‧硬遮罩
88‧‧‧硬遮罩
90‧‧‧硬遮罩
92‧‧‧介電層
94‧‧‧接觸插塞
96‧‧‧一阻隔層
98‧‧‧金屬層
第1圖至第13圖為本發明較佳實施例製作一半導體元件之方法示意圖。
12‧‧‧基底
14‧‧‧鰭狀結構
16‧‧‧淺溝隔離
32‧‧‧側壁子
34‧‧‧側壁子
36‧‧‧側壁子
38‧‧‧側壁子
40‧‧‧源極/汲極區域
42‧‧‧磊晶層
44‧‧‧金屬層
46‧‧‧矽化金屬層
50‧‧‧接觸插塞
52‧‧‧接觸插塞
60‧‧‧層間介電層
64‧‧‧硬遮罩
72‧‧‧高介電常數介電層
74‧‧‧功函數金屬層
76‧‧‧低阻抗金屬層
78‧‧‧金屬閘極
80‧‧‧金屬閘極
82‧‧‧金屬閘極
84‧‧‧金屬閘極
86‧‧‧硬遮罩
88‧‧‧硬遮罩
92‧‧‧介電層
94‧‧‧接觸插塞
96‧‧‧一阻隔層
98‧‧‧金屬層

Claims (15)

  1. 一種製作半導體元件的方法，包含：      提供一基底；      形成一第一閘極結構於該基底上；      形成一第一接觸插塞於該第一閘極結構旁；以及      進行一金屬閘極置換製程將該第一閘極結構轉換為金屬閘極。
  2. 如申請專利範圍第1項所述之方法，另包含一鰭狀結構設於該基底上以及一淺溝隔離環繞該鰭狀結構，該方法包含：      形成該第一閘極結構於該基底上以及一第二閘極結構於該淺溝隔離上，該第一閘極結構具有一第一硬遮罩且該第二閘極結構具有一第二硬遮罩；      形成一第一側壁子於該第一閘極結構旁以及一第二側壁子於該第二閘極結構旁；      形成該第一接觸插塞並接觸該第一側壁子以及形成一第二接觸插塞於該淺溝隔離上並接觸該第二側壁子；      形成一第三硬遮罩於該第一閘極結構及該第一接觸插塞上；      去除該第二接觸插塞以形成一第一開口；      形成一層間介電層於該第一開口內；      去除部分該第一接觸插塞；      形成一第四硬遮罩於該第一接觸插塞上；以及      進行該金屬閘極置換製程。
  3. 如申請專利範圍第2項所述之方法，其中該第三硬遮罩及該第四硬遮罩包含相同材料。
  4. 如申請專利範圍第2項所述之方法，另包含：      形成一源極/汲極區域於該第一閘極結構旁之該基底內；      形成一矽化金屬層於該源極/汲極區域上；      形成一金屬層於該鰭狀結構、該淺溝隔離、該第一閘極結構及該第二閘極結構上；以及      平坦化該金屬層以形成該第一接觸插塞及該第二接觸插塞。
  5. 如申請專利範圍第2項所述之方法，其中該金屬閘極置換製程包含：      去除該第一閘極結構及該第二閘極結構以於該鰭狀結構上形成一第二開口以及於該淺溝隔離上形成一第三開口；      形成一功函數金屬層以及一低阻抗金屬層於該第二開口及該第三開口；      平坦化該低阻抗金屬層及該功函數金屬層以形成一第一金屬閘極於該鰭狀結構上以及一第二金屬閘極於該淺溝隔離上；以及      形成一第五硬遮罩於該第一金屬閘極上以及一第六硬遮罩於該第二金屬閘極上。
  6. 如申請專利範圍第5項所述之方法，其中該第四硬遮罩之上表面係與該第五硬遮罩之上表面齊平。
  7. 如申請專利範圍第5項所述之方法，其中該第四硬遮罩與該第五硬遮罩包含不同材料。
  8. 一種半導體元件，包含：      一基底，該基底上具有一鰭狀結構；      一第一閘極結構設於該鰭狀結構上；      一第一接觸插塞設於該第一閘極結構旁；以及      一第一硬遮罩設於該第一接觸插塞上。
  9. 如申請專利範圍第8項所述之半導體元件，另包含：      一淺溝隔離環繞該鰭狀結構；      一第二閘極結構設於該淺溝隔離上；      一第一側壁子設於該第一閘極結構旁以及一第二側壁子設於該第二閘極結構旁；以及      一層間介電層設於該第二閘極結構旁之該淺溝隔離上。
  10. 如申請專利範圍第9項所述之半導體元件，另包含：      一第三閘極結構設於該鰭狀結構上；以及      一第三側壁子設於該第三閘極結構旁，其中該第一接觸插塞接觸該第一側壁子及該第三側壁子。
  11. 如申請專利範圍第8項所述之半導體元件，另包含：      一第二硬遮罩設於該第一閘極結構上，其中該第二硬遮罩之上表面與該第一硬遮罩之上表面齊平。
  12. 如申請專利範圍第11項所述之半導體元件，其中該第一硬遮罩及該第二硬遮罩包含不同材料。
  13. 如申請專利範圍第8項所述之半導體元件，另包含：      一介電層設於該第一閘極結構上；以及      一第二接觸插塞設於該介電層及該第一硬遮罩中並接觸該第一接觸插塞。
  14. 如申請專利範圍第13項所述之半導體元件，其中該介電層及該第一硬遮罩包含相同材料。
  15. 如申請專利範圍第13項所述之半導體元件，其中該第二接觸插塞直接接觸該第一硬遮罩。
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