CN108933083B - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN108933083B
CN108933083B CN201710364138.3A CN201710364138A CN108933083B CN 108933083 B CN108933083 B CN 108933083B CN 201710364138 A CN201710364138 A CN 201710364138A CN 108933083 B CN108933083 B CN 108933083B
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CN108933083A (zh
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Abstract

本发明提供一种半导体结构及其形成方法，所述形成方法包括：提供基底，所述基底包括用于形成第一器件的第一区域、用于形成第二器件的第二区域以及位于第一区域与第二区域之间的过渡区；在所述基底上形成第一功函数层；刻蚀去除过渡区基底上的第一功函数层；在位于所述过渡区的基底以及第二区域第一功函数层上形成硬掩膜；以所述硬掩膜为掩膜去除位于第一区域的第一功函数层；去除所述硬掩膜；在所述基底以及第一功函数层上形成第二功函数层。本发明形成的半导体结构的电学性能得到提高。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体制造技术领域，特别涉及一种半导体结构及其形成方法。
背景技术
随着半导体技术的飞速发展，半导体器件的特征尺寸不断缩小，使得集成电路的集成度越来越高，这对器件的性能也提出了更高的要求。
目前，随着金属-氧化物半导体场效应晶体管(MOSFET)的尺寸不断变小。为了适应工艺节点的减小，只能不断缩短MOSFET场效应管的沟道长度。沟道长度的缩短具有增加芯片的管芯密度、增加MOSFET场效应管的开关速度等好处。
然而，随着器件沟道长度的缩短，器件源极与漏极间的距离也随之缩短，这样一来栅极对沟道的控制能力变差，栅极电压夹断(pinch off)沟道的难度也越来越大，使得亚阀值漏电现象，即短沟道效应(SCE：short-channel effects)成为一个至关重要的技术问题。
因此，为了更好的适应器件尺寸按比例缩小的要求，半导体工艺逐渐开始从平面MOSFET晶体管向具有更高功效的三维立体式的晶体管过渡，如鳍式场效应管(FinFET)。FinFET具有很好的沟道控制能力。
现有技术形成的半导体结构的电学性能有待提高。
发明内容
本发明解决的问题是提供一种半导体结构及其形成方法，提高半导体结构的电学性能。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：提供基底，所述基底包括用于形成第一器件的第一区域、用于形成第二器件的第二区域以及位于第一区域与第二区域之间的过渡区；在所述基底上形成第一功函数层；刻蚀去除过渡区基底上的第一功函数层；在位于所述过渡区的基底以及第二区域第一功函数层上形成硬掩膜；以所述硬掩膜为掩膜去除位于第一区域的第一功函数层；去除所述硬掩膜；在所述基底以及第一功函数层上形成第二功函数层。
可选的，刻蚀去除过渡区基底上的第一功函数层的步骤包括：在所述第一功函数层上形成保护层；在所述保护层上形成图形层；以所述图形层为掩膜刻蚀去除过渡区的保护层和第一功函数层；去除所述图形层和保护层。
可选的，所述保护层的材料为多晶Si或者非晶Si中的一种或者多种。
可选的，去除所述保护层的工艺为：湿法刻蚀工艺或者干法刻蚀工艺。
可选的，以所述图形层为掩膜刻蚀所述保护层和第一功函数层的工艺为干法刻蚀工艺。
可选的，去除所述图形层的工艺为灰化工艺。
可选的，所述过渡区的宽度在36纳米至86纳米范围内。
可选的，所述第一器件与所述第二器件的导电类型不同。
可选的，所述第一器件为NMOS器件，所述第二器件为PMOS器件。
可选的，所述第一功函数层的材料为：TiN、TaN或者TiSiN中的一种或者多种。
可选的，所述第一功函数层的厚度在25埃至50埃范围内。
可选的，所述第二功函数层的材料为：TiAl、Al、TiC或者TiCAl中的一种或者多种。
可选的，所述第二功函数层的厚度在30埃至60埃范围内。
可选的，所述基底包括：衬底以及位于衬底上的多个分立的鳍部。
相应地，本发明还提供一种半导体结构，包括：基底，所述基底包括用于形成第一器件的第一区域、用于形成第二器件的第二区域以及位于第一区域与第二区域之间的过渡区；第一功函数层，位于第二区域的基底上；第二功函数层，位于所述基底以及第一功函数层上。
可选的，所述第一器件与所述第二器件的导电类型不同。
与现有技术相比，本发明的技术方案具有以下优点：
通过先刻蚀去除过渡区基底上的第一功函数层，能够使得所述过渡区将所述第一区域和第二区域隔开，即将所述第一器件与第二器件断开。后续在去除位于第一区域的第一功函数层时，由于所述第一区域和第二区域隔开，同时通过所述硬掩膜保护过渡区的基底以及位于第二区域的第一功函数层，使得去除位于第一区域第一功函数层的去除工艺对所述过渡区和第二区域产生的不良影响小。具体地，在半导体制造技术领域，通常采用湿法刻蚀工艺去除位于第一区域的第一功函数层，由于所述第一区域和第二区域之间通过所述过渡区隔开，使得所述湿法刻蚀的刻蚀溶液不会刻蚀掉位于第二区域的第一功函数层，从而提高了所述第一功函数层的质量。后续再在所述基底以及第一功函数层上形成第二功函数层，所述第一功函数层质量的提高，相应地也改善了所述第二功函数层的质量。综上，所述第一功函数层以及第二功函数层质量的提高有利于其各自发挥调节第一器件以及第二器件阈值电压的作用，从而使得所述半导体结构的电学性能得到改善。
可选方案中，刻蚀去除过渡区基底上的第一功函数层的步骤中，所述保护层用于保护所述第一功函数层，具体地，由于所述保护层位于所述第一功函数层和图形层之间，起到隔离所述第一功函数层与图形层的作用，后续在去除所述图形层的过程中，通常采用灰化工艺去除所述图形层，由于灰化工艺所述图形层中O、N、H等原子能够与所述第一功函数层发生不良化学反应，所述保护层可以避免所述第一功函数层与所述图形层相接触，从而缓解了所述第一功函数层发生不良化学反应的问题，进而提高了所述第一功函数层的质量。
附图说明
图1至图5是半导体结构形成过程的结构示意图；
图6至图13是本发明实施例半导体结构形成过程的结构示意图。
具体实施方式
根据背景技术形成的半导体结构的电学性能有待提高。现结合半导体结构的形成过程对半导体结构电学性能有待提高的原因进行分析。
图1至图5是半导体结构形成过程的结构示意图。
参考图1，提供衬底100，所述衬底100上具有多个分立的鳍部110，所述衬底100包括用于形成第一器件的第一区域I和用于形成第二器件的第二区域II；在所述鳍部110露出的衬底100上形成隔离层120；在所述鳍部110上形成界面介质层122；在所述界面介质层122以及鳍部110露出的隔离层120上形成高K介质层121。
参考图2，在所述高K介质层121上形成第一功函数层130。
参考图3，在位于第二区域II的鳍部110以及隔离层120上形成掩膜层140。
参考图4，以所述掩膜层140为掩膜刻蚀去除位于第一区域I的第一功函数层130。
参考图5，去除所述硬掩膜140，在位于第一区域I的高K介质层121以及位于第二区域II的第一功函数层130上形成第二功函数层150。
经分析发现，导致所述半导体结构电学性能有待提高的原因包括：先在位于第二区域II的鳍部110以及隔离层120上形成掩膜层140，再以所述掩膜层140为掩膜刻蚀去除位于第一区域I的第一功函数层130。通常采用湿法刻蚀工艺去除位于第一区域I的第一功函数层130，由于所述掩膜层140位于第二区域II的第一功函数层130上，即在所述掩膜层140和高K介质层121之间还具有所述第一功函数层130，在进行湿法刻蚀工艺的过程中，刻蚀溶液同样容易对位于第二区域II的第一功函数130层造成侵蚀问题(如图4中A所示)，从而导致位于第二区域II的第一功函数层130的质量差。而且，由于受所述刻蚀溶液的侵蚀，也会造成第一区域I和第二区域II之间区域高K介质层121的表面晶格缺陷多，从而也导致后续位于第一区域I的第二功函数层150的质量差，因此，所述半导体结构的电学性能有待提高。
为了解决上述问题，本发明实施例中通过先刻蚀去除过渡区基底上的第一功函数层，即先将第一区域和第二区域通过所述过渡区进行隔开，再通过所述硬掩膜将位于过渡区的基底以及位于第二区域的第一功函数层进行保护，从而减轻去除位于第一区域第一功函数层的去除工艺对所述过渡区以及第二区域产生的不良影响，从而提高了所述第一功函数层和第二功函数层的质量，进而改善了所述半导体结构的电学性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图6至图13是本发明实施例半导体结构形成过程的结构示意图。
参考图6，提供基底，所述基底包括衬底200以及位于衬底200上的多个分立的鳍部210；所述衬底200包括用于形成第一器件的第一区域I、用于形成第二器件的第二区域II以及位于第一区域I与第二区域II之间的过渡区III；在所述衬底200上还形成有隔离结构220；在所述鳍部210上还形成有界面介质层222；在所述鳍部210露出的隔离结构220以及界面介质层222上还形成有高K介质层221。
本实施例中，形成的所述半导体结构为鳍式场效应管。在本发明其他实施例中，形成的半导体结构还可以为平面结构，相应的，所述基底为平面衬底。
所述第一器件与所述第二器件的导电类型不同。本实施例中，所述第一器件为NMOS器件，所述第二器件为PMOS器件。在本发明其他实施例中，还可以为：所述第一器件为PMOS器件，所述第二器件为NMOS器件。
本实施例中，所述衬底200的材料为Si。在本发明其他实施例中，所述衬底的材料还可以为Ge、SiGe、SiC、GaAs或InGa。在其他实施例中，所述衬底还可以为绝缘体上的Si衬底或者绝缘体上的Ge衬底。
本实施例中，所述鳍部210的材料为Si。在本发明其他实施例中，所述鳍部的材料还可以为Ge、SiGe、SiC、GaAs或InGa。
本实施例中，所述隔离结构220可以起到电学隔离相邻所述鳍部210的作用。所述隔离结构220的材料为SiO2。在本发明其他实施例中，所述隔离结构的材料还可以为SiN或SiON。
本实施例中，所述界面介质层222的材料为SiO2或SiON中的一种或者多种。形成所述界面介质层222的工艺为氧化工艺。
本实施例中，所述高K介质层221的材料为高K介电常数的材料，具体为：HfO2、TaO2或者HfLaO中的一种或者多种。
参考图7，在所述高K介质层221上形成第一功函数层230。
本实施例中，所述第一功函数层230用于调节后续第二器件的阈值电压。所述第一功函数层230的材料为：TiN、TaN或者TiSiN中的一种或者多种。
本实施例中，所述第一功函数层230的厚度根据所述第二器件需求来定。所述第一功函数层230的厚度既不能过大也不能过小。若所述第一功函数层230的厚度过大或者所述第一功函数层230的厚度过小，则会导致所述第一功函数层230与所述第二器件之间发生电性失配问题。因此，所述第一功函数层230的厚度在25埃至50埃范围内。
本实施例中，形成所述第一功函数层230的工艺为：原子层沉积工艺或者化学气相沉积工艺。
结合参考图8至图10，刻蚀去除过渡区III基底上的第一功函数层230。
以下将结合附图对刻蚀去除过渡区III基底上第一功函数层230的步骤做详细说明。
参考图8，在所述第一功函数层230上形成保护层240。
本实施例中，所述保护层240具有隔离所述第一功函数层230与后续图形层的作用。所述保护层240的材料为多晶Si或者非晶Si中的一种或者多种。
参考图9，在所述保护层240上形成图形层250。
本实施例中，所述图形层250作为后续刻蚀去除过渡区III保护层240、第一功函数层230和高K介质层221的掩膜，起到定义所述过渡区III尺寸的作用。所述图形层250的材料为光刻胶。
本实施例中，所述图形层250定义所述过渡区III的尺寸既不能过大也不能过小。即在沿垂直于鳍部210延伸方向上，所述过渡区III的宽度既不能过大也不能过小。若所述过渡区III的宽度过大，则会造成半导体结构集成密度低；若所述过渡区III的宽度过小，则会造成所述第一区域I和第二区域II隔开的效果差，使得后续在去除位于第一区域I第一功函数层230时容易对位于第二区域II第一功函数层230产生不良影响。因此，在沿垂直于鳍部210延伸方向上，所述过渡区III的宽度在36纳米至86纳米范围内。
参考图10，以所述图形层250(参考图9)为掩膜刻蚀去除过渡区III的保护层240(参考图9)、第一功函数层230和高K介质层221；去除所述图形层250和保护层240。
本实施例中，由于所述保护层240起到隔离所述第一功函数层230与图形层250的作用，在去除所述图形层250和保护层240的过程中，通常采用灰化工艺去除所述图形层250，由于灰化工艺所述图形层中的O、N、H等原子能够与所述第一功函数层230发生不良化学反应，通过所述保护层240可以避免所述第一功函数层230与所述图形层250相接触，从而缓解了所述第一功函数层230发生不良化学反应的问题，进而提高了所述第一功函数层230的质量。
本实施例中，以所述图形层250为掩膜刻蚀去除过渡区III的保护层240、第一功函数层230和高K介质层221的工艺为干法刻蚀工艺。具体地，所述干法刻蚀工艺的参数包括：刻蚀气体为CF4、SF6、Cl2和O2，其中CF4的气体流量为10sccm至500sccm，SF6的气体流量为20sccm至300sccm，Cl2的气体流量为6sccm至120sccm，O2的气体流量为1sccm至90sccm，压力为1mtorr至350mtorr，功率为100w至500w。
本实施例中，去除所述保护层240的步骤与去除所述图形层250的步骤分开进行，即先去除所述图形层250，再去除所述保护层240。其中，去除所述图形层250的工艺为灰化工艺。去除所述保护层240的工艺为：湿法刻蚀工艺或者干法刻蚀工艺。
参考图11，在位于所述过渡区III的隔离结构220以及第二区域II的第一功函数层230上形成硬掩膜260。
本实施例中，所述硬掩膜260用于保护所述过度区III的隔离结构220以及第二区域II的第一功函数层230。所述硬掩膜260的材料为：SiN、SiCN、SiBN、SiOCN或者SiON中的一种或者多种。
参考图12，以所述硬掩膜260为掩膜去除位于第一区域I的第一功函数层230。
本实施例中，通过以所述图形层250(参考图9)为掩膜刻蚀去除过渡区III的保护层240(参考图9)、第一功函数层230和高K介质层221，从而使得所述第一区域I和第二区域II相互隔开，即所述第一器件和第二器件之间相互断开。由于第二区域II与第一区域I通过过渡区III相互隔开，且所述第二区域II和过渡区III通过所述硬掩膜260得以保护，在去除位于第一区域I第一功函数层230的去除工艺中，所述去除工艺不容易对所述过渡区III以及第二区域II第一功函数层230造成不良影响，从而使得所述第一功函数层230和后续第二功函数层270的质量得到提高，进而使得所述第一功函数层230以及第二功函数层270能够各自发挥调节第一器件以及第二器件阈值电压的作用，因此，所述半导体结构的电学性能得到改善。
本实施例中，以所述硬掩膜260为掩膜去除位于第一区域I的第一功函数层230的工艺为湿法刻蚀工艺。具体地，由于所述第一区域I和第二区域II通过所述第三区域III隔开，所述湿法刻蚀工艺的刻蚀溶液不容易对所述位于第二区域II的第一功函数层230造成侵蚀影响，从而提高了所述第一功函数层230的质量。在后续工艺中，还会在位于第一区域I的高K介质层221、位于第三区域III的隔离结构220以及位于第二区域II的第一功函数层230上形成第二功函数层，由于所述第一功函数层230的质量得到提高，相应地也改善了后续形成的第二功函数层质量。
参考图13，去除所述硬掩膜260，在位于所述第一区域I的高K介质层221、位于第三区域III的隔离结构220、以及位于第二区域II的第一功函数层230上形成第二功函数层270。
本实施例中，所述第二功函数层270用于调节第一器件的阈值电压。所述第二功函数层270的材料为：TiAl、Al、TiC或者TiCAl中的一种或者多种。
本实施例中，所述第二功函数层270的厚度根据所述第一器件需求来定。所述第二功函数层270的厚度既不能过大也不能过小。若所述第二功函数层270的厚度过大或者所述第二功函数层270的厚度过小，则会导致所述第二功函数层270与所述第一器件之间发生电性失配问题。因此，所述第二功函数层270的厚度在30埃至60埃范围内。
本实施例中，形成所述第二功函数层270的工艺为：原子层沉积工艺或者化学气相沉积工艺。
相应地，本发明还提供一种半导体结构，参考图13，包括：基底，所述基底包括衬底200以及位于衬底200上的多个分立的鳍部210，所述衬底200包括用于形成第一器件的第一区域I、用于形成第二器件的第二区域II以及位于第一区域I与第二区域II之间的过渡区III；隔离结构220，位于所述鳍部210露出的衬底200上；界面介质层222，位于所述鳍部210上；高K介质层221，位于所述鳍部210露出的隔离结构220以及界面介质层222上；第一功函数层230，位于第二区域II的高K介质层221上；第二功函数层270，位于第一区域I的高K介质层221、过渡区III的隔离结构220以及第二区域II的第一功函数层230上。
本实施例中，所述过渡区III将第一区域I和第二区域II相隔开，使得所述第一功函数层230和第二功函数层270的质量高，从而有利于所述第一功函数层230调节第二器件的阈值电压，所述第二功函数层270调节第一器件的阈值电压，进而改善了所述半导体结构的电学性能。
本实施例中，所述第一器件与所述第二器件的导电类型不同。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (14)

1.一种半导体结构的形成方法，其特征在于，包括：
提供基底，所述基底包括用于形成第一器件的第一区域、用于形成第二器件的第二区域以及位于第一区域与第二区域之间的过渡区；
在所述基底上形成第一功函数层；
采用干法刻蚀工艺，刻蚀去除过渡区基底上的第一功函数层；
在位于所述过渡区的基底以及第二区域第一功函数层上形成硬掩膜；
以所述硬掩膜为掩膜去除位于第一区域的第一功函数层；
去除所述硬掩膜；
在所述基底以及第一功函数层上形成第二功函数层。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，刻蚀去除过渡区基底上的第一功函数层的步骤包括：
在所述第一功函数层上形成保护层；
在所述保护层上形成图形层；
以所述图形层为掩膜刻蚀去除过渡区的保护层和第一功函数层；
去除所述图形层和保护层。
3.如权利要求2所述的半导体结构的形成方法，其特征在于，所述保护层的材料为多晶Si或者非晶Si中的一种或者多种。
4.如权利要求3所述的半导体结构的形成方法，其特征在于，去除所述保护层的工艺为：湿法刻蚀工艺或者干法刻蚀工艺。
5.如权利要求2所述的半导体结构的形成方法，其特征在于，以所述图形层为掩膜刻蚀所述保护层的工艺为干法刻蚀工艺。
6.如权利要求2所述的半导体结构的形成方法，其特征在于，去除所述图形层的工艺为灰化工艺。
7.如权利要求1所述的半导体结构的形成方法，其特征在于，所述过渡区的宽度在36纳米至86纳米范围内。
8.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一器件与所述第二器件的导电类型不同。
9.如权利要求8所述的半导体结构的形成方法，其特征在于，所述第一器件为NMOS器件，所述第二器件为PMOS器件。
10.如权利要求9所述的半导体结构的形成方法，其特征在于，所述第一功函数层的材料为：TiN、TaN或者TiSiN中的一种或者多种。
11.如权利要求10所述的半导体结构的形成方法，其特征在于，所述第一功函数层的厚度在25埃至50埃范围内。
12.如权利要求9所述的半导体结构的形成方法，其特征在于，所述第二功函数层的材料为：TiAl、Al、TiC或者TiCAl中的一种或者多种。
13.如权利要求12所述的半导体结构的形成方法，其特征在于，所述第二功函数层的厚度在30埃至60埃范围内。
14.如权利要求1所述的半导体结构的形成方法，其特征在于，所述基底包括：衬底以及位于衬底上的多个分立的鳍部。
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