JP5297859B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5297859B2 JP5297859B2 JP2009078122A JP2009078122A JP5297859B2 JP 5297859 B2 JP5297859 B2 JP 5297859B2 JP 2009078122 A JP2009078122 A JP 2009078122A JP 2009078122 A JP2009078122 A JP 2009078122A JP 5297859 B2 JP5297859 B2 JP 5297859B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor device
- wafer substrate
- semiconductor
- chamfered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 101
- 239000000758 substrate Substances 0.000 claims description 46
- 238000007789 sealing Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 9
- 230000002209 hydrophobic effect Effects 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 239000008188 pellet Substances 0.000 description 35
- 238000004519 manufacturing process Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000002265 prevention Effects 0.000 description 7
- 238000005453 pelletization Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Dicing (AREA)
Description
以下、参考形態の例を付記する。
1.ウェーハ基板と、
前記ウェーハ基板の表面に配列されて形成されている半導体素子と、
前記ウェーハ基板の表面に形成されて前記半導体素子を密閉している第一の絶縁膜と、
前記ウェーハ基板の表面に形成されて前記第一の絶縁膜を密閉している第二の絶縁膜と、を有し、
前記第一の絶縁膜は、角部が面取りされた多角形の平面形状に形成されている半導体装置。
2.前記第二の絶縁膜は、角部が面取りされた多角形の平面形状に形成されている1.に記載の半導体装置。
3.前記第一の絶縁膜の角部の内側に形成されているボンディングパッドを、さらに有し、
前記ボンディングパッドは、前記第一の絶縁膜の面取りに対応した部分が面取りされた多角形の平面形状に形成されている1.または2.に記載の半導体装置。
4.前記第一の絶縁膜は、角部が面取りされた矩形の平面形状に形成されている1.ないし3.の何れか一項に記載の半導体装置。
5.前記第一の絶縁膜は、親水性の材料で形成されており、
前記第二の絶縁膜は、疎水性の材料で形成されている1.ないし4.の何れか一項に記載の半導体装置。
6.前記第一の絶縁膜は、酸化膜で形成されており、
前記第二の絶縁膜は、窒化膜で形成されている1.ないし5.の何れか一項に記載の半導体装置。
7.ウェーハ基板の表面のペレット形成領域ごとに複数の半導体素子を配列させて形成し、
前記ウェーハ基板の表面に前記半導体素子を密閉する第一の絶縁膜を角部が面取りされた多角形の平面形状に形成し、
前記ウェーハ基板の表面にスクライブ領域を介して配列されるように第二の絶縁膜を形成して前記第一の絶縁膜を密閉する、半導体装置の製造方法。
2 半導体ペレット
3 チッピング防止壁
4 スクライブ領域
11 ウェーハ基板
12 半導体ペレット
14 スクライブ領域
15 絶縁膜
100 半導体装置
101 ウェーハ基板
102 ペレット形成領域
104 スクライブ領域
105A 第一の絶縁膜
105B 第二の絶縁膜
106 ボンディングパッド
107 半導体素子
110 半導体ペレット
Claims (4)
- ウェーハ基板と、
前記ウェーハ基板の表面に配列されて形成されている半導体素子と、
前記ウェーハ基板の表面に形成されて前記半導体素子を密閉している第一の絶縁膜と、
前記ウェーハ基板の表面に形成されて前記第一の絶縁膜を密閉している第二の絶縁膜と、を有し、
前記第一の絶縁膜は、角部が面取りされた多角形の平面形状に形成され、
前記第二の絶縁膜は、角部が面取りされた多角形の平面形状に形成され、
前記第一の絶縁膜の角部の内側に形成されているボンディングパッドを、さらに有し、
前記ボンディングパッドは、前記第一の絶縁膜の面取りに対応した部分が面取りされた多角形の平面形状に形成され、
前記第一の絶縁膜は、前記ウェーハ基板の表面に接して形成され、
前記第二の絶縁膜は、前記ウェーハ基板の表面と前記第一の絶縁膜とに接して、前記第一の絶縁膜を密閉している半導体装置。 - 前記第一の絶縁膜は、角部が面取りされた矩形の平面形状に形成されている請求項1に記載の半導体装置。
- 前記第一の絶縁膜は、親水性の材料で形成されており、
前記第二の絶縁膜は、疎水性の材料で形成されている請求項1または2に記載の半導体装置。 - 前記第一の絶縁膜は、酸化膜で形成されており、
前記第二の絶縁膜は、窒化膜で形成されている請求項1ないし3の何れか一項に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009078122A JP5297859B2 (ja) | 2009-03-27 | 2009-03-27 | 半導体装置 |
US12/659,762 US8143730B2 (en) | 2009-03-27 | 2010-03-19 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009078122A JP5297859B2 (ja) | 2009-03-27 | 2009-03-27 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010232411A JP2010232411A (ja) | 2010-10-14 |
JP5297859B2 true JP5297859B2 (ja) | 2013-09-25 |
Family
ID=42783122
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009078122A Expired - Fee Related JP5297859B2 (ja) | 2009-03-27 | 2009-03-27 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8143730B2 (ja) |
JP (1) | JP5297859B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI467757B (zh) | 2013-08-02 | 2015-01-01 | Chipbond Technology Corp | 半導體結構 |
JP2016171183A (ja) * | 2015-03-12 | 2016-09-23 | 日本電信電話株式会社 | 半導体集積回路 |
JP7045271B2 (ja) * | 2018-06-28 | 2022-03-31 | エイブリック株式会社 | 半導体装置及び半導体チップ |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63186448A (ja) * | 1987-01-28 | 1988-08-02 | Mitsubishi Electric Corp | 半導体装置 |
JPH08293476A (ja) | 1995-04-21 | 1996-11-05 | Hitachi Ltd | 半導体集積回路装置の製造方法および半導体ウエハならびにフォトマスク |
JP3514361B2 (ja) * | 1998-02-27 | 2004-03-31 | Tdk株式会社 | チップ素子及びチップ素子の製造方法 |
WO2001020661A1 (fr) * | 1999-09-10 | 2001-03-22 | Nitto Denko Corporation | Plaquette semi-conductrice dotee d'un film anisotrope et procede de fabrication correspondant |
JP4979154B2 (ja) * | 2000-06-07 | 2012-07-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US6908784B1 (en) * | 2002-03-06 | 2005-06-21 | Micron Technology, Inc. | Method for fabricating encapsulated semiconductor components |
JP2005142553A (ja) * | 2003-10-15 | 2005-06-02 | Toshiba Corp | 半導体装置 |
JP2006140404A (ja) * | 2004-11-15 | 2006-06-01 | Renesas Technology Corp | 半導体装置 |
JP2008028243A (ja) | 2006-07-24 | 2008-02-07 | Toshiba Corp | 半導体装置 |
-
2009
- 2009-03-27 JP JP2009078122A patent/JP5297859B2/ja not_active Expired - Fee Related
-
2010
- 2010-03-19 US US12/659,762 patent/US8143730B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2010232411A (ja) | 2010-10-14 |
US20100244285A1 (en) | 2010-09-30 |
US8143730B2 (en) | 2012-03-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10211165B2 (en) | Method of manufacturing semiconductor device and semiconductor device | |
US10461195B2 (en) | Semiconductor devices | |
CN101414584A (zh) | 半导体器件和制造半导体器件的方法 | |
CN103065952B (zh) | 非易失性存储器件及其制造方法 | |
US10510724B2 (en) | Semiconductor device package | |
JP5297859B2 (ja) | 半導体装置 | |
TW201820623A (zh) | 半導體裝置 | |
US20120286397A1 (en) | Die Seal for Integrated Circuit Device | |
US20180012853A1 (en) | Chip package and manufacturing method thereof | |
CN109962039A (zh) | 一种半导体器件及电子装置 | |
US7670878B2 (en) | Method for manufacturing semiconductor package | |
WO2022183647A1 (zh) | 半导体结构及半导体结构制作方法 | |
TWI720394B (zh) | 半導體裝置及其製造方法 | |
CN103435000A (zh) | 集成mems器件的传感器的晶圆级封装结构及封装方法 | |
US9892989B1 (en) | Wafer-level chip scale package with side protection | |
US9275963B2 (en) | Semiconductor structure having stage difference surface and manufacturing method thereof | |
TWI776569B (zh) | 半導體裝置及其製造方法 | |
CN114497176A (zh) | 半导体装置及半导体晶片 | |
TW201719744A (zh) | 囊封的半導體封裝以及其製造方法 | |
CN112530982B (zh) | Cmos图像传感器、封边圈结构及其形成方法 | |
JP4116962B2 (ja) | 半導体装置及びその製造方法 | |
US10833118B2 (en) | Chip package and manufacturing method thereof | |
JP2009076782A (ja) | 半導体基板、その製造方法、および半導体チップ | |
JP6406138B2 (ja) | 半導体装置およびその製造方法 | |
CN103219304A (zh) | 半导体晶圆级封装结构及其制备方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20111109 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130221 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130226 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130417 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130604 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130617 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5297859 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |