WO2022183647A1 - 半导体结构及半导体结构制作方法 - Google Patents

半导体结构及半导体结构制作方法 Download PDF

Info

Publication number
WO2022183647A1
WO2022183647A1 PCT/CN2021/104791 CN2021104791W WO2022183647A1 WO 2022183647 A1 WO2022183647 A1 WO 2022183647A1 CN 2021104791 W CN2021104791 W CN 2021104791W WO 2022183647 A1 WO2022183647 A1 WO 2022183647A1
Authority
WO
WIPO (PCT)
Prior art keywords
wall
layer
sub
sealing
metal
Prior art date
Application number
PCT/CN2021/104791
Other languages
English (en)
French (fr)
Inventor
王蒙蒙
黄信斌
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/648,130 priority Critical patent/US20220278054A1/en
Publication of WO2022183647A1 publication Critical patent/WO2022183647A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

Definitions

  • Embodiments of the present application relate to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for fabricating the semiconductor structure.
  • Chips made on wafers need to be cut and packaged before they can be used in electronic equipment. Cracks are prone to occur during the cutting process of the wafer, and the cracks are prone to extend to the inside of the chip, which is likely to cause chip failure.
  • Embodiments of the present application provide a semiconductor structure and a method for fabricating the semiconductor structure, so as to solve the technical problem that cracks generated during the cutting process of the wafer extend to the chip structure, which easily causes the chip structure to fail.
  • embodiments of the present application provide a semiconductor structure, including: a substrate, a chip structure and a sealing structure on the substrate; the sealing structure includes a metal wall and a barrier wall on top of the metal wall wherein, both the metal wall and the blocking wall are arranged around the chip structure.
  • an embodiment of the present application also provides a method for fabricating a semiconductor structure, including:
  • the sealing structure includes a metal wall and a blocking wall on the top of the metal wall;
  • both the metal wall and the blocking wall are arranged around the chip structure.
  • a chip structure and a sealing structure are arranged on the substrate, and the sealing structure includes a metal wall and a blocking wall on top of the metal wall, and both the metal wall and the blocking wall surround Chip structure settings.
  • the blocking wall can prevent cracks from extending to the chip structure, thereby preventing the chip structure from failing.
  • FIG. 1 is a top view of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 2 is a cross-sectional view 1 of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 3 is a second cross-sectional view of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 4 is a flowchart of a method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram after forming a top metal layer in a method for fabricating a semiconductor structure provided by an embodiment of the present application;
  • FIG. 6 is a schematic structural diagram after forming a metal block in a method for fabricating a semiconductor structure provided by an embodiment of the present application;
  • FIG. 7 is a schematic structural diagram of a semiconductor structure fabrication method provided by an embodiment of the present application after a capping layer is formed;
  • FIG. 8 is a schematic structural diagram after forming a photoresist layer in a method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a semiconductor structure fabrication method provided by an embodiment of the present application after forming a barrier groove
  • FIG. 10 is a schematic structural diagram after forming a barrier wall in the method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • the embodiments of the present application provide a semiconductor structure, by disposing a blocking wall at the top of the metal wall; when a crack is generated by wafer cutting, the blocking wall can prevent the crack from reaching the chip structure on the interlayer dielectric layer on the top of the metal wall. extension to avoid failure of the chip structure.
  • the present embodiment provides a semiconductor structure including a substrate 11, a chip structure 10 and a sealing structure 20 on the substrate 11.
  • the substrate 11 may include a silicon wafer, a germanium wafer, a gallium nitride wafer, Gallium germanium wafer or SOI wafer, etc.
  • the chip structure 10 is disposed on the substrate. This embodiment does not limit the chip structure 10.
  • the chip structure 10 corresponding to different chip types may be different.
  • connection structure; the chip structure 10 of the dynamic random access memory chip may include a device structure in the front stage, a capacitor structure in the middle stage, and a metal interconnection structure in the back stage.
  • the device structures include planar transistors, buried gate transistors, fin transistors, gate-all-around transistors, and the like.
  • the sealing structure 20 is disposed around the periphery of the chip structure 10 , and a dicing line 21 is formed between the sealing structures 20 .
  • FIG. 2 is a cross-sectional view between adjacent sealing structures 20 .
  • the sealing structure 20 includes a metal wall 40 and a blocking wall 501 located on top of the metal wall 40 .
  • the metal wall 40 and the blocking wall 501 are disposed around the chip structure 10 .
  • the semiconductor structure further includes an interlayer dielectric layer and an etch stop layer, the metal walls 40 and the barrier walls 501 are located in the interlayer dielectric layer and the etch stop layer, and the interlayer dielectric layer, the etch stop layer and the metal wall
  • the body 40 can prevent the outside air, water vapor, etc. from contacting the chip structure 10 , so as to protect the realization of the chip structure 10 .
  • the interlayer dielectric layer and the etch stop layer may be composed of insulating materials.
  • the material of the interlayer dielectric layer may be silicon oxide.
  • the interlayer dielectric layer in this embodiment may also be made of silicon oxynitride, silicon nitride, or the like.
  • the material of the metal wall 40 may include copper, tungsten, aluminum, etc., and the metal wall 40 is not limited in this embodiment.
  • the material of the etch stop layer can be silicon oxynitride, silicon carbonitride, etc. It should be noted that the materials of the interlayer dielectric layer and the etch stop layer are different.
  • the metal wall 40 may include a plurality of sub-walls stacked in sequence along a direction perpendicular to the substrate, and the projections of adjacent sub-wall layers on the substrate at least partially overlap. It should be noted that each sub-wall is made of metal material, and the material of each sub-wall may be the same or different, which is not limited in this embodiment. In this way, the metal wall 40 is formed by stacking a plurality of sub-walls, which can reduce the manufacturing difficulty of the metal wall 40; Partial joints can improve the sealing effect.
  • the interlayer dielectric layer includes a plurality of sub-layer dielectric layers arranged in sequence along the direction perpendicular to the substrate, and each sub-layer dielectric layer is disposed on the same layer as at least one sub-wall; during manufacture, a sub-layer can be formed first.
  • the interlayer dielectric layer is formed, and then a slot is formed on the sub-layer dielectric layer, and a sub-wall is formed in the slot; and so on, to form the sealing structure 20; of course, a metal layer can also be formed first, and part of the metal layer can be removed to form a sub-wall Then, a sub-layer dielectric layer disposed on the same layer as the sub-wall is formed; in this way, the sealing structure 20 can also be formed. Further, an etch stop layer is also arranged between the sub-layer dielectric layers.
  • each sub-wall is disposed on the same layer as a metal layer in the chip structure 10 .
  • the metal layer and the sub-walls in the chip structure 10 can be formed at the same time, which simplifies the fabrication steps of the semiconductor structure, and further reduces the fabrication difficulty of the semiconductor structure.
  • each sub-wall is disposed on the same layer as a metal layer in the chip structure 10
  • the materials of the sub-layer dielectric layers constituting the interlayer dielectric layer may be the same, partially the same or completely different, forming the metal wall.
  • the materials of the sub-walls of 40 may also be the same, partially the same or completely different.
  • the metal wall 40 may include six sub-walls that are sequentially stacked in a direction away from the base (not shown in the figure), which are the first sub-walls 4011 respectively. , the second sub-wall 4012, the third sub-wall 4013, the fourth sub-wall 4014, the fifth sub-wall 4015 and the sixth sub-wall 4016; wherein the first sub-wall 4011 and the fifth sub-wall
  • the 4015 may be composed of tungsten
  • the second sub-wall 4012, the third sub-wall 4013, and the fourth sub-wall 4014 may be composed of copper
  • the sixth sub-wall 4016 may be composed of aluminum.
  • barrier layers 4017 are provided on the sides of the first sub-wall 4011 and the fifth sub-wall 4015 that are perpendicular to the base and on the sides close to the base. Similarly, the sixth sub-wall 4016 is parallel to the base. Barrier layers 4017 are also provided on the side surfaces; for example, the material of the barrier layers 4017 may include titanium or titanium nitride.
  • the interlayer dielectric layer may include a first sub-interlayer dielectric layer 601, a second sub-interlayer dielectric layer 602 and a third sub-layer dielectric layer 603, and the etch stop layer may include a first sub-etch stop layer 701 and a second sub-layer dielectric layer 601 Sub-etch stop layer 702 .
  • the first sub-etch stop layer 701 is located between the first sub-layer dielectric layer 601 and the second sub-layer dielectric layer 602, and the second sub-etch stop layer 702 is located between the second sub-layer dielectric layer 602 and the second sub-layer dielectric layer 602. between the three sub-layer dielectric layers 603 .
  • the metal wall 40 is arranged in the interlayer dielectric layer, that is to say, while the interlayer dielectric layer is wrapped around the side wall of the metal wall 40 perpendicular to the substrate, at least part of the interlayer dielectric layer also covers the metal wall
  • the body 40 is on top facing away from the base.
  • the blocking wall 501 is disposed on top of the metal wall 40 . Specifically, the blocking wall 501 is located on the side of the metal wall 40 away from the base, and the blocking wall 501 is disposed facing the top of the metal wall. As shown in FIGS. 2 and 3 , when dicing the wafer to form the kerf 30 on the dicing lane 21 , the blocking wall 501 can prevent the cracks in the interlayer dielectric layer on the side of the metal wall 40 away from the substrate from reaching the chip structure 10 . extension to avoid failure.
  • the bottom end of the blocking wall 501 facing away from the substrate is in contact with the top of at least part of the metal wall 40 to avoid a gap between the blocking wall 501 and the metal wall 40 , and cracks extend to the chip structure 10 along the gap.
  • the barrier wall 501 may be located in the interlayer dielectric layer, that is, the thickness of the barrier wall along the direction perpendicular to the substrate is smaller than the thickness of the interlayer dielectric layer at the top of the metal wall 40 .
  • the thickness of the barrier wall 501 along the direction perpendicular to the substrate is equal to the thickness of the interlayer dielectric layer at the top of the metal wall 40; during manufacture, a barrier groove may be formed on the side of the interlayer dielectric layer away from the substrate. It extends to the top of the blocking wall 501 , and the bottom of the blocking groove is in contact with the top of the metal wall 40 , and the blocking wall 501 is filled in the blocking groove. This arrangement can further prevent the crack from extending to the chip structure 10 along the interlayer dielectric layer on the side of the metal wall 40 away from the substrate when the slit 30 is formed.
  • the blocking wall 501 is disposed at the top of the metal wall 40.
  • the blocking wall 501 covers at least part of the top surface of the metal wall 40, thereby preventing cracks from passing along the blocking wall 501 and the metal wall. 40 extends toward the chip structure 10 , thereby improving the sealing effect on the chip structure 10 .
  • the sixth sub-wall 4016 of the metal wall 40 is located at the top of the metal wall 40, and the projection of the blocking wall 501 on the substrate is located inside the projection of the sixth sub-wall 4016 on the substrate. , so that the blocking wall 501 covers part of the sixth sub-wall 4016 .
  • a plurality of chip structures 10 may be fabricated on a substrate (eg, a silicon wafer) during fabrication, and a sealing structure 20 is formed on the periphery of each semiconductor structure; Dicing is performed to form slits 30 between adjacent sealing structures 20, thereby obtaining a plurality of chips.
  • a substrate eg, a silicon wafer
  • a chip structure 10 and a sealing structure 20 are disposed on the substrate.
  • the sealing structure 20 includes a metal wall 40 and a blocking wall 501 located on top of the metal wall 40.
  • the metal wall 40 and the blocking wall 501 All are arranged around the chip structure 10 .
  • the blocking wall 501 can prevent cracks from extending to the chip structure 10 in the interlayer dielectric layer on the side of the metal wall 40 away from the substrate, thereby preventing the chip structure 10 from failing.
  • the plurality of blocking walls 501 are all located on the top of the same metal wall 40, for example, the plurality of blocking walls 501 are arranged at intervals on the top of the same sixth sub-wall 4016, so as to improve the protection effect at the same time , reducing the occupied area of the sealing structure.
  • the semiconductor structure provided in this embodiment further includes a sealing layer 50 disposed on the side of the sealing structure 20 away from the substrate.
  • the sealing layer 50 covers the sealing structure 20 , which can further improve the protection effect and sealing effect on the chip structure 10 .
  • the sealing layer 50 may be located on the side of the interlayer dielectric layer away from the substrate.
  • sealing layer 50 and the blocking wall 501 may be an integral structure; in this way, the blocking wall 501 and the sealing layer 50 may be formed through the same manufacturing step, which simplifies the manufacturing difficulty of the semiconductor structure.
  • the top surface of the sealing layer 50 located above the blocking wall 501 is higher than the top surface of the sealing layer 50 located above the scribe line 21 .
  • the sealing layer 50 above the barrier wall 501 and the scribe line 21 has a slope. This arrangement can buffer the lateral pressure on the sealing structure when cutting on the cutting track, and improve the stability of the sealing structure.
  • the material of the blocking wall 501 includes an insulating material; for example, the material of the blocking wall 501 may include silicon nitride, silicon oxynitride, and the like. In the implementation manner in which the sealing layer 50 and the blocking wall 501 are integrated, the material of the sealing layer 50 is the same as that of the blocking wall 501 .
  • Embodiments of the present application further provide a method for fabricating a semiconductor structure, which is used to fabricate the semiconductor structure in the above-mentioned embodiments.
  • a chip structure and a sealing structure are provided on the substrate of the semiconductor structure, and the sealing structure includes a metal wall and a The blocking wall, the metal wall and the blocking wall are all arranged around the chip structure.
  • the blocking wall can prevent cracks from extending to the chip structure in the interlayer dielectric layer on the side of the metal wall facing away from the substrate, thereby preventing the chip structure from failing.
  • an embodiment of the present application further provides a method for fabricating a semiconductor structure, including:
  • the substrate may include a silicon wafer, a germanium wafer, a gallium nitride wafer, a gallium germanium wafer, a gallium arsenide wafer, or a SOI wafer and other semiconductor material wafers.
  • the method for fabricating the semiconductor structure provided in this embodiment further includes:
  • S102 forming a chip structure and a sealing structure on the substrate, where the sealing structure includes a metal wall and a blocking wall on top of the metal wall; wherein, the metal wall and the blocking wall are both arranged around the chip structure.
  • a plurality of chip structures arranged at intervals can be formed on the silicon wafer, and a sealing structure is formed on the periphery of each chip structure, and a dicing line is formed between the sealing structures on the periphery of adjacent chip structures.
  • the top of the metal wall is provided with a blocking wall, which can prevent the crack from extending to the chip structure along the side of the metal wall away from the substrate when the wafer is diced, that is, when a slit is formed on the dicing road, thereby avoiding the chip structure of failure.
  • the chip structure is not limited in this embodiment, and the chip structures 10 corresponding to different chip types may be different.
  • the structure 10 may include a device structure in the front section, a capacitor structure in the middle section, and a metal interconnect structure in the rear section.
  • the device structures include planar transistors, buried gate transistors, fin transistors, gate-all-around transistors, and the like.
  • the steps of forming the chip structure and the sealing structure on the substrate include:
  • the first sub-interlayer dielectric layer 601, the second sub-interlayer dielectric layer 602 and the top dielectric layer 6031 are sequentially formed on the substrate, wherein the first sub-wall 4011 and the second sub-wall 4012 are located in the first sub-wall In the interlayer dielectric layer 601, the third sub-wall 4013 and the fourth sub-wall 4014 are located in the second sub-interlayer dielectric layer 602, the fifth sub-wall 4015 is located in the top dielectric layer 6031, and the top metal layer 402 is located on the top layer On the dielectric layer 6031 , the top metal layer 402 is bonded with the sub-wall, specifically, with the fifth sub-wall 4015 .
  • the chip structure (not shown in the figure) can be formed at the same time when the sub-wall is formed, and the sub-wall is located outside the chip structure and is arranged around the chip structure.
  • the chip structure and the sub-wall can be formed simultaneously in the same process steps of deposition, photolithography, and etching.
  • the etch stop layer may include a first sub-etch stop layer 701 and a second sub-etch stop layer 702 .
  • the first sub-etch stop layer 701 is located between the first sub-layer dielectric layer 601 and the second sub-layer dielectric layer 602
  • the second sub-etch stop layer 702 is located between the second sub-layer dielectric layer 602 and the top layer between the dielectric layers 6031.
  • the method further includes: removing part of the top metal layer 402 to form metal blocks 403 respectively joined to the sub-wall and the top dielectric layer.
  • part of the top metal layer 402 may be removed by photolithography, etching or the like.
  • the metal block 403 can also be used as a sub-wall and arranged around the chip structure.
  • the method further includes: forming a cover layer on the metal block 403 , and the material of the cover layer can be the same as the material of the top dielectric layer to achieve a better bonding effect, so that in the wafer cutting process peeling is unlikely to occur.
  • the cover layer and the top dielectric layer are both made of silicon oxide.
  • the cover layer and the top dielectric layer together form a third sub-layer dielectric layer 603 , and the third sub-layer dielectric layer 603 wraps the metal block 403 .
  • a photoresist layer 70 having openings 71 is formed on the cover layer, and the openings 71 are located above the sub-walls.
  • part of the cover layer is etched by using the photoresist layer as a mask to form a blocking groove 603 exposing the metal block 403 ; as shown in FIG. 10 , filling the blocking groove 603
  • the blocking material forms the blocking wall 501 .
  • the metal block 403 can be used as a sub-wall, and the metal block 403 and other sub-walls constitute the metal wall 40 .
  • the blocking groove 603 is formed by etching, and then the blocking wall 501 is formed in the blocking groove 603, which improves the position and dimensional accuracy of the blocking wall 501; in addition, the blocking groove 603 extends from the top surface of the cover layer away from the substrate. to the metal block 403 , and then expose the corresponding metal block 403 .
  • the blocking wall 501 is formed, the blocking wall 501 is in contact with the metal block 403 , which can prevent cracks from extending to the chip structure between the blocking wall 501 and the metal wall 40 . .
  • the material of the sub-wall and the metal block 403 may include copper, tungsten, aluminum, etc., and the metal wall 40 is not limited in this embodiment.
  • the number of sub-walls can be multiple, and the multiple sub-walls are arranged in layers, and each sub-wall is arranged on the same layer as a metal layer in the chip structure, which can simplify the manufacturing difficulty of the semiconductor structure. It should be noted that the projections of the adjacent sub-walls on the substrate at least partially overlap, so as to avoid the formation of gaps between the adjacent sub-walls.
  • the plurality of sub-walls may include a first sub-wall 4011, a second sub-wall 4012, a third sub-wall 4013, a first sub-wall 4011, a third sub-wall 4013, a The four sub-walls 4014 and the fifth sub-wall 4015, wherein the first sub-wall 4011 and the fifth sub-wall 4015 can be made of tungsten, the second sub-wall 4012, the third sub-wall 4013, the fourth sub-wall
  • the body 4014 may be composed of copper and the metal block 403 may be composed of aluminum.
  • barrier layers 4017 are provided on the sides of the first sub-wall 4011 and the fifth sub-wall 4015 that are perpendicular to the base and the sides close to the base. Similarly, the two sides of the metal block 403 parallel to the base are also provided with barrier layers 4017 . Each barrier layer 4017 is provided; for example, the material of the barrier layer 4017 may include titanium or titanium nitride.
  • the step of fabricating the barrier wall 501 includes: a sealing material is further formed on the cover layer, and part of the sealing material is filled in the barrier groove 603 to form the barrier wall 501 , and part of the sealing material covers the cover layer to form the sealing layer 50 .
  • the sealing layer 50 and the blocking wall 501 have an integral structure, and the blocking wall 501 and the sealing layer 50 are formed through the same manufacturing step, which simplifies the manufacturing difficulty of the semiconductor structure and increases the sealing effect.
  • the sealing layer 50 may be a silicon nitride layer.
  • the blocking wall 501 is also made of silicon nitride.
  • the top surface of the sealing layer 50 located above the blocking wall 501 is higher than the top surface of the sealing layer 50 located above the scribe line 21 .
  • the sealing layer 50 above the barrier wall 501 and the scribe line 21 has a slope. This arrangement can buffer the lateral pressure on the sealing structure when cutting on the cutting track 21 and improve the stability of the sealing structure.
  • a chip structure and a sealing structure are disposed on the substrate, and the sealing structure includes a metal wall 40 and a blocking wall 501 located on top of the metal wall 40.
  • the walls 501 are all disposed around the chip structure 10 .
  • the blocking wall 501 can prevent cracks from extending to the chip structure in the interlayer dielectric layer on the side of the metal wall 40 away from the substrate, thereby preventing the chip structure from failing.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种半导体结构及半导体结构制作方法，该半导体结构的基底上设置有芯片结构和密封结构，密封结构包括金属墙体和位于金属墙体顶部的阻挡墙体，金属墙体和阻挡墙体均环绕芯片结构设置。在晶圆切割的过程中，阻挡墙体可以阻止切割产生的裂纹在金属墙体背离基底一侧的层间介质层内向芯片结构延伸，进而避免芯片结构失效。

Description

半导体结构及半导体结构制作方法
本申请要求于2021年3月1日提交中国专利局、申请号为202110224400.0、申请名称为“半导体结构及半导体结构制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体制造技术领域，尤其涉及一种半导体结构及半导体结构制作方法。
背景技术
制作在晶圆上的芯片需要切割封装后才能运用在电子设备中，在晶圆的切割过程中容易产生裂纹，并且裂纹容易向芯片内部延伸，容易造成芯片失效。
发明内容
本申请实施例提供一种半导体结构及半导体结构制作方法，以解决在晶圆的切割过程中产生的裂纹向芯片结构延伸，容易造成芯片结构失效的技术问题。
第一方面，本申请实施例提供了一种半导体结构，包括：基底以及位于所述基底上的芯片结构和密封结构；所述密封结构包括金属墙体和位于所述金属墙体顶部的阻挡墙体；其中，所述金属墙体和所述阻挡墙体均环绕所述芯片结构设置。
第二方面，本申请实施例还提供一种半导体结构制作方法，包括：
提供基底；
在所述基底上形成芯片结构和密封结构；
所述密封结构包括金属墙体和位于所述金属墙体顶部的阻挡墙体；
其中，所述金属墙体和所述阻挡墙体均环绕所述芯片结构设置。
本申请实施例提供的半导体结构及半导体结构制作方法，基底上设置有芯片结构和密封结构，密封结构包括金属墙体和位于金属墙体顶部的阻挡墙体，金属墙体和阻挡墙体均环绕芯片结构设置。在晶圆切割的过程中，阻挡墙体可以阻止裂纹向芯片结构延伸，进而避免芯片结构失效。
附图说明
图1为本申请实施例提供的半导体结构的俯视图；
图2为本申请实施例提供的半导体结构的剖视图一；
图3为本申请实施例提供的半导体结构的剖视图二；
图4为本申请实施例提供的半导体结构制作方法的流程图；
图5为本申请实施例提供的半导体结构制作方法中形成顶层金属层后的结构示意图；
图6为本申请实施例提供的半导体结构制作方法中形成金属块后的结构示意图；
图7为本申请实施例提供的半导体结构制作方法中形成覆盖层后的结构示意图；
图8为本申请实施例提供的半导体结构制作方法中形成光刻胶层后的结构示意图；
图9为本申请实施例提供的半导体结构制作方法中形成阻挡槽后的结构示意图；
图10为本申请实施例提供的半导体结构制作方法中形成阻挡墙体后的结构示意图。
具体实施方式
本申请实施例提供一种半导体结构，通过在金属墙体的顶端设置阻挡墙体；在晶圆切割产生裂纹时，阻挡墙体可以阻止裂纹在金属墙体顶部的层间介质层上向芯片结构延伸，以避免芯片结构的失效。
请参照图1，本实施例提供半导体结构包括基底11以及位于基底11上的芯片结构10和密封结构20，示例性的，基底11可以包括硅晶圆、锗晶圆、氮化镓晶圆、锗化镓晶圆或SOI晶圆等。芯片结构10设置在基底上，本实施例对芯片结构10不作限制，不同的芯片种类对应的芯片结构10可以不同，例如，逻辑芯片的芯片结构10可以包括前段的器件结构和后段的金属互连结构；动态随机存储器芯片的芯片结构10可以包括前段的器件结构、中段的电容结构以及后段的金属互连结构。示例的，器件结构包括平面晶体管、埋入式栅极晶体管、鳍式晶体管或环栅式晶体管等。密封结构20环绕设置在芯片结构10外围，密封结构20之间为切割道21。
请参照图1和图2，其中，图2为相邻的密封结构20之间的剖视图。本实施例中，密封结构20包括金属墙体40和位于金属墙体40顶部的阻挡墙体501，金属墙体40和阻挡墙体501环绕芯片结构10设置。进一步地，半导体结构还包括层间介质层和刻蚀停止层，金属墙体40和阻挡墙体501位于层间介质层和刻蚀停止层内，层间介质层、刻蚀停止层以及金属墙体40可以阻止外界的空气、水蒸气等与芯片结构10接触，对实现芯片结构10进行保护。
层间介质层和刻蚀停止层可以由绝缘材料构成，示例性的，层间介质层的材质可以为氧化硅。当然，本实施例对此不作限制，本实施例中层间介质层还可以为氮氧化硅、氮化硅等的材质。金属墙体40的材质可以包括铜、钨、铝等，本实施例对金属墙体40不作限制。刻蚀停止层的材料可以为氮氧化硅、碳氮化硅等材料，需要注意的是层间介质层和刻蚀停止层的材质不同。
在一些实施例中，金属墙体40可以包括沿垂直于基底方向依次层叠设置的多个子墙体，相邻子墙体层在基底上的投影至少部分重合。值得说明的是，各子墙体均由金属材质构成，各子墙体的材质可以相同也可以不同，本实施例对此不限制。如此设置，金属墙体40由多个子墙体堆叠形成，可以降低金属墙体40的制作难度；另外，相邻子墙体在基底上的投影至少部分重合，使得相邻子墙体之间至少部分接合，可以提高密封效果。
相应的，层间介质层包括沿垂直于基底方向依次层叠设置的多个子层间介质层，每一子层间介质层至少与一个子墙体同层设置；制作时，可以先形成一子层间介质层，之后在子层间介质层上形成槽口，在槽口内形成子墙体；如此往复，以形成密封结构20；当然，也可以先形成金属层，去除部分金属层以形成子墙体，之后形成与该子墙体同层设置的子层间介质层；如此往复，也可形成密封结构20。进一步的，子层间介质层之间还设置有刻蚀停止层。
进一步地，每一子墙体与芯片结构10中的一个金属层同层设置。如此，芯片结构10中的金属层与子墙体可以同时形成，简化了半导体结构的制作步骤，进而降低了半导体结构的制作难度。
在每一子墙体与芯片结构10中的一个金属层同层设置的实现方式中，构成层间介质层的各子层间介质层的材质可以相同、部分相同或者完全不同，构成金属墙体40的各子墙体的材质也可以相同、部分相同或者完全不同。
以图2所示为例，在一些可实现的方式中，金属墙体40可以包括沿远离基底(图中未示出)方向依次层叠设置的6个子墙体，分别为第一子墙体4011、第二子墙体4012、第三子墙体4013、第四子墙体4014、第五子墙体4015以及第六子墙体4016；其中，第一子墙体4011和第五子墙体4015可以由钨构成，第二子墙体4012、第三子墙体4013、第四子墙体4014可以由铜构成，第六子墙体4016可以由铝构成。进一步地，在第一子墙体4011和第五子墙体4015垂直于基底的侧面以及靠近基底的侧面上均设置阻挡层4017，相同的，在第六子墙体4016与基底平行的两个侧面上也均设置阻挡层4017；示例性的，阻挡层4017的材质可以包括钛或者氮化钛。层间介质层可以包括第一子层间介质层601、第二子层间介质层602和第三子层间介质层603，刻蚀停止层可以包括第一子刻蚀停止层701和第二子刻蚀停止层702。其中，第一子刻蚀停止层701位于第一子层间介质层601和第二子层间介质层602之间，第二子刻蚀停止层702位于第二子层间介质层602和第三子层间介质层603之间。
本实施例中，金属墙体40设置在层间介质层内，也就是说层间介质层包裹在金属墙体40与基底垂直的侧壁的同时，至少部分层间介质层还覆盖在金属墙体40背离基底的顶部上。
阻挡墙体501设置在金属墙体40的顶部。具体的，阻挡墙体501位于金属墙体40背离基底的一侧，并且阻挡墙体501正对金属墙的顶部设置。如图2和图3所示，当切割晶圆在切割道21上形成切缝30时，阻挡墙体501可以阻止金属墙体40背离基底一侧的层间介质层内的裂纹向芯片结构10延伸，进而避免失效。
进一步地，阻挡墙体501背离基底的底端与至少部分金属墙体40的顶端接触，以避免阻挡墙体501和金属墙体40之间具有缝隙，裂纹沿该缝隙向芯片结构10延伸。
在一些实施例中，阻挡墙体501可以位于层间介质层内，也就说，阻挡墙沿垂直于基底方向的厚度小于金属墙体40顶端的层间介质层厚度。
在其他实施例中，阻挡墙体501沿垂直于基底方向的厚度等于金属墙体40顶端的层间介质层厚度；制作时，可以在层间介质层背离基底的侧面上形成阻挡槽，阻挡槽向阻挡墙体501的顶端延伸，并且阻挡槽的槽底与金属墙体40顶端接触，阻挡墙体501填充在阻挡槽内。如此设置，可以进一步避免在形成切缝30时，裂纹沿金属墙体40背离基底一侧的层间介质层向芯片结构10延伸。
在上述实现方式中，阻挡墙体501设置在金属墙体40的顶端，示例性的，阻挡墙体501覆盖金属墙体40的至少部分顶面，进而避免裂纹沿阻挡墙体501和金属墙体40之间向芯片结构10延伸，进而提高对芯片结构10的密封效果。
以图2所示结构为例，金属墙体40的第六子墙体4016位于金属墙体40的顶端，阻挡墙体501在基底上的投影位于第六子墙体4016在基底上的投影内部，使得阻挡墙体501 覆盖部分第六子墙体4016。
请参照图1和图3，本实施例中，制作时可以在基底上(例如硅晶圆上)制作多个芯片结构10，每一半导体结构的外围均形成密封结构20；之后对硅晶圆进行切割，以在相邻的密封结构20之间形成切缝30，进而得到多个芯片。
本实施例提供的半导体结构，基底上设置有芯片结构10和密封结构20，密封结构20包括金属墙体40和位于金属墙体40顶部的阻挡墙体501，金属墙体40和阻挡墙体501均环绕芯片结构10设置。在晶圆切割形成切缝30的过程中，阻挡墙体501可以阻止裂纹在金属墙体40背离基底一侧的层间介质层内向芯片结构10延伸，进而避免芯片结构10失效。
在一些实施例中，阻挡墙体501可以为多个，多个阻挡墙体501环绕芯片结构10间隔的设置；并且多个阻挡墙体501均位于金属墙体40的顶部。如此设置，多个阻挡墙体501可以提供多重保护，进一步提高保护效果。
在一些实施例中，多个阻挡墙体501均位于同一金属墙体40的顶部，例如，多个阻挡墙体501间隔的设置在同一第六子墙体4016的顶部，在提高保护效果的同时，降低了密封结构的占用面积。
本实施例提供的半导体结构，还包括设置在密封结构20背离基底一侧的密封层50。密封层50覆盖在密封结构20上，可以进一步提高对芯片结构10的保护效果和密封效果。示例性的，密封层50可以位于层间介质层背离基底的一侧。
进一步地，密封层50与阻挡墙体501可以为一体结构；如此设置，可以通过同一制作步骤形成阻挡墙体501和密封层50，简化了半导体结构的制作难度。
进一步的，位于阻挡墙体501上方的密封层50的顶表面高于位于切割道21上方的密封层50的顶表面。具体的，阻挡墙体501与切割道21之间上方的密封层50具有一斜坡。如此设置，可以缓冲在切割道上切割时对密封结构的侧向压力，提高密封结构的稳定性。
阻挡墙体501的材质包括绝缘材质；示例性的，阻挡墙体501的材质可以包括氮化硅、氮氧化硅等。在密封层50与阻挡墙体501为一体结构的实现方式中，密封层50的材质与阻挡墙体501的材质相同。
本申请实施例还提供一种半导体结构制作方法，用于制作上述实施例中的半导体结构，半导体结构的基底上设置有芯片结构和密封结构，密封结构包括金属墙体和位于金属墙体顶部的阻挡墙体，金属墙体和阻挡墙体均环绕芯片结构设置。在晶圆切割的过程中，阻挡墙体可以阻止裂纹在金属墙体背离基底一侧的层间介质层内向芯片结构延伸，进而避免芯片结构失效。
请参照图4，本申请实施例还提供一种半导体结构制作方法，包括：
S101：提供基底。
示例性的，基底可以包括硅晶圆、锗晶圆、氮化镓晶圆、锗化镓晶圆、砷化镓晶圆或SOI晶圆等半导体材质的晶圆。
在形成基底之后，本实施例提供的半导体结构制作方法还包括：
S102：在基底上形成芯片结构和密封结构，密封结构包括金属墙体和位于金属墙体顶部的阻挡墙体；其中，金属墙体和阻挡墙体均环绕芯片结构设置。
具体的，可以在硅晶圆上形成间隔设置的多个芯片结构，每一芯片结构外围均形成有 密封结构，相邻芯片结构外围的密封结构之间为切割道。本实施例中，金属墙体顶部设置有阻挡墙体，可以在晶圆切割时即在切割道上形成切缝时，阻止裂纹沿金属墙体背离基底的一侧向芯片结构延伸，进而避免芯片结构的失效。
本实施例对芯片结构不作限制，不同的芯片种类对应的芯片结构10可以不同，例如，逻辑芯片的芯片结构10可以包括前段的器件结构和后段的金属互连结构；动态随机存储器芯片的芯片结构10可以包括前段的器件结构、中段的电容结构以及后段的金属互连结构。示例的，器件结构包括平面晶体管、埋入式栅极晶体管、鳍式晶体管或环栅式晶体管等。
本实施例中，在基底上形成芯片结构和密封结构的步骤，包括：
如图5所示，在基底(图中未示出)上形成若干子层间介质层、若干子墙体以及顶层金属层402。具体的，在基底上依次形成第一子层间介质层601、第二子层间介质层602和顶层介质层6031，其中，第一子墙体4011和第二子墙体4012位于第一子层间介质层601中，第三子墙体4013和第四子墙体4014位于第二子层间介质层602中，第五子墙体4015位于顶层介质层6031中，顶层金属层402位于顶层介质层6031上，顶层金属层402与子墙体接合，具体的，与第五子墙体4015接合。其中，在形成子墙体时即可同时形成芯片结构(图中未示出)，子墙体位于芯片结构的外侧，且环绕芯片结构设置。具体的，可以在相同的沉积、光刻、刻蚀等工艺步骤中同时形成芯片结构和子墙体。
进一步的，还包括形成刻蚀停止层，所述刻蚀停止层可以包括第一子刻蚀停止层701和第二子刻蚀停止层702。其中，第一子刻蚀停止层701位于第一子层间介质层601和第二子层间介质层602之间，第二子刻蚀停止层702位于第二子层间介质层602和顶层介质层6031之间。
如图6所示，在形成顶层金属层402之后，还包括：去除部分顶层金属层402，以形成分别与子墙体和顶层介质层接合的金属块403。示例性的，可以通过光刻、蚀刻等方式去除部分顶层金属层402。具体的，金属块403也可以作为子墙体，并环绕芯片结构设置。
如图7所示，在形成金属块403之后，还包括：在金属块403上形成覆盖层，覆盖层的材质可以与顶层介质层的材质相同以达到更好的结合效果，使得在晶圆切割时，不易发生剥离。覆盖层和顶层介质层的材质均为氧化硅，覆盖层和顶层介质层共同组成第三子层间介质层603，第三子层间介质层603包覆金属块403。如图8所示，在形成覆盖层之后，在所述覆盖层上形成具有开口71的光刻胶层70，开口71位于子墙体上方。
如图9所示，在形成光刻胶层之后，以光刻胶层为掩膜蚀刻部分覆盖层，以形成暴露金属块403的阻挡槽603；如图10所示，在阻挡槽603中填充阻挡材料形成阻挡墙体501。
在上述实现方式中，金属块403可以作为子墙体，金属块403以及其他子墙体构成金属墙体40。
如此设置，通过蚀刻的方式形成阻挡槽603，之后在阻挡槽603内形成阻挡墙体501，提高了阻挡墙体501的位置和尺寸精度；另外，阻挡槽603由覆盖层背离基底的顶面延伸至金属块403，进而暴露对应的金属块403，在形成阻挡墙体501时，阻挡墙体501与金属块403接触，可以避免裂纹沿阻挡墙体501和金属墙体40之间向芯片结构延伸。
示例性的，子墙体和金属块403的材质可以包括铜、钨、铝等，本实施例对金属墙体40不作限制。
子墙体可以为多个，多个子墙体层叠设置，每一子墙体与芯片结构中的一个金属层同层设置，可以简化半导体结构的制作难度。值得说明的是，相邻子墙体在基底上的投影至少部分重叠，以避免相邻子墙体之间形成缝隙。
以图10所示为例，多个子墙体可以包括沿远离基底(图中未示出)方向依次设置的第一子墙体4011、第二子墙体4012、第三子墙体4013、第四子墙体4014以及第五子墙体4015，其中第一子墙体4011和第五子墙体4015可以由钨构成，第二子墙体4012、第三子墙体4013、第四子墙体4014可以由铜构成，金属块403可以由铝构成。进一步地，在第一子墙体4011和第五子墙体4015垂直于基底的侧面以及靠近基底的侧面上均设置阻挡层4017，相同的，在金属块403与基底平行的两个侧面上也均设置阻挡层4017；示例性的，阻挡层4017的材质可以包括钛或者氮化钛。
继续参照图10，本实施例提供的半导体结构制作方法，制作阻挡墙体501的步骤包括：在覆盖层上还形成有密封材料，部分密封材料填充在阻挡槽603内，以形成阻挡墙体501，部分密封材料覆盖在覆盖层上以形成密封层50。
如此设置，密封层50与阻挡墙体501为一体结构，通过同一制作步骤形成阻挡墙体501和密封层50，简化了半导体结构的制作难度，同时增大了密封效果。
示例性的，密封层50可以为氮化硅层。相应的，阻挡墙体501也由氮化硅构成。
进一步的，位于阻挡墙体501上方的密封层50顶表面高于位于切割道21上方的密封层50顶表面。具体的，阻挡墙体501与切割道21之间上方的密封层50具有一斜坡。如此设置，可以缓冲在切割道21上切割时对密封结构的侧向压力，提高密封结构的稳定性。
本实施例提供的半导体结构制作方法制作的半导体结构，基底上设置有芯片结构和密封结构，密封结构包括金属墙体40和位于金属墙体40顶部的阻挡墙体501，金属墙体40和阻挡墙体501均环绕芯片结构10设置。在切割晶圆形成切缝的过程中，阻挡墙体501可以阻止裂纹在金属墙体40背离基底一侧的层间介质层内向芯片结构延伸，进而避免芯片结构失效。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种半导体结构，包括：
    基底以及位于所述基底上的芯片结构和密封结构；
    所述密封结构包括金属墙体和位于所述金属墙体顶部的阻挡墙体；
    其中，所述金属墙体和所述阻挡墙体均环绕所述芯片结构设置。
  2. 根据权利要求1所述的半导体结构，其中，多个所述阻挡墙体环绕所述芯片结构间隔的设置。
  3. 根据权利要求2所述的半导体结构，其中，所述多个阻挡墙体均位于所述金属墙体的顶部。
  4. 根据权利要求1所述的半导体结构，其中，还包括：
    密封层，位于所述密封结构背离所述基底的一侧。
  5. 根据权利要求4所述的半导体结构，其中，所述阻挡墙体与所述密封层为一体结构。
  6. 根据权利要求5所述的半导体结构，其中，所述阻挡墙体的材质为绝缘材料。
  7. 根据权利要求6所述的半导体结构，其中，所述阻挡墙体覆盖所述金属墙体的部分顶面。
  8. 根据权利要求1所述的半导体结构，其中，所述金属墙体包括沿垂直于所述基底方向依次层叠设置的多个子墙体，相邻所述子墙体在所述基底上的投影至少部分重合。
  9. 根据权利要求8所述的半导体结构，其中，每一所述子墙体与所述芯片结构中的金属层同层设置。
  10. 根据权利要求6所述的半导体结构，其中，还包括：
    位于所述密封结构之间的切割道，所述阻挡墙体上方的密封层顶表面高于所述切割道上方的密封层顶表面。
  11. 一种半导体结构制作方法，包括：
    提供基底；
    在所述基底上形成芯片结构和密封结构，
    所述密封结构包括金属墙体和位于所述金属墙体顶部的阻挡墙体；
    其中，所述金属墙体和所述阻挡墙体均环绕所述芯片结构设置。
  12. 根据权利要求11所述的半导体结构制作方法，其中，所述在所述基底上形成芯片结构和密封结构的步骤，包括：
    在所述基底上依次形成若干子层间介质层、顶层介质层以及顶层金属层，其中， 若干子墙体分别位于所述子层间介质层和顶层介质层中；
    去除部分所述顶层金属层以形成与所述子墙体接合的金属块；
    在所述金属块上形成覆盖层；
    在所述覆盖层上形成具有开口的光刻胶层，所述开口位于所述子墙体上方；
    以所述光刻胶层为掩膜蚀刻所述覆盖层，以形成暴露所述子墙体上方的所述金属块的阻挡槽；
    在所述阻挡槽中填充阻挡材料形成所述阻挡墙体。
  13. 根据权利要求12所述的半导体结构制作方法，其中，还包括：所述覆盖层上还形成有密封材料，部分所述密封材料填充在所述阻挡槽内，以形成所述阻挡墙体，部分所述密封材料覆盖在所述覆盖层上以形成密封层。
  14. 根据权利要求13所述的半导体结构制作方法，其中，还包括：
    位于所述密封结构之间的切割道，所述阻挡墙体上方的密封层顶表面高于所述切割道上方的密封层顶表面。
  15. 根据权利要求13所述的半导体结构制作方法，其中，所述覆盖层和所述顶层介质层的材质相同。
PCT/CN2021/104791 2021-03-01 2021-07-06 半导体结构及半导体结构制作方法 WO2022183647A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/648,130 US20220278054A1 (en) 2021-03-01 2022-01-16 Semiconductor structure and manufacturing method of semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110224400.0 2021-03-01
CN202110224400.0A CN113035835B (zh) 2021-03-01 2021-03-01 半导体结构及半导体结构制作方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/648,130 Continuation US20220278054A1 (en) 2021-03-01 2022-01-16 Semiconductor structure and manufacturing method of semiconductor structure

Publications (1)

Publication Number Publication Date
WO2022183647A1 true WO2022183647A1 (zh) 2022-09-09

Family

ID=76464835

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/104791 WO2022183647A1 (zh) 2021-03-01 2021-07-06 半导体结构及半导体结构制作方法

Country Status (2)

Country Link
CN (1) CN113035835B (zh)
WO (1) WO2022183647A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035835B (zh) * 2021-03-01 2022-04-01 长鑫存储技术有限公司 半导体结构及半导体结构制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1734764A (zh) * 2004-07-15 2006-02-15 台湾积体电路制造股份有限公司 具有预防裂痕的环状结构的半导体装置及其制造方法
US20100078769A1 (en) * 2008-09-23 2010-04-01 Texas Instruments Incorporated Environmental die seal enhancement for wafer level chip scale packages
CN102468247A (zh) * 2010-11-03 2012-05-23 台湾积体电路制造股份有限公司 附着聚酰亚胺层的密封环结构
US20140035128A1 (en) * 2012-07-31 2014-02-06 Taiwan Semiconductor Manufacturing Company Limited Semiconductor seal ring
CN113035835A (zh) * 2021-03-01 2021-06-25 长鑫存储技术有限公司 半导体结构及半导体结构制作方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW497207B (en) * 2001-04-10 2002-08-01 United Microelectronics Corp Guard ring structure
US7397106B2 (en) * 2005-12-12 2008-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Laser fuse with efficient heat dissipation
US20080277659A1 (en) * 2007-05-10 2008-11-13 Shih-Hsun Hsu Test structure for semiconductor chip
JP5334459B2 (ja) * 2008-05-30 2013-11-06 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
WO2012095907A1 (ja) * 2011-01-14 2012-07-19 パナソニック株式会社 半導体装置及びフリップチップ実装品
CN106298694B (zh) * 2015-05-19 2019-09-03 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法和电子装置
CN106898580B (zh) * 2015-12-18 2019-05-03 中芯国际集成电路制造(上海)有限公司 芯片保护环、半导体芯片、半导体晶圆及封装方法
CN206422061U (zh) * 2017-01-18 2017-08-18 中芯国际集成电路制造(北京)有限公司 晶圆切割道结构
CN109962039B (zh) * 2017-12-25 2021-01-26 中芯国际集成电路制造(上海)有限公司 一种半导体器件及电子装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1734764A (zh) * 2004-07-15 2006-02-15 台湾积体电路制造股份有限公司 具有预防裂痕的环状结构的半导体装置及其制造方法
US20100078769A1 (en) * 2008-09-23 2010-04-01 Texas Instruments Incorporated Environmental die seal enhancement for wafer level chip scale packages
CN102468247A (zh) * 2010-11-03 2012-05-23 台湾积体电路制造股份有限公司 附着聚酰亚胺层的密封环结构
US20140035128A1 (en) * 2012-07-31 2014-02-06 Taiwan Semiconductor Manufacturing Company Limited Semiconductor seal ring
CN113035835A (zh) * 2021-03-01 2021-06-25 长鑫存储技术有限公司 半导体结构及半导体结构制作方法

Also Published As

Publication number Publication date
CN113035835B (zh) 2022-04-01
CN113035835A (zh) 2021-06-25

Similar Documents

Publication Publication Date Title
US7994589B2 (en) Semiconductor device and method for fabricating the same
US9793224B2 (en) Crack stop barrier and method of manufacturing thereof
TWI775766B (zh) 半導體裝置
US11164840B2 (en) Chip interconnection structure, wafer interconnection structure and method for manufacturing the same
JP2008270488A (ja) 半導体装置及びその製造方法
US11069647B2 (en) Semiconductor wafer, bonding structure and wafer bonding method
JPH10270388A (ja) クラックストッパを形成する方法
TW201933430A (zh) 製造半導體裝置的方法以及半導體裝置
TW202213681A (zh) 積體電路裝置及其製造方法
JP2006005011A (ja) 半導体装置
WO2022183647A1 (zh) 半导体结构及半导体结构制作方法
US20180175038A1 (en) Method for fabricating semiconductor device
TWI670857B (zh) 記憶體結構及其形成方法
US20100314674A1 (en) Semiconductor device and method for manufacturing the same
TWI788897B (zh) 半導體記憶體裝置
WO2022198888A1 (zh) 半导体结构的制作方法及半导体结构
TWI696227B (zh) 半導體元件及其製造方法
TW202205675A (zh) 半導體元件
US20220278054A1 (en) Semiconductor structure and manufacturing method of semiconductor structure
US6853050B2 (en) Semiconductor device with fuse box and method for fabricating the same
US11145601B2 (en) Semiconductor chip including alignment pattern
JP5726989B2 (ja) 半導体装置
US20230046051A1 (en) Interconnection structure, semiconductor device with interconnection structure and method for fabricating the same
TWI830319B (zh) 半導體裝置及其製造方法
TW202234490A (zh) 半導體元件以及其製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21928725

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21928725

Country of ref document: EP

Kind code of ref document: A1