CN101414584A - 半导体器件和制造半导体器件的方法 - Google Patents
半导体器件和制造半导体器件的方法 Download PDFInfo
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Abstract
包括具有在一侧上形成的外部连接端子的半导体芯片的半导体器件会抑制在半导体芯片的脊线部分产生破片。覆盖层(103)形成在半导体芯片(102)的另一侧上。覆盖层的端部(106)的至少一部分在半导体芯片的脊线部分(107)的外面。
Description
技术领域
本发明涉及一种半导体器件和制造半导体器件的方法。
背景技术
电子器件高集成度的趋势刺激了半导体器件(半导体封装),如包括一侧上的外部连接端子且具有与要被安装的半导体芯片近似相同的外部尺寸的WLBGA(晶片级球栅格阵列)的发展。此外,WLBGA有时候称为晶片级芯片尺寸封装。
这种半导体器件通常构造为暴露半导体芯片的一侧(形成硅衬底的一侧)。因此,例如由于在检查阶段和封装阶段期间的处理所施加的外力,有时候会导致破片,如半导体芯片的脊线位置中的裂纹和破裂。在本申请中,半导体芯片的一侧的端部(例如,图1中的脊线部分107)称为脊线部分。由相应破片产生的硅碎片附着在布线层和其它半导体芯片上,以导致电性能恶化,如相互布线之间的短路,而导致故障。
日本专利特开No.2006—80284论述了用来避免这种问题的技术。如图11所示,半导体器件10由半导体芯片11和密封树脂12上的外部连接端子13组成。斜面部分14形成在半导体芯片11的端部。该斜面部分14旨在抑制在处理期间发生破片。
日本专利特开No.2001—230224的目的是不同的。然而,为了提高整个半导体器件抵抗弯曲变形的强度,在半导体芯片11上的结构中和在形成于电路表面16上的外部连接端子13的相对一侧上,提供具有的面积与相应的半导体芯片11的面积相同的树脂15,如同图12中一样。
发明内容
日本专利特开No.2006—80284和日本专利特开No.2001—230224中的现有技术仍然需要如下改善。
对于日本专利特开No.2006—80284,半导体芯片11在其端部提供有斜面部分14。然而,由于半导体芯片11的脊线部分17(本申请中由箭头指示的相应两个位置也处于脊线部分中)被暴露,所以外力有时候会施加到相应部分,特别是在由半导体器件的一侧(硅衬底形成侧)处理时。因此,有时仍然会产生破片。对于日本专利特开No.2001—230224,树脂15形成在半导体芯片12上。因此,考虑到相应的树脂15在半导体芯片12上表面的处理时会有效地抑制外力施加。然而,在结构中易引起破片的半导体芯片12的脊线部分17被暴露且外力在上述处理期间有时侯会施加到相应的部分。因此,抑制半导体芯片破片仍需要改善。
如上所述,由于施加外力,例如处理时,现有技术不能抑制在半导体芯片的脊线部分出现的破片。
本发明提供了包括具有在一侧上形成的外部连接端子的半导体芯片的半导体器件,其中覆盖层形成在半导体芯片的另一侧上且覆盖层的端部的至少一部分在半导体芯片的脊线部分的外面。
另外,本发明提供了由半导体晶片制造半导体器件的方法,在半导体晶片一侧上提供外部连接端子,并在半导体晶片另一侧上提供覆盖层,包括:从一侧到至少在半导体晶片和半导体晶片中的覆盖层之间的界面形成具有第一宽度的凹槽;以及用第二宽度从凹槽底面切割覆盖层,其中第二宽度比第一宽度窄。
在本发明中,在包括具有形成在一侧上的外部连接端子的半导体芯片的半导体器件中,在半导体芯片另一侧上形成的至少一部分覆盖层在半导体芯片的脊线部分的外面。因此,在处理时,半导体芯片的脊线部分将不再直接接触到例如用于处理的夹具。由于半导体芯片的脊线部分被保护,因此能够抑制破片的产生。
本发明可以提供包括具有形成在一侧上的外部连接端子的半导体芯片的半导体器件,其中抑制了在半导体芯片的脊线部分产生破片。本发明还可以提供了制造半导体器件的方法。
附图说明
图1是关于本发明第一实施例的半导体器件的横截面示意图;
图2是关于本发明第一实施例的半导体器件的平面示意图;
图3是关于本发明第一实施例的WLBGA的平面示意图;
图4A到4F是关于本发明第一实施例的工艺流程的横截面示意图;
图5A到5D是关于本发明第一实施例的工艺流程的示意图;
图6是关于本发明第二施例的半导体器件的横截面示意图;
图7A到7F是关于本发明第二实施例的工艺流程的横截面示意图;
图8是关于本发明第三实施例的半导体器件的横截面示意图;
图9是关于本发明第三施例的半导体器件的横截面示意图;
图10A到10F是关于本发明第四实施例的工艺流程的横截面示意图;
图11是描述本发明的现有技术的图;以及
图12示出了描述本发明的现有技术的图。
具体实施方式
(第一实施例)
图1是描述本发明第一实施例的半导体器件的横截面示意图。图2是它的平面图。
如图1所示,半导体器件101包括半导体芯片102、覆盖层103、布线层104和外部连接端子105。如图1和图2所示,覆盖层的端部106在半导体芯片的脊线部分107的外面。覆盖层的突出部分122将不被特别限制,但是其不能大于所使用的半导体芯片102的大约厚度。例如,如下描述突出部分122可以为7.5μm左右。覆盖层103的厚度不被特别限制,但是不能大于半导体芯片102的厚度的大约一半,例如,50μm。例如,树脂层和带层能够用作为覆盖层103。
焊球105形成为半导体器件101一侧(图1中的下侧)上的外部接触端子。焊球105经由在半导体芯片102一侧上形成的布线层104电连接到半导体芯片102表面上的接合垫108。在结构中,如图1所示,布线层104可以包括第一绝缘层109(由聚酰亚胺制成)、第二绝缘层110(由树脂制成)、UBM(凸块下金属)111、布线112和柱113。布线112和柱113可以由Cu制成且由Ti/Cu制成的叠层膜可以用作UBM111。在本实施例中,半导体芯片102表面上的接合垫108通过布线层104连接到外部连接端子105,但是在结构中,可以采用其直接连接。图2是由形成覆盖层103的一侧得到的平面图。图2仅示出覆盖层103和半导体芯片102。省略对诸如其它布线层和焊球的组件的描述。
在本实施例中,覆盖层的端部106形成在半导体芯片102的另一侧上,且在半导体芯片的脊线部分107的外面。因此,在从半导体芯片102的另一侧处理时,半导体芯片的脊线部分107将不再直接接触到例如用于处理的夹具(图中未示出)。半导体芯片的脊线部分107的保护能够抑制产生破片。在本实施例中,如图2所示,覆盖层103沿半导体芯片102的四侧向外突出。然而,突出仅在任意侧或在任意位置(一个部分)中提供。
接着,描述制造关于本实施例的半导体器件的方法。如图3所示,采用公知的制造方法来制造WLBGA 130。图3是由外部连接端子105的一侧得到的整个平面图。外部连接端子105在半导体晶片131上形成。半导体器件101的单独芯片将用划线132来相互分隔。
图4示出了工艺流程的横截面示意图。图4A示出了图3中示出的WLBGA 130的部分横截面图。半导体晶片131的元件通过公知方法形成。WLBGA 130的布线层104通过公知方法形成在半导体晶片131的一侧上。外部连接端子(焊球)105经由相应的布线层104形成。
接着,如图4B所示,覆盖层103形成在半导体晶片104的另一侧上。例如,通过施加树脂层和粘贴带层形成覆盖层。在形成外部连接端子105之后,形成本实施例中的覆盖层103。相反,在半导体晶片的另一侧上形成覆盖层103之后,可以在外部连接端子105的一侧上形成覆盖层103。
如图4C所示,在其外部连接端子105设置在其上侧的情况下,将WLBGA 130粘贴用于切割的切割带114上。在本实施例中WLBGA 130的单独芯片用刀片115制造。
为描述切割工艺,图4D和图4E示出用图4C中的圆127以扩大方式指定的切割部分。首先,如图4D所示,用第一刀片115在半导体晶片131的一侧(形成外部连接端子的表面)形成第一凹槽125。将第一凹槽125形成为到达半导体晶片131和覆盖层103之间的界面。
接着,如图4E所示,用第二刀片116从第一凹槽125底面的中心形成切割覆盖层103的第二凹槽121。在这里,第二刀片116的宽度比第一刀片115的宽度窄。即,第二凹槽126的宽度比第一凹槽125的宽度窄。自半导体芯片102脊线部分的覆盖层103的突出部分由第一凹槽125和第二凹槽126之间的宽度差来确定。因此,任意地选择这些凹槽,可以调整突出部分以达到预定值。其后,如图4F所示,从切割片114剥离并得到半导体器件101的单独芯片。
图5示出在覆盖层103的半导体芯片102的脊线部分的突出部分设计为7.5μm的情况下详细示例切割工艺以说明实施例的示意图。图5A是用第一刀片形成第一凹槽的步骤;图5B是用第二刀片形成第二凹槽的步骤;以及图5C是在切割工艺之后的横截面示意图。图5D示出WLBGA中划线交叉的平面图。
如图5A所示,用具有50μm刀片宽度117的第一刀片115,对准80μm划线宽度119的中心,从形成外部连接端子105的表面到半导体晶片131和覆盖层103之间的界面,来形成第一凹槽125。在这种情况下,刀片115的侧表面提供有微磨石(图中未示出)。因此,切割后的第一凹槽宽度120略微比刀片宽度宽一些,且大约为55μm(图5B)。接着,如图5B所示,用具有35μm刀片宽度118的第二切割刀片116,从第一凹槽125的底面切割覆盖层103,来形成第二凹槽126。在那种情况下,由于刀片侧表面上的磨石(图中未示出),第二凹槽宽度121略微宽且大约为40μm(图5C)。图5C是切割工艺后的横截面图。因此,第一凹槽125和第二凹槽126之间的宽度差可以制造包括具有设计尺寸为7.5μm的突出部分122的半导体器件。
图5D是在得到半导体器件101的单独芯片之前的半导体器件101的单独芯片的平面图。覆盖层103比半导体芯片102的脊线部分107向外即向划线侧突出7.5μm(突出部分122)。
通过这种方法制造的半导体器件101将构造为图1所示的以便在半导体芯片另一侧上形成的覆盖层在上述半导体芯片的脊线部分的外面。因此,在处理时,半导体芯片的脊线部分将不再直接地接触到例如用于处理的夹具。由于半导体芯片的脊线部分被保护,因此可以抑制破片产生。
(第二实施例)
在覆盖层的端部106处的突出模式方面,本实施例不同于其它实施例。
图6是关于本发明第二实施例的半导体器件的横截面示意图。第二实施例不同于第一实施例(图1)之处在于,半导体芯片102的覆盖层的端部106的一部分在半导体芯片的脊线部分107的外面。由于覆盖层103的一部分在半导体芯片的脊线部分107的外面,所以第二实施例会产生类似于第一实施例作用的效果。
图7示出制造关于第二实施例的半导体器件的方法的横截面示意图。
如图7A所示,常规WLBGA 130用公知制造方法而制作。在WLBGA 130中,外部连接端子(焊球)105经由布线层104形成在半导体晶片131的一侧上。
接着,如图7B所示,覆盖层103形成在半导体晶片131的另一侧上。如图7C所示,在覆盖层103的表面上粘贴切割带114,刀片115从WLBGA 130制造单独块。
为描述切割工艺,图7D和图7E示出用图7C中的圆127以扩大方式指定的切割部分。首先,如图7D所示,用第一刀片115在半导体晶片131的一侧(形成外部连接端子的表面)形成第一凹槽125。将第一凹槽125形成为经由半导体晶片131到达覆盖层103的中间。由于覆盖层的剩余膜在那时对应于突出的厚度,所以可以适当调整第一凹槽125的深度以便得到预定厚度。
接着,如图7E所示,用第二刀片116从第一凹槽125底面的中心形成用于切割覆盖层103的第二凹槽126。在这里,第二刀片116的宽度比第一刀片115的宽度窄。即,第二凹槽126的宽度比第一凹槽125的宽度窄。从半导体芯片102的脊线部分的覆盖层103的突出部分由第一凹槽125和第二凹槽126之间的宽度差确定。因此,任意地选择这些凹槽,可以调整突出部分以获得预定值。其后,如图7F所示,从切割片114剥离并得到半导体器件101的单独芯片。
通过这种方法制造的半导体器件101构造为如图6所示,产生抑制破片效果。
(第三实施例)
在形成覆盖层以便覆盖半导体芯片的脊线部分方面,本实施例不同于其它实施例。
与第一实施例或第二实施例(图1或图6)中的半导体器件101不同,通过对覆盖层103的端部应用热处理,可以形成覆盖层103以覆盖半导体芯片102的脊线部分107。
如图8所示,根据热处理的条件,可以使覆盖层103在半导体器件101的外部连接端子105的一侧方向上弯曲以便覆盖半导体芯片102的脊线部分107。
如图9所示,红外线加热(图中未示出)可以局部地过度加热覆盖层103的端部至熔化以便使覆盖层103覆盖半导体芯片102的脊线部分107并与它们的侧表面接触。
由于覆盖层103覆盖半导体芯片102脊线部分107,所以本实施例可以更有效地抑制破片产生。
(第四实施例)
本实施例不同于其它实施例在于形成覆盖层的方法。
图10示出制造关于第四实施例的半导体器件的方法的横截面示意图。
如图10A所示,例如,常规WLBGA130由公知方法制造。在WLBGA 130中,外部连接端子(焊球)105经由布线层104形成在半导体晶片131的一侧上。
接着,如图10B所示,使用由层叠覆盖层和切割带制成的切割带(双层结构)124。将半导体晶片131的另一侧粘贴在形成相应切割带的覆盖层的一侧上。
如图10C所示,在本实施例中用刀片115从WLBGA 130制造单独芯片。为描述切割工艺,图10D和图10E示出用图10C中的圆127以扩大方式指定的切割部分。
首先,如图10D所示,用第一刀片115在半导体晶片131的一侧中(形成外部连接端子的表面)形成第一凹槽125。将第一凹槽125形成为到达半导体晶片131和覆盖层104之间的界面。
接着,如图10E所示,用第二刀片116从第一凹槽125底面的中心形成切割覆盖层103的第二凹槽126。在这里,第二刀片116的宽度比第一刀片115的宽度窄。即,第二凹槽126的宽度比第一凹槽125的宽度窄。从半导体芯片102脊线部分的覆盖层103的突出部分由第一凹槽125和第二凹槽126之间的宽度差确定。因此,任意地选择这些凹槽,可以调整突出部分以获得预定值。
其后,如图10F所示,从覆盖层103和切割片114剥离并得到半导体器件101的单独芯片。
在这里,对于上述各个实施例,描述了用刀片切割形成第一凹槽和第二凹槽的实例。然而,可以使用用激光的激光切割来形成代替刀片切割的那些凹槽。另外,可以以复合的方式使用这两种方法,例如用刀片切割形成第一凹槽和用激光切割形成第二凹槽(或用刀片切割形成第二凹槽和用激光切割形成第一凹槽)。
Claims (9)
1.一种半导体器件,包括具有形成在一侧上的外部连接端子的半导体芯片,
其中覆盖层形成在所述半导体芯片的另一侧上,以及
所述覆盖层的端部的至少一部分在所述半导体芯片的脊线部分的外面。
2.根据权利要求1所述的半导体器件,其中形成所述覆盖层以便覆盖所述半导体芯片的脊线部分。
3.根据权利要求1所述的半导体器件,其中在所述半导体芯片的一侧上提供的接合垫通过布线层连接到所述外部连接端子。
4.根据权利要求2所述的半导体器件,其中所述半导体芯片的接合垫连接到所述外部连接端子。
5.一种由半导体晶片制造半导体器件的方法,在半导体晶片的一侧上提供外部连接端子,以及在所述半导体晶片的另一侧上提供覆盖层,所述方法包括:
在所述半导体晶片中,从所述一侧到至少在所述半导体晶片和所述覆盖层之间的界面,形成具有第一宽度的凹槽;以及
用第二宽度从所述凹槽的底面切割所述覆盖层,
其中所述第二宽度比所述第一宽度窄。
6.根据权要求5所述的制造半导体器件的方法,包括在用所述第二宽度从所述凹槽的底面切割所述覆盖层之后,使所述覆盖层的端部在形成外部连接端子的一侧的方向上弯曲。
7.根据权要求6所述的制造半导体器件的方法,其中通过热处理执行使所述覆盖层弯曲。
8.根据权要求5所述的制造半导体器件的方法,其中执行形成具有所述第一宽度的凹槽以通过所述半导体晶片到达所述覆盖层的中间。
9.根据权要求5所述的制造半导体器件的方法,其中通过刀片切割或激光切割执行在所述半导体晶片中形成所述凹槽或切割所述覆盖层。
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CN108231677A (zh) * | 2016-12-14 | 2018-06-29 | 台湾积体电路制造股份有限公司 | 裁切半导体晶片的方法 |
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-
2007
- 2007-10-18 JP JP2007271178A patent/JP2009099838A/ja active Pending
-
2008
- 2008-10-14 US US12/285,744 patent/US7859097B2/en not_active Expired - Fee Related
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CN106409807A (zh) * | 2015-07-31 | 2017-02-15 | 瑞萨电子株式会社 | 半导体器件 |
CN106409807B (zh) * | 2015-07-31 | 2021-03-30 | 瑞萨电子株式会社 | 半导体器件 |
CN108231677A (zh) * | 2016-12-14 | 2018-06-29 | 台湾积体电路制造股份有限公司 | 裁切半导体晶片的方法 |
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US20090102042A1 (en) | 2009-04-23 |
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