CN104377170A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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CN104377170A
CN104377170A CN201310367493.8A CN201310367493A CN104377170A CN 104377170 A CN104377170 A CN 104377170A CN 201310367493 A CN201310367493 A CN 201310367493A CN 104377170 A CN104377170 A CN 104377170A
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semiconductor
semiconductor package
making
insulating barrier
parts according
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CN104377170B (zh
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张宏达
赖顗喆
邱启新
邱世冠
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装件及其制法，该制法先提供一半导体结构，该半导体结构包含承载件、形成于该承载件上的线路部、及结合于该线路部上的多个半导体组件，再结合压合件于该些半导体组件上，且以绝缘层包覆该些半导体组件，之后移除该承载件。以藉由该压合件的设计，以增加相邻两半导体组件间的强度，所以当移除该承载件时，能避免该半导体组件与绝缘层间的热膨胀系数不匹配所造成的碎裂问题。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件，尤指一种具晶圆级线路的半导体封装件及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。目前应用于芯片封装领域的技术，例如芯片尺寸构装(ChipScale Package,CSP)、芯片直接贴附封装(Direct Chip Attached,DCA)或多芯片模块封装(Multi－Chip Module,MCM)等覆晶型态的封装模块、或将芯片立体堆栈化整合为三维集成电路(3D IC)芯片堆栈技术等。
图1A为现有半导体封装件1的剖面示意图，该半导体封装件1于一封装基板14与半导体芯片12之间设置一硅中介板（Through Siliconinterposer,TSI）10，该硅中介板10具有导电硅穿孔（Through-silicon via,TSV）100及设于该导电硅穿孔100上的线路重布结构（Redistributionlayer,RDL）101，令该线路重布结构101藉由多个导电组件18电性结合间距较大的封装基板14的焊垫140，并形成底胶13包覆该些导电组件18，而间距较小的半导体芯片12的电极垫120藉由多个焊锡凸块121电性结合该导电硅穿孔100。之后，再形成底胶13包覆该些焊锡凸块121。
若该半导体芯片12直接结合至该封装基板14上，因该半导体芯片12与该封装基板14两者的热膨胀系数的差异甚大，所以该半导体芯片12外围的焊锡凸块121不易与该封装基板14上对应的焊垫140形成良好的接合，致使该焊锡凸块121易自该封装基板14上剥离。另一方面，因该半导体芯片12与该封装基板14之间的热膨胀系数不匹配(mismatch)，其所产生的热应力(thermal stress)与翘曲(warpage)的现象也日渐严重，致使该半导体芯片12与该封装基板14之间的电性连接可靠度(reliability)下降，且将造成信赖性测试的失败。
因此，藉由半导体基材制作的硅中介板10的设计，其与该半导体芯片12的材质接近，所以可有效避免上述所产生的问题。
然而，前述现有半导体封装件1的制法中，于制作该硅中介板10时，需形成该导电硅穿孔100，而该导电硅穿孔100的制程需于该硅中介板10上挖孔及金属填孔，致使该导电硅穿孔100的整体制程占整个该硅中介板10的制作成本达约40～50%（以12寸晶圆为例，不含人工成本），以致于最终产品的成本及价格难以降低。
此外，该硅中介板10的制作技术难度高，致使该半导体封装件1的生产量相对降低，且制作良率降低。
于是，业界遂发展出一种无需制作硅中介板的半导体封装件1’，如图1B所示，其为多个半导体芯片12藉由焊锡凸块121结合于一承载件（图略）上的线路部11上，且形成底胶13于该线路部11与各该半导体芯片12之间，再形成封装胶体16于该线路部11上以包覆各该半导体芯片12，藉以保护该些半导体芯片12，并增加该半导体封装件1’的刚性。之后，移除该线路部11下侧的承载件（图略），再形成一绝缘保护层17于该线路部11下侧，且该绝缘保护层17外露该线路部11，以供结合如焊球的导电组件18。
然而，现有半导体封装件1’中，各该半导体芯片12间之间隙极小，当移除该线路部11下侧的承载件时，因该半导体芯片12、该线路部11的内金属介电层（inter-metal dielectric,IMD）与封装胶体16间的热膨胀系数不匹配(mismatch)，致使使该线路部11的内金属介电层因应力变化过大而破裂，进而造成该些焊锡凸块121碎裂（crack）（如图1B所示的破裂处k）。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种半导体封装件及其制法，能避免该半导体组件与绝缘层间的热膨胀系数不匹配所造成的碎裂问题。
本发明的半导体封装件，包括：线路部，其具有相对的第一侧与第二侧；多个半导体组件，其设于该线路部的第一侧；压合件，其设于该些半导体组件上；以及绝缘层，其设于该线路部的第一侧，以包覆该些半导体组件。
前述的半导体封装件中，该绝缘层还包覆该压合件，例如，该压合件外露于该绝缘层表面。
前述的半导体封装件中，该绝缘层的侧面与该压合件的侧面齐平。
前述的半导体封装件中，还包括粘着材，可为芯片粘着层或热接口材料，其设于该些半导体组件与该压合件之间，例如，该粘着材还设于该绝缘层与该压合件之间。
前述的半导体封装件中，该绝缘层还设于该压合件与该些半导体组件之间。
本发明还提供一种半导体封装件的制法，包括：提供一半导体结构，该半导体结构包含承载件、形成于该承载件上的线路部、及结合于该线路部上的多个半导体组件；结合压合件于该些半导体组件上；形成绝缘层于该线路部上以包覆该些半导体组件；以及移除该承载件。
前述的制法中，该绝缘层还包覆该压合件，例如，于形成该绝缘层后，令该压合件外露于该绝缘层表面。
本发明又提供一种半导体封装件的制法，包括：提供一半导体结构，该半导体结构包含承载件、形成于该承载件上的线路部、及结合于该线路部上的多个半导体组件；形成绝缘层于该线路部上以包覆该些半导体组件；结合压合件于该些半导体组件与该绝缘层上；以及移除该承载件。
前述的两种制法中，该压合件藉由粘着材结合于该些半导体组件（及该绝缘层上）上，例如，该粘着材为芯片粘着层或热接口材料。
本发明另提供一种半导体封装件的制法，包括：提供一半导体结构，该半导体结构包含承载件、形成于该承载件上的线路部、及结合于该线路部上的多个半导体组件；提供一具有绝缘层的压合件，令该压合件藉该绝缘层结合于该线路部上，且该绝缘层包覆该些半导体组件；以及移除该承载件。
前述的制法中，该绝缘层形成于该压合件与该半导体组件之间。
前述的三种制法中，该承载件为含硅的板体。
前述的半导体封装件及三种制法中，该半导体结构还包含形成于该线路部与各该半导体组件之间的底胶。
前述的半导体封装件及三种制法中，该绝缘层还形成于该线路部与各该半导体组件之间。
前述的半导体封装件及三种制法中，该压合件为半导体挡片。
另外，前述的半导体封装件及三种制法中，还包括于移除该承载件后，外露该线路部，以供形成多个导电组件于该线路部上。
由上可知，本发明的半导体封装件及其制法，主要藉由该压合件的设计，以增加相邻两半导体组件间的强度，所以当移除该承载件时，能避免该半导体组件与绝缘层间的热膨胀系数不匹配所造成的碎裂问题。
附图说明
图1A为现有半导体封装件的剖面示意图；
图1B为现有半导体封装件的剖面示意图；
图2A至图2E为本发明的半导体封装件的制法的第一实施例的剖面示意图；其中，图2E’为图2E的其它实施例；
图3A至图3D为本发明的半导体封装件的制法的第二实施例的剖面示意图；其中，图3D’为图3D的其它实施例；以及
图4A至图4D为本发明的半导体封装件的制法的第三实施例的剖面示意图；其中，图4D’为图4D的其它实施例。
符号说明
1,1’,2,2’,3,3’,4,4’  半导体封装件
10                       硅中介板
100                      导电硅穿孔
101                      线路重布结构
11,21                    线路部
12                       半导体芯片
120                      电极垫
121                      焊锡凸块
13,23                    底胶
14                       封装基板
140                      焊垫
16                       封装胶体
17,27                    绝缘保护层
18,28                    导电组件
2a                       半导体结构
20                       承载件
21a                      第一侧
21b                      第二侧
210                      介电层
211                      线路层
212                      电性接触垫
22                       半导体组件
221                      导电凸块
24,34                    粘着材
25,35,35’,45,45’       压合件
26,36,46                 绝缘层
270                      开孔
35a,36a,45a,46a          侧面
k                        破裂处
S                        切割路径。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2E为本发明的半导体封装件2的制法的第一实施例的剖面示意图。
如图2A所示，提供一半导体结构2a，该半导体结构2a包含一承载件20、形成于该承载件20上的一线路部21、结合于该线路部21上的多个半导体组件22、及形成于该线路部21与各该半导体组件22之间的底胶23。
于本实施例中，该承载件20为含硅的板体。
此外，该线路部21包含相叠的多个介电层210与多个线路层211，并具有相对的第一侧21a与第二侧21b，该线路部21的第二侧21b结合至该承载件20上，且该些半导体组件22结合于该线路部21的第一侧21a。
又，各该半导体组件22藉由多个导电凸块221覆晶结合该线路部21的线路层211，且该底胶23包覆该些导电凸块221。
另外，该线路层211为晶圆级线路，而非封装基板级线路。目前封装基板最小的线宽与线距为12μm，而半导体制程能制作出3μm以下的线宽与线距。
如图2B所示，形成粘着材24于各该半导体组件22上。于本实施例中，该粘着材24为芯片粘着层（die attach film,DAF）或热接口材料（Thermal Interface Material,TIM），如散热胶。
如图2C所示，形成一压合件25于该粘着材24上，以增加各该半导体组件22间的强度。
于本实施例中，该压合件25为半导体挡片（dummy die），且该半导体挡片由一晶圆经切单后所得的单一挡片。
此外，于其它实施例中，也可先形成该粘着材24于该压合件25上，再将该压合件25以其上的粘着材24结合于各该半导体组件22上。
如图2D所示，形成一绝缘层26于该线路部21的第一侧21a以包覆各该半导体组件22。
于本实施例中，该绝缘层26还包覆该压合件25，且该压合件25外露于该绝缘层26表面；于其它实施例中，该压合件25也可未外露于该绝缘层26表面。
此外，该绝缘层26可为封装胶体、压合膜或涂布方式形成的层等。
如图2E所示，移除该承载件20，以外露该线路部21的第二侧21b，以供形成多个导电组件28于该线路部21的第二侧21b。之后，沿如图2D所示的切割路径S进行切单制程，以获得多个半导体封装件2。
于本实施例中，先形成多个电性连接该线路层211的电性接触垫212于该线路部21的第二侧21b，再形成一绝缘保护层27于该线路部21的第二侧21b，且该绝缘保护层27形成有多个开孔270，令该些电性接触垫212外露于各该开孔270，以供结合如焊球的导电组件28。
此外，于其它实施例中，也可先进行切单制程，再形成电性接触垫212、绝缘保护层27与导电组件28。
另外，于其它实施例中，可不形成该底胶23，而是形成该绝缘层26于该线路部21与各该半导体组件22之间，以包覆该些导电凸块221，如图2E’所示。
图3A至图3D为本发明的半导体封装件3的制法的第二实施例的剖面示意图。本实施例与第一实施例的差异在于压合件与绝缘层的制作顺序，其它步骤的制程大致相同，所以不再赘述相同处。
如图3A所示，提供一如图2A所示的半导体结构2a。
如图3B所示，形成绝缘层36于该线路部21的第一侧21a，以包覆各该半导体组件22，且令各该半导体组件22外露于该绝缘层36表面。
如图3C所示，形成一压合件35于各该半导体组件22与该绝缘层36上。
于本实施例中，该压合件35藉由粘着材34结合于各该半导体组件22与该绝缘层36上。
此外，该压合件35为尚未切单的晶圆型态半导体挡片（dummydie）。
如图3D所示，移除该承载件20，以外露该线路部21的第二侧21b，以供形成多个导电组件28于该线路部21的第二侧21b。之后，沿如图3C所示的切割路径S进行切单制程，以获得多个半导体封装件3，且该绝缘层36的侧面36a与该压合件35的侧面35a齐平。
此外，于其它实施例中，如图3D’所示，于形成该些导电组件28后，可先薄化该压合件35，以令该压合件35’的厚度减少，再进行切单制程。
图4A至图4D为本发明的半导体封装件4的制法的第三实施例的剖面示意图。本实施例与第二实施例的差异在于压合件的结合方式，其它步骤的制程大致相同，所以不再赘述相同处。
如图4A所示，提供一如第2A图所示的半导体结构2a。
如图4B所示，提供一具有绝缘层46的压合件45，且该压合件45为尚未切单的晶圆型态半导体挡片（dummy die）。
如图4C所示，该压合件45藉由该绝缘层46结合于该线路部21的第一侧21a，且该绝缘层46包覆各该半导体组件22。
于本实施例中，该绝缘层46形成于该压合件45与各该半导体组件22之间，以固定该压合件45于各该半导体组件22上。
如图4D所示，移除该承载件20，以外露该线路部21的第二侧21b，以供形成多个导电组件28于该线路部21的第二侧21b。之后，沿如图4C所示的切割路径S进行切单制程，以获得多个半导体封装件4，且该绝缘层46的侧面46a与该压合件45的侧面45a齐平。
此外，于其它实施例中，如图4D’所示，于形成该些导电组件28后，可先薄化该压合件45，以令该压合件45’的厚度减少，再进行切单制程。
本发明的制法藉由该压合件25,35,35’,45,45’结合于相邻两半导体组件22上，以增加相邻两半导体组件22间的强度，当移除该承载件20时，能避免因该半导体组件22与绝缘层26,36,46间的热膨胀系数不匹配（mismatch）而造成的导电凸块221碎裂（crack）的问题发生，所以能避免该线路部21的介电层210破裂。
本发明提供一种半导体封装件2,2’,3,3’,4,4’，包括：一线路部21、多个半导体组件22、一压合件25,35,35’,45,45’以及绝缘层26,36,46。
所述的线路部21具有相对的第一侧21a与第二侧21b。
所述的半导体组件22设于该线路部21的第一侧21a。
所述的压合件25,35,35’,45,45’设于该些半导体组件22上，且该压合件25,35,35’,45,45’为半导体挡片。
所述的绝缘层26,36,46设于该线路部21的第一侧21a，以包覆该些半导体组件22。
于一实施例中，该绝缘层26还包覆该压合件25，且该压合件25外露于该绝缘层26表面。
于一实施例中，所述的半导体封装件2还包括底胶23，其设于该线路部21的第一侧21a与各该半导体组件22之间。
于一实施例中，该绝缘层26还设于该线路部21的第一侧21a与各该半导体组件22之间。
于一实施例中，所述的半导体封装件2,2’,3,3’还包括粘着材24,34，例如芯片粘着层或热接口材料，其设于各该半导体组件22与该压合件25,35,35’之间。于一实施例中，该粘着材34还设于该绝缘层36与该压合件35,35’之间。
于一实施例中，该绝缘层36,46的侧面36a,46a与该压合件35,45的侧面35a,45a齐平。
于一实施例中，该绝缘层46还设于该压合件45,45’与各该半导体组件22之间。
于一实施例中，所述的半导体封装件2,2’,3,3’,4,4’还包括多个导电组件28，其设于该线路部21的第二侧21b。
关于前述第一至第三实施例的半导体封装件结构，较佳为形成底胶23于半导体组件22与线路部21之间；但也可于半导体组件22与线路部21之间直接填充绝缘层26,36,46。
综上所述，本发明的半导体封装件及其制法，藉由该压合件结合于相邻两半导体组件上，以增加相邻两半导体组件间的强度，以避免该半导体组件的导电凸块发生碎裂。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (38)

1.一种半导体封装件，包括：
线路部，其具有相对的第一侧与第二侧；
多个半导体组件，其设于该线路部的第一侧；
压合件，其设于该些半导体组件上；以及
绝缘层，其设于该线路部的第一侧，以包覆该些半导体组件。
2.根据权利要求1所述的半导体封装件，其特征在于，该压合件为半导体挡片。
3.根据权利要求1所述的半导体封装件，其特征在于，该绝缘层还包覆该压合件。
4.根据权利要求3所述的半导体封装件，其特征在于，该压合件外露于该绝缘层表面。
5.根据权利要求1所述的半导体封装件，其特征在于，该绝缘层的侧面与该压合件的侧面齐平。
6.根据权利要求1项所述的半导体封装件，其特征在于，该半导体封装件还包括粘着材，其设于该些半导体组件与该压合件之间。
7.根据权利要求6所述的半导体封装件，其特征在于，该粘着材还设于该绝缘层与该压合件之间。
8.根据权利要求6所述的半导体封装件，其特征在于，该粘着材为芯片粘着层或热接口材料。
9.根据权利要求1所述的半导体封装件，其特征在于，该绝缘层还设于该压合件与该些半导体组件之间。
10.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括多个导电组件，其设于该线路部的第二侧。
11.根据权利要求1所述的半导体封装件，其特征在于，该绝缘层还设于该线路部与各该半导体组件之间。
12.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括底胶，其设于该线路部与各该半导体组件之间。
13.一种半导体封装件的制法，其包括：
提供一半导体结构，其包含承载件、形成于该承载件上的线路部、及结合于该线路部上的多个半导体组件；
结合压合件于该些半导体组件上；
形成绝缘层于该线路部上以包覆该些半导体组件；以及
移除该承载件。
14.根据权利要求13所述的半导体封装件的制法，其特征在于，该承载件为含硅的板体。
15.根据权利要求13所述的半导体封装件的制法，其特征在于，该半导体结构还包含形成于该线路部与各该半导体组件之间的底胶。
16.根据权利要求13所述的半导体封装件的制法，其特征在于，该绝缘层还形成于该线路部与各该半导体组件之间。
17.根据权利要求13所述的半导体封装件的制法，其特征在于，该压合件为半导体挡片。
18.根据权利要求13所述的半导体封装件的制法，其特征在于，该压合件藉由粘着材结合于该些半导体组件上。
19.根据权利要求18所述的半导体封装件的制法，其特征在于，该粘着材为芯片粘着层或热接口材料。
20.根据权利要求13所述的半导体封装件的制法，其特征在于，该绝缘层还包覆该压合件。
21.根据权利要求20所述的半导体封装件的制法，其特征在于，该制法还包括于形成该绝缘层后，令该压合件外露于该绝缘层表面。
22.根据权利要求13所述的半导体封装件的制法，其特征在于，该制法还包括于移除该承载件后，外露该线路部，以供形成多个导电组件于该线路部上。
23.一种半导体封装件的制法，包括：
提供一半导体结构，其包含承载件、形成于该承载件上的线路部、及结合于该线路部上的多个半导体组件；
形成绝缘层于该线路部上以包覆该些半导体组件；
结合压合件于该些半导体组件与该绝缘层上；以及
移除该承载件。
24.根据权利要求23所述的半导体封装件的制法，其特征在于，该承载件为含硅的板体。
25.根据权利要求23所述的半导体封装件的制法，其特征在于，该半导体结构还包含形成于该线路部与各该半导体组件之间的底胶。
26.根据权利要求23所述的半导体封装件的制法，其特征在于，该绝缘层还形成于该线路部与各该半导体组件之间。
27.根据权利要求23所述的半导体封装件的制法，其特征在于，该制法还包括于结合该压合件前，令该些半导体组件外露于该绝缘层表面。
28.根据权利要求27所述的半导体封装件的制法，其特征在于，该压合件藉由粘着材结合于该些半导体组件与该绝缘层上。
29.根据权利要求28所述的半导体封装件的制法，其特征在于，该粘着材为芯片粘着层或热接口材料。
30.根据权利要求23所述的半导体封装件的制法，其特征在于，该压合件为半导体挡片。
31.根据权利要求23所述的半导体封装件的制法，其特征在于，该制法还包括于移除该承载件后，外露该线路部，以供形成多个导电组件于该线路部上。
32.一种半导体封装件的制法，其包括：
提供一半导体结构，其包含承载件、形成于该承载件上的线路部、及结合于该线路部上的多个半导体组件；
提供一具有绝缘层的压合件，令该压合件藉该绝缘层结合于该线路部上，且该绝缘层包覆该些半导体组件；以及
移除该承载件。
33.根据权利要求32所述的半导体封装件的制法，其特征在于，该承载件为含硅的板体。
34.根据权利要求32所述的半导体封装件的制法，其特征在于，该半导体结构还包含形成于该线路部与各该半导体组件之间的底胶。
35.根据权利要求32所述的半导体封装件的制法，其特征在于，该绝缘层还形成于该线路部与各该半导体组件之间。
36.根据权利要求32所述的半导体封装件的制法，其特征在于，该绝缘层形成于该压合件与该半导体组件之间。
37.根据权利要求32所述的半导体封装件的制法，其特征在于，该压合件为半导体挡片。
38.根据权利要求32所述的半导体封装件的制法，其特征在于，该制法还包括于移除该承载件后，外露该线路部，以供形成多个导电组件于该线路部上。
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