CN106206476A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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CN106206476A
CN106206476A CN201510237020.5A CN201510237020A CN106206476A CN 106206476 A CN106206476 A CN 106206476A CN 201510237020 A CN201510237020 A CN 201510237020A CN 106206476 A CN106206476 A CN 106206476A
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layer
electronic
preparation
line construction
metal
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黄晓君
陈贤文
陈仕卿
马光华
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种电子封装件及其制法，该电子封装件包括：具有相对的第一侧与第二侧的线路结构、设于该第一侧上的电子元件、设于该第一侧上以包覆该电子元件的封装胶体、形成于部分该第二侧上的介电层、以及设于该介电层与该线路结构上的金属结构，其中，该金属结构包含第一金属层与第二金属层，该金属结构藉其第一金属层结合至该线路结构上，且该第二金属层形成于该第一金属层与该介电层上，以藉由该线路结构取代现有硅板体，故无需制作现有导电硅穿孔，因而大幅降低制程难度及制作成本。

Description

电子封装件及其制法
技术领域
本发明涉及一种封装制程，尤指一种节省制作成本的电子封装件及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。目前应用于晶片封装领域的技术，例如晶片尺寸构装(ChipScale Package，简称CSP)、晶片直接贴附封装(Direct Chip Attached，简称DCA)或多晶片模组封装(Multi-Chip Module，简称MCM)等覆晶型态的封装模组、或将晶片立体堆迭化整合为三维积体电路(3D IC)晶片堆迭技术等。
图1A至图1F为现有3D晶片堆迭的半导体封装件1的制法的剖面示意图。
如图1A所示，提供一具有相对的转接侧10b与置晶侧10a的硅板体10，且该硅板体10的置晶侧10a上形成有多个穿孔100。
如图1B所示，将绝缘材102与导电材(如铜材)填入该些穿孔100中以形成导电硅穿孔(Through-silicon via，简称TSV)101。接着，于该置晶侧10a上形成一电性连接该导电硅穿孔101的线路重布层(Redistribution layer，简称RDL)。
具体地，该RDL的制法，其包括形成一介电层11于该置晶侧10a上，再形成一线路层12于该介电层11上，且该线路层12形成有多个位于该介电层11中并电性连接该导电硅穿孔101的导电盲孔120，之后形成一防焊层13于该介电层11与该线路层12上，且该防焊层13外露部分该线路层12。
另外，可结合多个焊锡凸块14于该线路层12的外露表面上。
如图1C所示，以机械研磨方式配合化学机械研磨(Chemical-Mechanical Polishing，简称CMP)方式研磨该转接侧10b的部分材质，使该些导电硅穿孔101的端面外露于该转接侧10b’。
如图1D所示，形成另一防焊层15于该转接侧10b’上，且该防焊层15外露该些导电硅穿孔101的端面，再结合多个导电元件16于该些导电硅穿孔101的端面上，且该导电元件16电性连接该导电硅穿孔101，其中，该导电元件16含有焊锡材料或铜凸块，且可选择性含有凸块底下金属层(Under Bump Metallurgy，简称UBM)160。
如图1E所示，沿如图1D所示的切割路径S进行切单制程，以获取多个硅中介板(Through Silicon interposer，简称TSI)1a，再将该硅中介板1a以其导电元件16设于一封装基板19上，使该封装基板19电性连接该些导电硅穿孔101。具体地，该封装基板19是以间距较大的电性接触垫190结合该些导电元件16，使该些导电元件16电性连接该些导电硅穿孔101，再以底胶191包覆该些导电元件16。
如图1F所示，将具有间距较小的电极垫的多个半导体晶片17设置于该些焊锡凸块14上，使该半导体晶片17电性连接该线路层12。具体地，该半导体晶片17以覆晶方式结合该些焊锡凸块14，再以底胶171包覆该些焊锡凸块14。
接着，形成封装材18于该封装基板19上，以令该封装材18包覆该半导体晶片17与该硅中介板1a。
最后，形成多个焊球192于该封装基板19的下侧，以供接置于一如电路板的电子装置(图略)上。
惟，现有半导体封装件1的制法中，使用硅中介板1a作为半导体晶片17与封装基板19之间讯号传递的介质，因需具备一定深宽比的控制(即该导电硅穿孔101的深宽比为100um/10um)，才能制作出适用的硅中介板1a，因而往往需耗费大量制程时间及化学药剂的成本，导致制作成本难以降低。
此外，于进行CMP制程时，该导电硅穿孔101的铜离子会渗入该硅板体10中，但由于该硅板体10为半导体材，所以各该导电硅穿孔101之间会产生桥接或漏电等问题。
又，现有电子封装件1因具有硅中介板1a而使整体厚度增加，故不利于薄型化的需求。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种电子封装件及其制法，能大幅降低制程难度及制作成本。
本发明的电子封装件，包括：线路结构，其具有相对的第一侧与第二侧；至少一电子元件，其设于该线路结构的第一侧上；封装胶体，其设于该线路结构的第一侧上，以包覆该电子元件；介电层，其形成于该线路结构的第二侧上，且该介电层外露部分该线路结构的第二侧；以及金属结构，其设于该介电层与该线路结构外露的部分第二侧上，并包含第一金属层与第二金属层，其中，该金属结构藉其第一金属层结合至该线路结构上，且该第二金属层形成于该第一金属层与该介电层上。
本发明还提供一种电子封装件的制法，其包括：提供一具有相对的第一侧与第二侧的线路结构；结合至少一电子元件于该线路结构的第一侧上；形成封装胶体于该线路结构的第一侧上，以包覆该电子元件；形成介电层于该线路结构的第二侧上，其中，部分该线路结构的第二侧外露于该介电层；以及形成金属结构于该介电层与该线路结构外露的部分第二侧上，其中，该金属结构包含第一金属层与第二金属层，供该金属结构藉其第一金属层结合至该线路结构上，且该第二金属层形成于该第一金属层与该介电层上。
前述的制法中，该介电层形成有多个外露部分该线路结构的开孔，且形成该金属结构的方式为先溅镀该第一金属层于该开孔的底面上，再溅镀该第二金属层于该第一金属层、该开孔的侧壁面与该介电层上。
前述的电子封装件及其制法中，该线路结构包含相迭的多个绝缘层与多个线路层，且该电子元件电性连接该线路层。例如，该线路结构的制程为双镶崁结构且一次成型。
前述的电子封装件及其制法中，该线路结构的第二侧具有多个外露于该介电层的电性接触垫，且该第一金属层形成于该些电性接触垫上。
前述的电子封装件及其制法中，该封装胶体外露该电子元件的部分表面。
前述的电子封装件及其制法中，该介电层为聚苯恶唑或光阻材所形成者。
前述的电子封装件及制法中，该第一金属层为钛层，且该第二金属层为铜层。
前述的电子封装件及制法中，还包括设置基板于该封装胶体上。
前述的电子封装件及制法中，还包括形成至少一导电通孔于该封装胶体中，其中，该导电通孔电性连接该线路结构。又包括设置基板于该封装胶体上，其中，该基板电性连接该导电通孔。
另外，前述的电子封装件及制法中，还包括设于该金属结构上的多个导电元件。
由上可知，本发明的电子封装件及其制法，主要藉由线路结构取代现有硅板体，并利用线路结构作为电子元件与封装基板之间讯号传递的介质，故无需制作现有导电硅穿孔，因而大幅降低制程难度及制作成本，且能避免现有各该导电硅穿孔间所产生桥接或漏电等的问题。
此外，本发明因没有使用硅中介板，故能降低整体封装件的厚度，以利于薄型化的需求。
附图说明
图1A至图1F为现有电子封装件的制法的剖面示意图；
图2A至图2G为本发明的电子封装件的制法的剖面示意图；其中，图2F’为图2F的局部放大图；以及
图3A至图3B为本发明的电子封装件的制法的另一实施例的剖面示意图。
符号说明
1 电子封装件
1a 硅中介板
10 硅板体
10a 置晶侧
10b,10b’ 转接侧
100 穿孔
101 导电硅穿孔
102 绝缘材
11 介电层
12 线路层
120 导电盲孔
13,15 防焊层
14 焊锡凸块
16,29 导电元件
160 凸块底下金属层
17 半导体晶片
171,191,23 底胶
18 封装材
19 封装基板
190 电性接触垫
192 焊球
2 电子封装件
20 承载件
200,250 离形层
21 线路结构
21a 第一侧
21b 第二侧
210 绝缘层
211 线路层
212 电性接触垫
22 电子元件
22a 作用面
22b 非作用面
221 导电凸块
24 封装胶体
25,35 基板
26 布线层
27 介电层
270 开孔
28 金属结构
280 第一金属层
281 第二金属层
340 导电通孔
S 切割路径。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，熟悉此技艺的人士可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技艺的人士的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2G为本发明的电子封装件2的制法的剖面示意图。
如图2A所示，提供一形成有线路结构21的承载件20，再结合多个电子元件22于该线路结构21上，且于该线路结构21与该电子元件22之间形成有底胶23。
于本实施例中，该承载件20为高分子有机物、玻璃、金属或半导体板材(如硅板)。
此外，该电子元件22为主动元件、被动元件或其二者的组合者，该主动元件例如为半导体晶片，而该被动元件为例如电阻、电容及电感。于此该电子元件22为主动元件，且其具有相对的作用面22a与非作用面22b。
又，该线路结构21包含相迭的多个绝缘层210与多个线路层211，并具有相对的第一侧21a与第二侧21b，使该些电子元件22的作用面22a藉由多个导电凸块221覆晶结合于该线路结构21的第一侧21a的线路层211上，而该底胶23包覆该些导电凸块221，且该线路结构21的第二侧21b具有多个电性接触垫212并结合至该承载件20上。
例如，该线路结构21的制程可为双镶崁(Dual Damascene)结构且一次成型。具体地，先形成氧化层与氮化层以作为绝缘层210，再蚀刻氧化层与氮化层以形成盲孔，接着以化学沉积、溅镀或电镀等方式形成钛层或铜层以作为导电层，之后电镀铜层以形成线路层211，最后移除多余的导电层。
另外，该承载件20与该线路结构21的第二侧21b之间可设有一离形层200。例如，该离形层200可利用加热而移除；或者，当该承载件20为玻璃板(或可透光材质)时，该离形层200可利用激光照射而移除。
如图2B所示，进行模压制程，即形成一封装胶体24于该线路结构21的第一侧21a上以包覆各该电子元件22与该底胶23。
于本实施例中，进一步移除该封装胶体24的顶部材质，以外露该些电子元件22的非作用面22b，以供散热。
如图2C所示，形成一基板25于该封装胶体24与该些电子元件22的非作用面22b上。
于本实施例中，该基板25可为高分子有机物、玻璃、金属或半导体板材(如硅板)。
此外，该基板25与该封装胶体24之间可设有一离形层250。例如，该离形层250可利用加热而移除；或者，当该基板25为玻璃板(或可透光材质)时，该离形层250可利用激光照射而移除。
如图2D所示，移除该承载件20，以外露该线路结构21的第二侧21b。
如图2E所示，形成一介电层27于该线路结构21的第二侧21b上，且该介电层27形成有多个开孔270，令该线路结构21的电性接触垫212外露于各该开孔270。
于本实施例中，该介电层27可为如聚苯恶唑(polybenzoxazole，简称PBO)或光阻材。
如图2F所示，形成一金属结构28于该介电层27与该些电性接触垫212上。
于本实施例中，该金属结构28包含第一金属层280与第二金属层281，如图2F’所示。具体地，该第一金属层280为钛层(以作为金属粘着层)且形成于该电性接触垫212上，该第二金属层281为铜层(以作为电镀用的导电层)且形成于该第一金属层280与该介电层27上。
例如，先溅镀钛层(该第一金属层280)于该开孔270的底面，但未形成于该开孔270的侧壁面上。接着，溅镀铜层(该第二金属层281)于该钛层、该开孔270的侧壁面与该介电层27上。
如图2G所示，形成多个如焊锡材料的导电元件29于该开孔270中的金属结构28(即该第二金属层281)上，再蚀刻移除该金属结构28未覆盖有该导电元件29之处(即移除该介电层27上的第二金属层281)，使剩余的该金属结构28作为凸块底下金属层(UBM)。之后，移除该基板25及离形层250。
于本实施例中，是以电镀或印刷方式形成该导电元件29，且该导电元件29电性连接该些电性接触垫212。
于后续制程中，可进行切单制程，以获得多个电子封装件2，使该电子封装件2可藉由该些导电元件28结合至一如电路板的电子装置(图略)上。
于另一方式中，可省略该金属结构28的制程，即直接将焊锡材料填入该开孔270中，使该导电元件29接触该电性接触垫212。
本发明的制法中，是以该线路结构21取代现有硅板体，并利用线路层211作为电子元件22与封装基板(图略)之间讯号传递的介质，故无需制作现有导电硅穿孔，因而大幅降低制程难度及制作成本，且能避免现有各该导电硅穿孔间所产生桥接或漏电等的问题。
此外，本发明的电子封装件2因没有使用硅中介板，故能降低整体封装件的厚度，以利于薄型化的需求。
图3A至图3B为本发明的电子封装件3的制法的另一实施例的剖面示意图。
如图3A所示，为于图2C的制程中，先于该封装胶体24中形成至少一导电通孔340，且该导电通孔340电性连接该线路结构21的线路层211，并于该封装胶体24上形成电性连接该导电通孔340的布线层26。接着，设置该基板35于该封装胶体24上，且该基板35为线路板，以令该基板35电性连接该导电通孔240与该布线层26，以供于该基板35上堆迭如封装结构、中介板、或晶片等的电子装置(图略)。
如图3B所示，接续图2D至图2G所示的制程，但无需移除该基板35，以于切单制程后，获得多个电子封装件3。
本发明的制法中，藉由该导电通孔340的设计，使该基板35能电性连接至该线路结构21的线路层211，故该基板35可供堆迭其它电子装置。
本发明提供一种电子封装件2,3，包括：具有相对的第一侧21a与第二侧21b的一线路结构21、设于该线路结构21的第一侧21a上的多个电子元件22、设于该线路结构21的第一侧21a上以包覆该电子元件22的封装胶体24、形成于该线路结构21的第二侧21b上且外露部分该第二侧21b的一介电层27、以及设于该介电层27与该线路结构21上的一金属结构28。
所述的线路结构21包含相迭的多个绝缘层210与多个线路层211，使该电子元件22电性连接该线路层211，该线路结构21的第二侧21b具有多个电性接触垫212。
所述的电子元件22具有相对的作用面22a与非作用面22b。
所述的介电层27为聚苯恶唑或光阻材，且外露该些电性接触垫212。
所述的金属结构28包含第一金属层280与第二金属层281，该第一金属层280形成于该线路结构21的第二侧21b的电性接触垫212上，且该第二金属层281形成于该第一金属层280与该介电层27上。
于一实施例中，该封装胶体24外露该电子元件22的非作用面22b。
于一实施例中，该第一金属层280为钛层。
于一实施例中，该第二金属层281为铜层。
于一实施例中，所述的电子封装件2,3还包括多个导电元件29，其设于该金属结构28上。
于一实施例中，所述的电子封装件2,3还包括设于该封装胶体24上的基板25,35。
于一实施例中，所述的电子封装件3还包括形成于该封装胶体24中的至少一导电通孔340，且该导电通孔340电性连接该线路结构21。又包括设于该封装胶体24上的基板35，且该基板35电性连接该导电通孔340。
综上所述，本发明的电子封装件及其制法，是藉由该线路结构取代现有硅板体，故无需制作现有导电硅穿孔，因而大幅降低制程难度及制作成本，且能避免现有各该导电硅穿孔间所产生桥接或漏电等的问题。
此外，本发明的电子封装件因没有使用硅中介板，故能降低整体封装件的厚度，以利于薄型化的需求。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟习此项技艺的人士均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (24)

1.一种电子封装件，其特征为，该电子封装件包括：
线路结构，其具有相对的第一侧与第二侧；
至少一电子元件，其设于该线路结构的第一侧上；
封装胶体，其设于该线路结构的第一侧上，以包覆该电子元件；
介电层，其形成于该线路结构的第二侧上，且该介电层外露部分该线路结构的第二侧；以及
金属结构，其设于该介电层与该线路结构外露的部分第二侧上，并包含第一金属层与第二金属层，其中，该金属结构藉其第一金属层结合至该线路结构上，且该第二金属层形成于该第一金属层与该介电层上。
2.如权利要求1所述的电子封装件，其特征为，该线路结构包含相迭的多个绝缘层与多个线路层，且该电子元件电性连接该线路层。
3.如权利要求1所述的电子封装件，其特征为，该线路结构的第二侧具有多个外露于该介电层的电性接触垫，且该第一金属层结合至该些电性接触垫上。
4.如权利要求1所述的电子封装件，其特征为，该封装胶体外露该电子元件的部分表面。
5.如权利要求1所述的电子封装件，其特征为，该介电层为聚苯恶唑或光阻材所形成者。
6.如权利要求1所述的电子封装件，其特征为，该第一金属层为钛层。
7.如权利要求1所述的电子封装件，其特征为，该第二金属层为铜层。
8.如权利要求1所述的电子封装件，其特征为，该电子封装件还包括设于该封装胶体上的基板。
9.如权利要求1所述的电子封装件，其特征为，该电子封装件还包括形成于该封装胶体中的至少一导电通孔，其中，该导电通孔电性连接该线路结构。
10.如权利要求9所述的电子封装件，其特征为，该电子封装件还包括设于该封装胶体上的基板，其中，该基板电性连接该导电通孔。
11.如权利要求1所述的电子封装件，其特征为，该电子封装件还包括设于该金属结构上的多个导电元件。
12.一种电子封装件的制法，其特征为，该制法包括：
提供一具有相对的第一侧与第二侧的线路结构；
结合至少一电子元件于该线路结构的第一侧上；
形成封装胶体于该线路结构的第一侧上，以包覆该电子元件；
形成介电层于该线路结构的第二侧上，其中，部分该线路结构的第二侧外露于该介电层；以及
形成金属结构于该介电层与该线路结构外露的部分第二侧上，其中，该金属结构包含第一金属层与第二金属层，供该金属结构藉其第一金属层结合至该线路结构上，且该第二金属层形成于该第一金属层与该介电层上。
13.如权利要求12所述的电子封装件的制法，其特征为，该线路结构包含相迭的多个绝缘层与多个线路层，且该电子元件电性连接该线路层。
14.如权利要求13所述的电子封装件的制法，其特征为，该线路结构的制程为双镶崁结构且一次成型。
15.如权利要求12所述的电子封装件的制法，其特征为，该线路结构的第二侧具有多个外露于该介电层的电性接触垫，且该第一金属层形成于该些电性接触垫上。
16.如权利要求12所述的电子封装件的制法，其特征为，该封装胶体外露该电子元件的部分表面。
17.如权利要求12所述的电子封装件的制法，其特征为，该介电层为聚苯恶唑或光阻材所形成者。
18.如权利要求12所述的电子封装件的制法，其特征为，该第一金属层为钛层。
19.如权利要求12所述的电子封装件的制法，其特征为，该第二金属层为铜层。
20.如权利要求12所述的电子封装件的制法，其特征为，该介电层形成有多个外露部分该线路结构的开孔，且形成该金属结构的方式先溅镀该第一金属层于该开孔的底面上，再溅镀该第二金属层于该第一金属层、该开孔的侧壁面与该介电层上。
21.如权利要求12所述的电子封装件的制法，其特征为，该制法还包括设置基板于该封装胶体上。
22.如权利要求12所述的电子封装件的制法，其特征为，该制法还包括形成至少一导电通孔于该封装胶体中，其中，该导电通孔电性连接该线路结构。
23.如权利要求22所述的电子封装件的制法，其特征为，该制法还包括设置基板于该封装胶体上，其中，该基板电性连接该导电通孔。
24.如权利要求12所述的电子封装件的制法，其特征为，该制法还包括设于该金属结构上的多个导电元件。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111354686A (zh) * 2018-12-21 2020-06-30 矽品精密工业股份有限公司 电子封装件及其制法暨封装用基板及其制法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9237648B2 (en) 2013-02-25 2016-01-12 Invensas Corporation Carrier-less silicon interposer
US9691693B2 (en) 2013-12-04 2017-06-27 Invensas Corporation Carrier-less silicon interposer using photo patterned polymer as substrate
US9437536B1 (en) 2015-05-08 2016-09-06 Invensas Corporation Reversed build-up substrate for 2.5D
US10211160B2 (en) 2015-09-08 2019-02-19 Invensas Corporation Microelectronic assembly with redistribution structure formed on carrier
US9666560B1 (en) * 2015-11-25 2017-05-30 Invensas Corporation Multi-chip microelectronic assembly with built-up fine-patterned circuit structure
US10515921B2 (en) * 2017-07-27 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of fabricating semiconductor package
TWI697081B (zh) * 2019-06-10 2020-06-21 恆勁科技股份有限公司 半導體封裝基板及其製法與電子封裝件
TWI712135B (zh) * 2019-09-16 2020-12-01 矽品精密工業股份有限公司 電子封裝件及其製法
TWI726500B (zh) * 2019-11-25 2021-05-01 東捷科技股份有限公司 封裝結構的製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101425493A (zh) * 2007-11-01 2009-05-06 台湾积体电路制造股份有限公司 无铝垫的后端集成电路的晶圆级封装结构
US20100140759A1 (en) * 2008-12-10 2010-06-10 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a Shielding Layer over a Semiconductor Die after Forming a Build-Up Interconnect Structure
CN102683322A (zh) * 2011-03-09 2012-09-19 三星半导体(中国)研究开发有限公司 Pop封装结构及其制造方法
CN104377170A (zh) * 2013-08-12 2015-02-25 矽品精密工业股份有限公司 半导体封装件及其制法
CN104505351A (zh) * 2014-12-30 2015-04-08 中国科学院微电子研究所 一种侧向互连的堆叠封装结构的制备方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5877076A (en) * 1997-10-14 1999-03-02 Industrial Technology Research Institute Opposed two-layered photoresist process for dual damascene patterning
TW449813B (en) * 2000-10-13 2001-08-11 Advanced Semiconductor Eng Semiconductor device with bump electrode
TWI234210B (en) * 2002-12-03 2005-06-11 Sanyo Electric Co Semiconductor module and manufacturing method thereof as well as wiring member of thin sheet
JP5060038B2 (ja) * 2005-10-07 2012-10-31 ルネサスエレクトロニクス株式会社 電子回路装置およびその製造方法
US7993972B2 (en) * 2008-03-04 2011-08-09 Stats Chippac, Ltd. Wafer level die integration and method therefor
KR20080102022A (ko) * 2007-05-17 2008-11-24 삼성전자주식회사 회로기판의 제조방법, 반도체 패키지의 제조방법, 이에의해 제조된 회로기판 및 반도체 패키지
US10074553B2 (en) * 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
US10204879B2 (en) * 2011-01-21 2019-02-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming wafer-level interconnect structures with advanced dielectric characteristics
US9142501B2 (en) * 2013-03-14 2015-09-22 International Business Machines Corporation Under ball metallurgy (UBM) for improved electromigration
US9299688B2 (en) * 2013-12-10 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
US10490521B2 (en) * 2014-06-26 2019-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced structure for info wafer warpage reduction

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101425493A (zh) * 2007-11-01 2009-05-06 台湾积体电路制造股份有限公司 无铝垫的后端集成电路的晶圆级封装结构
US20100140759A1 (en) * 2008-12-10 2010-06-10 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a Shielding Layer over a Semiconductor Die after Forming a Build-Up Interconnect Structure
CN102683322A (zh) * 2011-03-09 2012-09-19 三星半导体(中国)研究开发有限公司 Pop封装结构及其制造方法
CN104377170A (zh) * 2013-08-12 2015-02-25 矽品精密工业股份有限公司 半导体封装件及其制法
CN104505351A (zh) * 2014-12-30 2015-04-08 中国科学院微电子研究所 一种侧向互连的堆叠封装结构的制备方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111354686A (zh) * 2018-12-21 2020-06-30 矽品精密工业股份有限公司 电子封装件及其制法暨封装用基板及其制法
CN111354686B (zh) * 2018-12-21 2022-11-08 矽品精密工业股份有限公司 电子封装件及其制法暨封装用基板及其制法

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