CN103390600A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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Publication number
CN103390600A
CN103390600A CN2012105852013A CN201210585201A CN103390600A CN 103390600 A CN103390600 A CN 103390600A CN 2012105852013 A CN2012105852013 A CN 2012105852013A CN 201210585201 A CN201210585201 A CN 201210585201A CN 103390600 A CN103390600 A CN 103390600A
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semiconductor chip
semiconductor package
acting surface
layer
making
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CN2012105852013A
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CN103390600B (zh
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程吕义
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装件及其制法，该半导体封装件包括：线路增层、半导体芯片、电子组件与封装胶体，该半导体芯片覆晶接置于该线路增层的顶面，且具有贯穿的凸块，该电子组件接置于该半导体芯片上，该封装胶体形成于该线路增层的顶面上，且包覆该半导体芯片与电子组件。本发明能有效提高良率与增进整体散热效率。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件及其制法，尤指一种堆栈芯片型式的半导体封装件及其制法。
背景技术
随着时代的进步，现今电子产品均朝向微型化、多功能、高电性及高速运作的方向发展，为了配合此一发展趋势，半导体业者莫不积极研发体积微小、高性能、高功能、与高速度化的半导体封装件，藉以符合电子产品的要求。
请参阅第5,202,754与5,270,261号美国专利，其揭露一种半导体封装件及其制法，其主要通过于一具有多个半导体芯片的晶圆中埋设有蚀刻停止层（etch stoplayer），并将该晶圆接合（bond）至一承载板上，接着，进行蚀刻步骤，使该晶圆的厚度减少至该蚀刻停止层处，并于该晶圆中形成有贯穿的硅穿孔（Through-Silicon Via，简称TSV），且于该硅穿孔中形成有导电通孔，最后再将该晶圆从该承载板去除（debond），而最终可得到厚度较薄的半导体芯片，则可使用该半导体芯片来堆栈完成一整体体积较小且高功能的3D-IC封装件。
但是，前述现有专利在从该承载板上取下该半导体芯片时，容易使厚度较薄的半导体芯片毁损；又接合与去除的步骤容易使晶圆破裂或毁损；且现有的制法是以整片晶圆结合至承载板，而无法仅针对已知良好晶粒（known good die），进而增加整体成本；此外，已薄化的半导体芯片容易有翘曲现象，而使后续的接合工艺不易成功。
因此，如何避免上述现有技术中的种种问题，从而提供一种较佳的半导体封装件及其制法，实已成为目前亟欲解决的课题。
发明内容
有鉴于上述现有技术的缺陷，本发明的主要目的在于提供一种半导体封装件及其制法，能有效提高良率与增进整体散热效率。
本发明的半导体封装件，其包括：线路增层，其具有多个外露于其顶面的电性连接垫；第一半导体芯片，其覆晶接置于该线路增层的顶面，且具有相对的第一作用面与第一非作用面，该第一作用面具有多个电性连接该电性连接垫的第一电极垫，于该第一非作用面之侧形成有多个第一通孔，且于各该第一通孔中形成有电性连接该第一电极垫的第一凸块；电子组件，其接置于该第一半导体芯片上，且电性连接该第一凸块；以及封装胶体，其形成于该线路增层的顶面上，且包覆该第一半导体芯片与电子组件。
本发明提供另一种半导体封装件，其包括：承载板，其具有多个外露于其顶面的电性连接垫；第一半导体芯片，其覆晶接置于该承载板的顶面，且具有相对的第一作用面与第一非作用面，该第一作用面具有多个电性连接该电性连接垫的第一电极垫，于该第一非作用面之侧形成有多个第一通孔，且于各该第一通孔中形成有电性连接该第一电极垫的第一凸块，又于该第一半导体芯片的第一非作用面上形成有导热层；电子组件，其接置于该第一半导体芯片上，且电性连接该第一凸块；以及封装胶体，其形成于该承载板的顶面上，且包覆该第一半导体芯片与电子组件，并外露该导热层边缘。
本发明还提供一种半导体封装件的制法，其包括：提供一承载板，其具有相对的第一表面与第二表面，该第一表面上形成有线路增层，该线路增层具有多个外露于该线路增层顶面的电性连接垫；于该线路增层上覆晶接置第一半导体芯片，该第一半导体芯片具有相对的第一作用面与第一非作用面，该第一作用面具有多个电性连接该电性连接垫的第一电极垫；从该第一非作用面之侧薄化该第一半导体芯片；于该第一非作用面之侧形成多个第一通孔；于各该第一通孔中形成电性连接该第一电极垫的第一凸块；于该第一半导体芯片上接置电子组件，该电子组件具有相对的第二作用面与第二非作用面，该第二作用面具有多个电性连接该第一凸块的第二电极垫；以及于该线路增层上形成包覆该第一半导体芯片与电子组件的封装胶体。
本发明提供另一种半导体封装件的制法，其包括：提供一承载板，其具有相对的第一表面与第二表面，该第一表面上形成有多个电性连接垫；于该第一表面上覆晶接置第一半导体芯片，该第一半导体芯片具有相对的第一作用面与第一非作用面，该第一作用面具有多个电性连接该电性连接垫的第一电极垫；从该第一非作用面之侧薄化该第一半导体芯片；于该第一非作用面之侧形成多个第一通孔；于各该第一通孔中形成电性连接该第一电极垫的第一凸块，并于该第一半导体芯片的第一非作用面上形成导热层；于该第一半导体芯片上接置电子组件，该电子组件具有相对的第二作用面与第二非作用面，该第二作用面具有多个电性连接该第一凸块的第二电极垫；以及于该第一表面上形成包覆该第一半导体芯片与电子组件的封装胶体。
本发明提供又一种半导体封装件的制法，其包括：提供一承载板，其具有相对的第一表面与第二表面，该第一表面上形成有多个导电组件；于该第一表面上覆晶接置第一半导体芯片，该第一半导体芯片具有相对的第一作用面与第一非作用面，该第一作用面具有多个电性连接该导电组件的第一电极垫；从该第一非作用面之侧薄化该第一半导体芯片；于该第一非作用面之侧形成多个第一通孔；于各该第一通孔中形成电性连接该第一电极垫的第一凸块；于该第一半导体芯片上接置电子组件，该电子组件电性连接该第一凸块；以及于该第一表面上形成包覆该第一半导体芯片与电子组件的封装胶体。
本发明再提供一种半导体封装件的制法，其包括：提供一承载板，其具有相对的第一表面与第二表面，该第一表面上形成有线路增层，该线路增层具有多个外露于该线路增层顶面的电性连接垫；于该线路增层上覆晶接置第一半导体芯片，该第一半导体芯片具有相对的第一作用面与第一非作用面，该第一作用面具有多个电性连接该电性连接垫的第一电极垫，该第一半导体芯片中具有电性连接该第一电极垫的第一凸块；从该第一非作用面之侧薄化该第一半导体芯片，以令该第一凸块外露于该第一非作用面；于该第一半导体芯片上接置电子组件，该电子组件电性连接该第一凸块；以及于该线路增层上形成包覆该第一半导体芯片与电子组件的封装胶体。
由上可知，因为本发明直接在承载板上开始进行工艺，且后续不包括去除晶圆的步骤，所以可避免良率的减低；又本发明可先在该承载板上进行电性测试，并仅在电性测试无误之处接置良品芯片，因此能减少良率的损失；此外，半导体芯片是在接置在承载板上后才进行薄化步骤，而能避免薄化后的半导体芯片不易进行堆栈或接合步骤的缺点；况且，本发明最终可无须承载板，所以能有效减少封装件的厚度；此外，本发明还可设置有导热层与散热罩，所以可提供较佳的散热效率。
附图说明
图1-1至图1-33为本发明的半导体封装件及其制法的第一实施例的剖视图，其中，图1-7’至图1-8’为图1-7至图1-12的另一实施方法，图1-12’与图1-17’分别为图1-12与图1-17的另一实施例，图1-21’至图1-22’为图1-21至1-25的另一实施方法，图1-32’为图1-32的另一实施例；
图2-1至图2-3为本发明的半导体封装件及其制法的第二实施例的剖视图；
图3-1至图3-10为本发明的半导体封装件及其制法的第三实施例的剖视图；
图4为本发明的半导体封装件的第四实施例的剖视图，其中，图4’为图4的另一实施例；
图5-1至图5-5为本发明的半导体封装件及其制法的第五实施例的剖视图；
图6-1至图6-6为本发明的半导体封装件及其制法的第六实施例的剖视图，其中，图6-6’为图6-6的另一实施例；以及
图7-1至图7-5与图8-1至图8-3为本发明的半导体封装件及其制法的第七实施例的剖视图，其中，图8-1至图8-3为图7-4至图7-5的另一实施方法。
主要组件符号说明
10             承载板
10a            第一表面
10b            第二表面
11a            第一介电层
110a           第一介电层开孔
11b            第二介电层
110b           第二介电层开孔
12a            第一导电层
12b            第一线路层
121            焊垫
13             第一阻层
130            第一阻层开孔
131            电性连接垫
14             第二导电层
15             第二阻层
150            第二阻层开孔
16             第一焊料
161,175        化镍钯浸金层
17             第一半导体芯片
17a            第一作用面
17b            第一非作用面
170            第一通孔
171            第一电极垫
172,262,272    铜柱
173,263,273    第三焊料
174            第三线路层
18a            第一底充材料
18b            第二底充材料
18c            第三底充材料
19a            第一封装胶体
19b            第二封装胶体
19c            第三封装胶体
20             第三阻层
200            第三阻层开孔
21             第一绝缘层
22             第四阻层
220            第四阻层开孔
23             第三导电层
24            第五阻层
240           第五阻层开孔
25a           第一凸块
25b           第二凸块
26            第二半导体芯片
26a           第二作用面
26b           第二非作用面
261           第二电极垫
27            第三半导体芯片
27a           第三作用面
27b           第三非作用面
271           第三电极垫
28            焊球
29            第二线路层
30            第三介电层
300           第三介电层开孔
31            第二焊料
32            导热层
33            第六阻层
330           第六阻层开孔
34            第三凸块
35            散热胶
36            散热罩
37            第四介电层。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“顶”、“底”、“侧”、“外”、“U形”、“上”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
第一实施例
请参阅图1-1至图1-33，其为本发明的半导体封装件及其制法的第一实施例的剖视图。
如图1-1所示，提供一承载板10，其具有相对的第一表面10a与第二表面10b，该第一表面10a上形成第一介电层11a，且该第一介电层11a具有外露部分该第一表面10a的第一介电层开孔110a；其中，该承载板10可为硅晶圆、镀铝晶圆或玻璃薄板，但不以此为限，若该承载板10表面具导电特性(如镀铝晶圆)，即可进行电性测试以得到其上的线路的良率，该第一介电层11a的材质可为BCB（Benzocyclo-buthene）、聚酰亚胺（polyimide）或PBO（polybenzoxazole）等的高分子绝缘材料，也可为二氧化硅（SiO2）或氮化硅（Si3N4）等的绝缘材料。
如图1-2所示，于该第一表面10a与第一介电层11a上以溅镀方式形成一第一导电层12a。
如图1-3所示，于该第一导电层12a上形成第一阻层13，且该第一阻层13具有外露部分该第一导电层12a的第一阻层开孔130。
如图1-4所示，于该第一导电层12a上形成第一线路层12b，该第一线路层12b的材质可为铜或铝。
如图1-5所示，移除该第一阻层13及其所覆盖的第一导电层12a，此时，该第一介电层11a、剩余的第一导电层12a与第一线路层12b构成一线路增层，但该线路增层的型式不以图标者为限。
如图1-6所示，于该第一介电层11a与第一线路层12b上形成第二介电层11b，且该第二介电层11b具有多个第二介电层开孔110b，以对应外露该第一线路层12b的电性连接垫131，该第二介电层11b的材质可为BCB（Benzocyclo-buthene）、聚酰亚胺（polyimide）或PBO（polybenzoxazole）等的高分子绝缘材料，也可为二氧化硅（SiO2）或氮化硅（Si3N4）等的绝缘材料。
如图1-7所示，于该第二介电层11b与第一线路层12b上以溅镀方式形成一第二导电层14。
如图1-8所示，于该第二导电层14上形成第二阻层15，且该第二阻层15具有外露部分该第二导电层14的第二阻层开孔150。
如图1-9所示，于该第二导电层14上形成材质例如为锡银的第一焊料16。
如图1-10所示，移除该第二阻层15及其所覆盖的第二导电层14。
如图1-11所示，进行回焊步骤。
如图1-12所示，提供一例如为第一半导体芯片17的电子组件，该第一半导体芯片17具有相对的第一作用面17a与第一非作用面17b，该第一作用面17a具有多个第一电极垫171，且该第一电极垫171上形成有铜柱172与其上的第三焊料173。或者，如图1-12’所示，该第一电极垫171上仅形成有第三焊料173，而无铜柱172，以下仅以第1-12图为代表来例示说明。
要注意的是，前述图1-7至图1-12的步骤也可简化为化镍钯浸金（Electroless-Nickel-Electroless-Palladium-Immersion-Gold，简称ENEPIG）的工艺或类似工艺，以方便后续与半导体芯片的焊料对接；例如，如图1-7’至图1-8’所示，于该第二介电层开孔110b中形成化镍钯浸金层161，并省去图1-11的回焊步骤，且使该电性连接垫131通过化镍钯浸金层161电性连接后续覆晶的第一半导体芯片17的第一电极垫171；或者，将图1-9的步骤改为化镍钯浸金（ENEPIG）的工艺或类似工艺，以增加后续与半导体芯片的焊料对接的面积，并可省去图1-11的回焊步骤，然此为本发明所属技术领域的通常知识者依据本说明书所能了解，所以不在此加以赘述与图标。
如图1-13所示，于该第一焊料16上覆晶接置该第一半导体芯片17，且于该第一半导体芯片17与第二介电层11b之间形成第一底充材料18a。
如图1-14所示，于该第二介电层11b上形成包覆该第一半导体芯片17与第一底充材料18a的第一封装胶体19a。
如图1-15所示，以例如研磨的方式从该第一非作用面17b之侧移除部分第一封装胶体19a，并薄化该第一半导体芯片17。
如图1-16所示，于该第一半导体芯片17与第一封装胶体19a上形成第三阻层20，且该第三阻层20具有多个外露该第一非作用面17b的第三阻层开孔200，各该第三阻层开孔200分别对应各该第一电极垫171。
如图1-17所示，移除该第三阻层开孔200中的部分第一半导体芯片17，以定义出多个外露该第一电极垫171的第一通孔170，并移除该第三阻层20。于其它实施例中，该第一通孔170也可外露与该第一电极垫171电性连接的任一第三线路层174，如图1-17’所示。
如图1-18所示，于该第一非作用面17b、第一封装胶体19a与第一电极垫171上形成第一绝缘层21，形成该第一绝缘层21的方式可为电浆增强式化学气相沉积（PECVD），且该第一绝缘层21的材质可为Si3N4或SiO2。
如图1-19所示，于该第一绝缘层21上形成第四阻层22，且该第四阻层22具有多个第四阻层开孔220，以对应外露该第一封装胶体19a与部分该第一电极垫171上的第一绝缘层21。
如图1-20所示，通过干蚀刻移除未被该第四阻层22所覆盖的第一绝缘层21，接着移除该第四阻层22。
要补充说明的是，于前述图1-18至图1-20的步骤中，该第一绝缘层21的材质也可改用感光型的BCB（Benzocyclo-buthene）、聚酰亚胺（polyimide）或PBO（polybenzoxazole）等材料并进行涂布、曝光与显影，以降低成本并使该第一绝缘层21具有弹性，进而吸收该第一半导体芯片17的第一通孔170中的导体的热膨胀应力。
如图1-21所示，于该第一绝缘层21、第一封装胶体19a与部分该第一电极垫171上形成作为阻障层及凸块底下金属层的第三导电层23。
如图1-22所示，于该第三导电层23上形成第五阻层24，且该第五阻层24具有多个对应该第一通孔170的第五阻层开孔240。
如图1-23所示，于各该第五阻层开孔240中形成第一凸块25a，形成该第一凸块25a的方式可为电镀、化镍钯浸金层工艺或印刷锡膏，且该第一凸块25a的材质可为镍、锡、银、铜、钯、金、铝的其中一者或其组合。
如图1-24所示，移除该第五阻层24及其所覆盖的第三导电层23，并进行回焊步骤。
如图1-25所示，提供一例如为第二半导体芯片26的电子组件，该第二半导体芯片26具有相对的第二作用面26a与第二非作用面26b，该第二作用面26a具有多个第二电极垫261，且该第二电极垫261上形成有铜柱262与其上的第三焊料263。
要注意的是，前述图1-21至图1-25的步骤也可简化为化镍钯浸金（Electroless-Nickel-Electroless-Palladium-Immersion-Gold，简称ENEPIG）的工艺或类似工艺，以方便后续与半导体芯片的焊料对接；例如，如图1-21’至图1-22’所示，于该第一电极垫171上形成化镍钯浸金层175，并省去图1-24的回焊步骤，且使该第一电极垫171通过化镍钯浸金层175电性连接后续覆晶的第二半导体芯片26的第二电极垫261；或者，将图1-23的步骤改为化镍钯浸金（ENEPIG）的工艺或类似工艺，以增加后续与半导体芯片的焊料对接的面积，并可省去图1-24的回焊步骤，然此为本发明所属技术领域的通常知识者依据本说明书所能了解，所以不在此加以赘述与图标。
如图1-26所示，将该第二半导体芯片26覆晶接置于该第一半导体芯片17的第一凸块25a上，并重复前述图1-13至图1-24的步骤，以形成第二底充材料18b、第二封装胶体19b与第二凸块25b等。
如图1-27所示，提供一例如为第三半导体芯片27的电子组件，该第三半导体芯片27具有相对的第三作用面27a与第三非作用面27b，该第三作用面27a具有多个第三电极垫271，且该第三电极垫271上形成有铜柱272与其上的第三焊料273；要补充说明的是，于其它实施例中，该电子组件也可为被动组件或封装件。
如图1-28所示，将该第三半导体芯片27覆晶接置于该第二半导体芯片26的第二凸块25b上，并重复前述图1-13至图1-14的步骤，以形成第三底充材料18c与第三封装胶体19c等。
如图1-29所示，从该第三半导体芯片27之侧研磨移除部分该第三封装胶体19c；于其它实施例中，也可研磨至该第三半导体芯片27的第三非作用面27b外露，以增加散热效果。
如图1-30所示，研磨移除部分该承载板10，若该该承载板10为硅晶圆，则可用干蚀刻及化学机械研磨（CMP）的方式去除之。
如图1-31所示，通过干蚀刻或化学机械研磨（CMP）来完全移除该承载板10，以外露部分该第一导电层12a做为焊垫121。
如图1-32所示，于该焊垫121上设置焊球28；或者，也可于该焊垫121形成多层的线路增层，再设置焊球28，如图1-32’所示，但是详细的实施内容为本发明所属技术领域的通常知识者依据本说明书所能了解，所以不在此加以赘述。
如图1-33所示，进行切单（singulation）工艺。
要补充说明的是，于图1-11、图1-13、图1-14、图1-15、图1-24或图1-26的步骤后，可薄化该承载板10或于该承载板10的底面上涂布一层BCB（Benzocyclo-buthene）、聚酰亚胺（polyimide）或PBO（polybenzoxazole）等的高分子绝缘材料、或者二氧化硅（SiO2）或氮化硅（Si3N4）等的绝缘材料，藉以调整该承载板10的表面应力，进而降低整体的翘曲。
第二实施例
请参阅图2-1至图2-3，其为本发明的半导体封装件及其制法的第二实施例的剖视图。
如图2-1所示，其接续自图1-21，于该第三导电层23上形成第五阻层24，且该第五阻层24具有多个对应该第一通孔170及部分第一非作用面17b的第五阻层开孔240，并于各该第五阻层开孔240中形成第一凸块25a与电性连接该第一凸块25a的第二线路层29。
如图2-2所示，移除该第五阻层24及其所覆盖的第三导电层23。
如图2-3所示，于该第一绝缘层21、第一封装胶体19a与第二线路层29上形成第三介电层30，该第三介电层30具有多个外露部分该第二线路层29的第三介电层开孔300，并于该第三介电层开孔300中形成凸块底下金属层（Under BumpMetallurgy，简称UBM）与第二焊料31。接着，可依循前一实施例的方式来进行堆栈半导体芯片、被动组件或封装件等封装步骤，所以不在此加以赘述。
第三实施例
请参阅图3-1至图3-10，其为本发明的半导体封装件及其制法的第三实施例的剖视图。
如图3-1所示，其接续自图1-21，于该第三导电层23上形成第五阻层24，且该第五阻层24具有多个对应该第一通孔170、外露部分该第一非作用面17b与部分该第一封装胶体19a的第五阻层开孔240。
如图3-2所示，于该第五阻层开孔240中各自形成材质例如为铜的第一凸块25a与导热层32，该第一凸块25a位于该第一通孔170中，该导热层32位于该第一非作用面17b与第一封装胶体19a上。
如图3-3所示，移除该第五阻层24。
如图3-4所示，形成覆盖该导热层32的第六阻层33，且该第六阻层33具有外露该第一凸块25a的第六阻层开孔330。
如图3-5所示，于该第六阻层开孔330中形成第三凸块34与第二焊料31，该第三凸块34的材质为铜或镍，该第二焊料31的材质为锡银。
如图3-6所示，移除该第六阻层33及其所覆盖的第三导电层23。
如图3-7所示，于该第一绝缘层21、第一封装胶体19a与导热层32上形成第三介电层30，该第三介电层30具有多个外露该第三凸块34、第二焊料31及部分第一封装胶体19a的第三介电层开孔300。
如图3-8所示，进行回焊步骤。
如图3-9所示，提供一第二半导体芯片26，该第二半导体芯片26具有相对的第二作用面26a与第二非作用面26b，该第二作用面26a具有多个第二电极垫261。
如图3-10所示，将该第二半导体芯片26覆晶接置于该第三凸块34上，并依据第一实施例的概念进行封装与切单步骤，以形成第二底充材料18b、第二封装胶体19b与焊球28等，且该导热层32边缘外露于封装件之外；其中，该第二底充材料18b填入该第三介电层开孔300中，以增加该第二底充材料18b与第一封装胶体19a的接触面积，而可避免脱层。
第四实施例
请参阅图4，其为本发明的半导体封装件的第四实施例的剖视图。
本实施例大致相同于前一实施例，其主要不同点在于本实施例还于该第一封装胶体19a、第二封装胶体19b与第二非作用面26b外依序形成散热胶35与设置一U形的散热罩36。
要注意的是，该散热罩36可通过散热胶35连接该导热层32，且部分该第三凸块34可用来接地，而连接该导热层32，如图4’所示。
第五实施例
请参阅图5-1至图5-5，其为本发明的半导体封装件及其制法的第五实施例的剖视图。
本实施例大致相同于第一实施例，其主要不同点在于本实施例的承载板采用内部与表面具有线路的电路板或封装基板，且最终并不移除该承载板，至于其它具体内容可参照第一实施例，所以不在此加以赘述。
如图5-1所示，提供一承载板10与第一半导体芯片17，该承载板10为内部与表面具有线路的电路板或封装基板。
如图5-2所示，将该第一半导体芯片17覆晶接置于该承载板10上，于该第一半导体芯片17与承载板10之间形成第一底充材料18a，再于该承载板10上形成包覆该第一半导体芯片17与第一底充材料18a的第一封装胶体19a，且进行研磨步骤。
如图5-3所示，于该第一半导体芯片17与第一封装胶体19a上形成导热层32与第三凸块34。
如图5-4所示，于该第三凸块34上覆晶接置第二半导体芯片26，并形成第二底充材料18b与第二封装胶体19b。
如图5-5所示，进行研磨步骤，并设置焊球28，且进行切单步骤。
第六实施例
请参阅图6-1至图6-6，其为本发明的半导体封装件及其制法的第六实施例的剖视图，其中，图6-6’为图6-6的另一实施例。
本实施例大致相同于第一实施例，其主要不同点在于本实施例为未先形成有该线路增层，而直接于该承载板10上形成第一导电层12a与例如为第一焊料16或化镍钯浸金层的导电组件，接着，进行如图1-12至图1-31所示的步骤，并于外露的该第一导电层12a上形成焊球28，而成为图6-6的结构；或者，于外露的该第一导电层12a上形成线路增层后，再形成焊球28，而成为图6-6’的结构。至于本实施例的其它具体实施内容可参照第一实施例，所以不在此加以赘述。
第七实施例
请参阅图7-1至图7-5，其为本发明的半导体封装件及其制法的第七实施例的剖视图。
本实施例为延续自图1-11且大致相同于第一实施例，其主要不同点在于本实施例的第一半导体芯片17中具有材质例如为铜的第一凸块25a，且后续从该第一非作用面17b进行薄化工艺以外露该第一凸块25a，并于该第一非作用面17b与第一封装胶体19a上形成外露该第一凸块25a的第四介电层37，再通过该第一凸块25a电性连接后续堆栈的半导体芯片，本实施例之后续其它具体实施内容可参照第一实施例，所以不在此加以图标与赘述。
要注意的是，于第七实施例中，进行薄化工艺时可仅薄化该第一半导体芯片17，使该第一凸块25a突出于该第一非作用面17b，再于该第一非作用面17b、第一封装胶体19a与第一凸块25a上涂布第四介电层37，并进行研磨工艺，以移除部分该第一凸块25a与第四介电层37，并外露该第一凸块25a的顶端，以供后续电性连接半导体芯片之用，如图8-1至图8-3所示。
此外，第七实施例的具有第一凸块25a的第一半导体芯片17同样可应用于第二实施例至第六实施例中，但详细的实施内容为本发明所属技术领域的通常知识者依据本说明书所能了解，所以不在此加以赘述。
要补充说明的是，本发明所述的半导体芯片可通过焊锡、不导电胶（NCP）、异向性导电膜（ACF）或异方性导电胶（ACP）等以电性连接其它半导体芯片或电子组件；且于其它实施例中，可仅使用底充材料或封装胶体来包覆各半导体芯片或电子组件；又本发明的半导体芯片也可用层叠的半导体芯片来取代；此外，本发明的导电层的材质可为Ti、Cu、Ni、V、Al、W、Au、或其组合，但不局限于上述的材质；而且，本发明所述的工艺中，电镀锡银也可含铜/镍/锗等。
本发明还提供一种半导体封装件，其包括：线路增层，其具有多个外露于其顶面的电性连接垫131；第一半导体芯片17，其覆晶接置于该线路增层的顶面，且具有相对的第一作用面17a与第一非作用面17b，该第一作用面17a具有多个电性连接该电性连接垫131的第一电极垫171，于该第一非作用面17b之侧形成有多个外露该第一电极垫171的第一通孔170，且于各该第一通孔170中形成有电性连接该第一电极垫171的第一凸块25a；电子组件，其接置于该第一半导体芯片17上，且电性连接该第一凸块25a；以及封装胶体，其形成于该线路增层的顶面上，且包覆该第一半导体芯片17与电子组件。
本发明还提供另一种半导体封装件，其包括：承载板10，其具有多个外露于其顶面的电性连接垫131；第一半导体芯片17，其覆晶接置于该承载板10的顶面，且具有相对的第一作用面17a与第一非作用面17b，该第一作用面17a具有多个电性连接该电性连接垫131的第一电极垫171，于该第一非作用面17b之侧形成有多个第一通孔170，且于各该第一通孔170中形成有电性连接该第一电极垫171的第一凸块25a，又于该第一半导体芯片17的第一非作用面17b上形成有导热层32；电子组件，其接置于该第一半导体芯片17上，且电性连接该第一凸块25a；以及封装胶体，其形成于该承载板10的顶面上，且包覆该第一半导体芯片17与电子组件。
前述的半导体封装件中，该第一通孔170外露该第一电极垫171，该第一通孔170外露与该第一电极垫171电性连接的任一线路层，且该第一凸块25a的材质为镍、锡、银、铜、钯、金、铝的其中一者或其组合。
于本发明的半导体封装件中，该线路增层具有多个外露于底面的焊垫121，且若无线路增层，则该承载板10为电路板或封装基板。
所述的半导体封装件中，该电子组件为半导体芯片、被动组件或封装件，该电性连接垫131的顶面还包括第二导电层14与其上的第一焊料16，该第一半导体芯片17与线路增层之间还形成有第一底充材料（underfill）18a，且该第一半导体芯片17与第二半导体芯片26之间还形成有第二底充材料18b。
又于前述的半导体封装件中，该封装胶体包括包覆该第一半导体芯片17的第一封装胶体19a与包覆该第二半导体芯片26的第二封装胶体19b。
依上所述的半导体封装件，该第一半导体芯片17与电子组件之间还设置有第二半导体芯片26，于该第一半导体芯片17的第一非作用面17b上还可形成有电性连接该第一凸块25a的第二线路层29，且还可包括设于该封装胶体外的散热罩36。
又于本发明的半导体封装件中，该散热罩36与封装胶体之间还形成有散热胶35，且该散热罩36的外形呈U形。
又于所述的半导体封装件中，于该第一半导体芯片17的第一非作用面17b上还形成有导热层32，并还包括设于该封装胶体外的散热罩36，且该散热罩36连接该导热层32。
综上所述，相比于现有技术，由于本发明直接在承载板上开始进行工艺，且后续并不使用去结合（debond）的步骤，所以可避免良率的减低；又本发明可先在该承载板上进行电性测试，并仅在电性测试无误之处接置良品芯片，因此能减少良率的损失；此外，半导体芯片是在接置在承载板上后才进行薄化步骤，而能避免薄化后的半导体芯片不易进行堆栈或接合步骤的缺点；况且，本发明最终可无须承载板，所以能有效减少封装件的厚度；此外，本发明还可设置有导热层与散热罩，所以可提供较佳的散热效率。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (36)

1.一种半导体封装件，其包括：
线路增层，其具有多个外露于其顶面的电性连接垫；
第一半导体芯片，其覆晶接置于该线路增层的顶面，且具有相对的第一作用面与第一非作用面，该第一作用面具有多个电性连接该电性连接垫的第一电极垫，于该第一非作用面之侧形成有多个第一通孔，且于各该第一通孔中形成有电性连接该第一电极垫的第一凸块；
电子组件，其接置于该第一半导体芯片上，且电性连接该第一凸块；以及
封装胶体，其形成于该线路增层的顶面上，且包覆该第一半导体芯片与电子组件。
2.一种半导体封装件，其包括：
承载板，其具有多个外露于其顶面的电性连接垫；
第一半导体芯片，其覆晶接置于该承载板的顶面，且具有相对的第一作用面与第一非作用面，该第一作用面具有多个电性连接该电性连接垫的第一电极垫，于该第一非作用面之侧形成有多个第一通孔，且于各该第一通孔中形成有电性连接该第一电极垫的第一凸块，又于该第一半导体芯片的第一非作用面上形成有导热层；
电子组件，其接置于该第一半导体芯片上，且电性连接该第一凸块；以及
封装胶体，其形成于该承载板的顶面上，且包覆该第一半导体芯片与电子组件，并外露该导热层边缘。
3.根据权利要求1或2所述的半导体封装件，其特征在于，该第一通孔外露该第一电极垫。
4.根据权利要求1或2所述的半导体封装件，其特征在于，该第一通孔外露与该第一电极垫电性连接的任一线路层。
5.根据权利要求1或2所述的半导体封装件，其特征在于，该第一凸块的材质为镍、锡、银、铜、钯、金、铝的其中一者或其组合。
6.根据权利要求1所述的半导体封装件，其特征在于，该线路增层具有多个外露于其底面的焊垫。
7.根据权利要求1或2所述的半导体封装件，其特征在于，该电子组件为半导体芯片、被动组件或封装件。
8.根据权利要求2所述的半导体封装件，其特征在于，该承载板为电路板或封装基板。
9.根据权利要求1所述的半导体封装件，其特征在于，该电性连接垫的顶面还包括导电层与其上的第一焊料。
10.根据权利要求1或2所述的半导体封装件，其特征在于，该封装胶体包括包覆该第一半导体芯片的第一封装胶体与包覆该电子组件的第二封装胶体。
11.根据权利要求1或2所述的半导体封装件，其特征在于，该第一半导体芯片与电子组件之间还设置有第二半导体芯片。
12.根据权利要求1或2所述的半导体封装件，其特征在于，于该第一半导体芯片的第一非作用面上还形成有电性连接该第一凸块的线路层。
13.根据权利要求1或2所述的半导体封装件，其特征在于，该半导体封装件还包括散热罩，其设于该封装胶体外。
14.根据权利要求13所述的半导体封装件，其特征在于，该散热罩与封装胶体之间还形成有散热胶。
15.根据权利要求1所述的半导体封装件，其特征在于，于该第一半导体芯片的第一非作用面上还形成有导热层。
16.根据权利要求2或15所述的半导体封装件，其特征在于，该半导体封装件还包括散热罩，其设于该封装胶体外，且该散热罩连接该导热层。
17.一种半导体封装件的制法，其包括：
提供一承载板，其具有相对的第一表面与第二表面，该第一表面上形成有线路增层，该线路增层具有多个外露于该线路增层顶面的电性连接垫；
于该线路增层上覆晶接置第一半导体芯片，该第一半导体芯片具有相对的第一作用面与第一非作用面，该第一作用面具有多个电性连接该电性连接垫的第一电极垫；
从该第一非作用面之侧薄化该第一半导体芯片；
于该第一非作用面之侧形成多个第一通孔；
于各该第一通孔中形成电性连接该第一电极垫的第一凸块；
于该第一半导体芯片上接置电子组件，该电子组件电性连接该第一凸块；以及
于该线路增层上形成包覆该第一半导体芯片与电子组件的封装胶体。
18.一种半导体封装件的制法，其包括：
提供一承载板，其具有相对的第一表面与第二表面，该第一表面上形成有多个电性连接垫；
于该第一表面上覆晶接置第一半导体芯片，该第一半导体芯片具有相对的第一作用面与第一非作用面，该第一作用面具有多个电性连接该电性连接垫的第一电极垫；
从该第一非作用面之侧薄化该第一半导体芯片；
于该第一非作用面之侧形成多个第一通孔；
于各该第一通孔中形成电性连接该第一电极垫的第一凸块，并于该第一半导体芯片的第一非作用面上形成导热层；
于该第一半导体芯片上接置电子组件，该电子组件电性连接该第一凸块；以及
于该第一表面上形成包覆该第一半导体芯片与电子组件的封装胶体。
19.一种半导体封装件的制法，其包括：
提供一承载板，其具有相对的第一表面与第二表面，该第一表面上形成有多个导电组件；
于该第一表面上覆晶接置第一半导体芯片，该第一半导体芯片具有相对的第一作用面与第一非作用面，该第一作用面具有多个电性连接该导电组件的第一电极垫；
从该第一非作用面之侧薄化该第一半导体芯片；
于该第一非作用面之侧形成多个第一通孔；
于各该第一通孔中形成电性连接该第一电极垫的第一凸块；
于该第一半导体芯片上接置电子组件，该电子组件电性连接该第一凸块；以及
于该第一表面上形成包覆该第一半导体芯片与电子组件的封装胶体。
20.一种半导体封装件的制法，其包括：
提供一承载板，其具有相对的第一表面与第二表面，该第一表面上形成有线路增层，该线路增层具有多个外露于该线路增层顶面的电性连接垫；
于该线路增层上覆晶接置第一半导体芯片，该第一半导体芯片具有相对的第一作用面与第一非作用面，该第一作用面具有多个电性连接该电性连接垫的第一电极垫，该第一半导体芯片中具有电性连接该第一电极垫的第一凸块；
从该第一非作用面之侧薄化该第一半导体芯片，以令该第一凸块外露于该第一非作用面；
于该第一半导体芯片上接置电子组件，该电子组件电性连接该第一凸块；以及
于该线路增层上形成包覆该第一半导体芯片与电子组件的封装胶体。
21.根据权利要求17、18或19所述的半导体封装件的制法，其特征在于，该第一通孔外露该第一电极垫。
22.根据权利要求17、18或19所述的半导体封装件的制法，其特征在于，该第一通孔外露与该第一电极垫电性连接的任一线路层。
23.根据权利要求17、18或19所述的半导体封装件的制法，其特征在于，该第一凸块以电镀、化镍钯浸金层工艺或印刷锡膏并回焊形成。
24.根据权利要求17或20所述的半导体封装件的制法，其特征在于，该线路增层具有多个接触该承载板的第一表面的焊垫，且该制法还包括移除该承载板，以外露该等焊垫。
25.根据权利要求17、18、19或20所述的半导体封装件的制法，其特征在于，该电子组件为半导体芯片、被动组件或封装件。
26.根据权利要求17、19或20所述的半导体封装件的制法，其特征在于，该承载板为硅晶圆、镀铝晶圆或玻璃薄板。
27.根据权利要求18所述的半导体封装件的制法，其特征在于，该承载板为电路板或封装基板。
28.根据权利要求17或20所述的半导体封装件的制法，其特征在于，该电性连接垫的顶面还包括第一焊料或化镍钯浸金层。
29.根据权利要求17、18、19或20所述的半导体封装件的制法，其特征在于，该封装胶体包括包覆该第一半导体芯片的第一封装胶体与包覆该电子组件的第二封装胶体。
30.根据权利要求17、18、19或20所述的半导体封装件的制法，其特征在于，该第一半导体芯片与电子组件之间还设置有第二半导体芯片。
31.根据权利要求17、18、19或20所述的半导体封装件的制法，其特征在于，还包括于该第一半导体芯片的第一非作用面上形成电性连接该第一凸块的线路层。
32.根据权利要求17、18、19或20所述的半导体封装件的制法，还包括于该封装胶体外设置散热罩。
33.根据权利要求32所述的半导体封装件的制法，其特征在于，该散热罩与封装胶体之间还形成有散热胶。
34.根据权利要求17、19或20所述的半导体封装件的制法，其特征在于，该制法包括于该第一半导体芯片的第一非作用面上形成导热层。
35.根据权利要求18所述的半导体封装件的制法，其特征在于，该制法还包括于该封装胶体外设置散热罩，且该散热罩连接该导热层。
36.根据权利要求19项所述的半导体封装件的制法，其特征在于，该导电组件为焊料或化镍钯浸金层。
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