TWI527170B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TWI527170B
TWI527170B TW101116801A TW101116801A TWI527170B TW I527170 B TWI527170 B TW I527170B TW 101116801 A TW101116801 A TW 101116801A TW 101116801 A TW101116801 A TW 101116801A TW I527170 B TWI527170 B TW I527170B
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Taiwan
Prior art keywords
semiconductor wafer
layer
active surface
bump
semiconductor package
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TW101116801A
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English (en)
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TW201347113A (zh
Inventor
程呂義
Original Assignee
矽品精密工業股份有限公司
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Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW101116801A priority Critical patent/TWI527170B/zh
Priority to US13/628,549 priority patent/US9997481B2/en
Priority to CN201210585201.3A priority patent/CN103390600B/zh
Publication of TW201347113A publication Critical patent/TW201347113A/zh
Application granted granted Critical
Publication of TWI527170B publication Critical patent/TWI527170B/zh
Priority to US15/975,232 priority patent/US10622323B2/en
Priority to US16/742,040 priority patent/US11101235B2/en

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Description

半導體封裝件及其製法
本發明係有關於一種半導體封裝件及其製法，尤指一種堆疊晶片型式之半導體封裝件及其製法。
隨著時代的進步，現今電子產品均朝向微型化、多功能、高電性及高速運作的方向發展，為了配合此一發展趨勢，半導體業者莫不積極研發體積微小、高性能、高功能、與高速度化的半導體封裝件，藉以符合電子產品之要求。
請參閱第5,202,754與5,270,261號美國專利，係揭露一種半導體封裝件及其製法，其主要係於一具有複數半導體晶片的晶圓中埋設有蝕刻停止層(etch stop layer)，並將該晶圓接合(bond)至一承載板上，接著，進行蝕刻步驟，使該晶圓的厚度減少至該蝕刻停止層處，並於該晶圓中形成有貫穿的矽穿孔(Through-Silicon Via，簡稱TSV)，且於該矽穿孔中形成有導電通孔，最後再將該晶圓從該承載板去除(debond)，而最終可得到厚度較薄的半導體晶片，則可使用該半導體晶片來堆疊完成一整體體積較小且高功能的3D-IC封裝件。
惟，前述習知專利在從該承載板上取下該半導體晶片時，容易使厚度較薄之半導體晶片毀損；又接合與去除之步驟容易使晶圓破裂或毀損；且習知之製法是以整片晶圓結合至承載板，而無法僅針對已知良好晶粒(known good die)，進而增加整體成本；此外，已薄化的半導體晶片容易有翹曲現象，而使後續的接合製程不易成功。
因此，如何避免上述習知技術中之種種問題，俾提供一種較佳之半導體封裝件及其製法，實已成為目前亟欲解決的課題。
有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件，係包括：線路增層，係具有複數外露於其頂面之電性連接墊；第一半導體晶片，係覆晶接置於該線路增層之頂面，且具有相對之第一作用面與第一非作用面，該第一作用面具有複數電性連接該電性連接墊的第一電極墊，於該第一非作用面之側形成有複數第一通孔，且於各該第一通孔中形成有電性連接該第一電極墊的第一凸塊；電子元件，係接置於該第一半導體晶片上，且電性連接該第一凸塊；以及封裝膠體，係形成於該線路增層之頂面上，且包覆該第一半導體晶片與電子元件。
本發明提供另一種半導體封裝件，係包括：承載板，係具有複數外露於其頂面之電性連接墊；第一半導體晶片，係覆晶接置於該承載板之頂面，且具有相對之第一作用面與第一非作用面，該第一作用面具有複數電性連接該電性連接墊的第一電極墊，於該第一非作用面之側形成有複數第一通孔，且於各該第一通孔中形成有電性連接該第一電極墊的第一凸塊，又於該第一半導體晶片之第一非作用面上形成有導熱層；電子元件，係接置於該第一半導體晶片上，且電性連接該第一凸塊；以及封裝膠體，係形成於該承載板之頂面上，且包覆該第一半導體晶片與電子元件，並外露該導熱層邊緣。
本發明復提供一種半導體封裝件之製法，係包括：提供一承載板，係具有相對之第一表面與第二表面，該第一表面上形成有線路增層，該線路增層係具有複數外露於該線路增層頂面之電性連接墊；於該線路增層上覆晶接置第一半導體晶片，該第一半導體晶片係具有相對之第一作用面與第一非作用面，該第一作用面具有複數電性連接該電性連接墊的第一電極墊；從該第一非作用面之側薄化該第一半導體晶片；於該第一非作用面之側形成複數第一通孔；於各該第一通孔中形成電性連接該第一電極墊的第一凸塊；於該第一半導體晶片上接置電子元件，該電子元件係具有相對之第二作用面與第二非作用面，該第二作用面具有複數電性連接該第一凸塊的第二電極墊；以及於該線路增層上形成包覆該第一半導體晶片與電子元件的封裝膠體。
本發明提供另一種半導體封裝件之製法，係包括：提供一承載板，係具有相對之第一表面與第二表面，該第一表面上形成有複數電性連接墊；於該第一表面上覆晶接置第一半導體晶片，該第一半導體晶片係具有相對之第一作用面與第一非作用面，該第一作用面具有複數電性連接該電性連接墊的第一電極墊；從該第一非作用面之側薄化該第一半導體晶片；於該第一非作用面之側形成複數第一通孔；於各該第一通孔中形成電性連接該第一電極墊的第一凸塊，並於該第一半導體晶片之第一非作用面上形成導熱層；於該第一半導體晶片上接置電子元件，該電子元件係具有相對之第二作用面與第二非作用面，該第二作用面具有複數電性連接該第一凸塊的第二電極墊；以及於該第一表面上形成包覆該第一半導體晶片與電子元件的封裝膠體。
本發明提供又一種半導體封裝件之製法，係包括：提供一承載板，係具有相對之第一表面與第二表面，該第一表面上形成有複數導電元件；於該第一表面上覆晶接置第一半導體晶片，該第一半導體晶片係具有相對之第一作用面與第一非作用面，該第一作用面具有複數電性連接該導電元件的第一電極墊；從該第一非作用面之側薄化該第一半導體晶片；於該第一非作用面之側形成複數第一通孔；於各該第一通孔中形成電性連接該第一電極墊的第一凸塊；於該第一半導體晶片上接置電子元件，該電子元件係電性連接該第一凸塊；以及於該第一表面上形成包覆該第一半導體晶片與電子元件的封裝膠體。
本發明再提供一種半導體封裝件之製法，係包括：提供一承載板，係具有相對之第一表面與第二表面，該第一表面上形成有線路增層，該線路增層係具有複數外露於該線路增層頂面之電性連接墊；於該線路增層上覆晶接置第一半導體晶片，該第一半導體晶片係具有相對之第一作用面與第一非作用面，該第一作用面具有複數電性連接該電性連接墊的第一電極墊，該第一半導體晶片中係具有電性連接該第一電極墊的第一凸塊；從該第一非作用面之側薄化該第一半導體晶片，以令該第一凸塊外露於該第一非作用面；於該第一半導體晶片上接置電子元件，該電子元件係電性連接該第一凸塊；以及於該線路增層上形成包覆該第一半導體晶片與電子元件的封裝膠體。
由上可知，因為本發明係直接在承載板上開始進行製程，且後續不包括去除晶圓之步驟，所以可避免良率的減低；又本發明可先在該承載板上進行電性測試，並僅在電性測試無誤之處接置良品晶片，因此能減少良率的損失；再者，半導體晶片是在接置在承載板上後才進行薄化步驟，而能避免薄化後之半導體晶片不易進行堆疊或接合步驟的缺點；況且，本發明最終可無須承載板，所以能有效減少封裝件的厚度；此外，本發明復可設置有導熱層與散熱罩，故可提供較佳的散熱效率。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「頂」、「底」、「側」、「外」、「U形」、「上」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第一實施例
請參閱第1-1至1-33圖，係本發明之半導體封裝件及其製法的第一實施例之剖視圖。
如第1-1圖所示，提供一承載板10，係具有相對之第一表面10a與第二表面10b，該第一表面10a上形成第一介電層11a，且該第一介電層11a具有外露部分該第一表面10a的第一介電層開孔110a；其中，該承載板10可為矽晶圓、鍍鋁晶圓或玻璃薄板，但不以此為限，若該承載板10表面具導電特性(如鍍鋁晶圓)，即可進行電性測試以得到其上之線路的良率，該第一介電層11a之材質可為BCB(Benzocyclo-buthene)、聚醯亞胺(polyimide)或PBO(polybenzoxazole)等之高分子絕緣材料，亦可為二氧化矽(SiO2)或氮化矽(Si3N4)等之絕緣材料。
如第1-2圖所示，於該第一表面10a與第一介電層11a上以濺鍍方式形成一第一導電層12a。
如第1-3圖所示，於該第一導電層12a上形成第一阻層13，且該第一阻層13具有外露部分該第一導電層12a的第一阻層開孔130。
如第1-4圖所示，於該第一導電層12a上形成第一線路層12b，該第一線路層12b之材質可為銅或鋁。
如第1-5圖所示，移除該第一阻層13及其所覆蓋之第一導電層12a，此時，該第一介電層11a、剩餘之第一導電層12a與第一線路層12b係構成一線路增層，惟該線路增層之型式不以圖示者為限。
如第1-6圖所示，於該第一介電層11a與第一線路層12b上形成第二介電層11b，且該第二介電層11b具有複數第二介電層開孔110b，以對應外露該第一線路層12b之電性連接墊131，該第二介電層11b之材質可為BCB(Benzocyclo-buthene)、聚醯亞胺(polyimide)或PBO(polybenzoxazole)等之高分子絕緣材料，亦可為二氧化矽(SiO2)或氮化矽(Si3N4)等之絕緣材料。
如第1-7圖所示，於該第二介電層11b與第一線路層12b上以濺鍍方式形成一第二導電層14。
如第1-8圖所示，於該第二導電層14上形成第二阻層15，且該第二阻層15具有外露部分該第二導電層14的第二阻層開孔150。
如第1-9圖所示，於該第二導電層14上形成材質例如為錫銀的第一銲料16。
如第1-10圖所示，移除該第二阻層15及其所覆蓋之第二導電層14。
如第1-11圖所示，進行廻銲步驟。
如第1-12圖所示，提供一例如為第一半導體晶片17的電子元件，該第一半導體晶片17係具有相對之第一作用面17a與第一非作用面17b，該第一作用面17a具有複數第一電極墊171，且該第一電極墊171上形成有銅柱172與其上的第三銲料173。或者，如第1-12’圖所示，該第一電極墊171上僅形成有第三銲料173，而無銅柱172，惟以下僅以第1-12圖為代表來例示說明。
要注意的是，前述第1-7至1-12圖之步驟亦可簡化為化鎳鈀浸金(Electroless-Nickel-Electroless-Palladium-Immersion-Gold，簡稱ENEPIG)之製程或類似製程，以方便後續與半導體晶片之銲料對接；例如，如第1-7’至1-8’圖所示，於該第二介電層開孔110b中形成化鎳鈀浸金層161，並省去第1-11圖之廻銲步驟，且使該電性連接墊131藉由化鎳鈀浸金層161電性連接後續覆晶之第一半導體晶片17的第一電極墊171；或者，將第1-9圖之步驟改為化鎳鈀浸金(ENEPIG)之製程或類似製程，以增加後續與半導體晶片之銲料對接之面積，並可省去第1-11圖之廻銲步驟，惟此係本發明所屬技術領域之通常知識者依據本說明書所能瞭解，故不在此加以贅述與圖示。
如第1-13圖所示，於該第一銲料16上覆晶接置該第一半導體晶片17，且於該第一半導體晶片17與第二介電層11b之間形成第一底充材料18a。
如第1-14圖所示，於該第二介電層11b上形成包覆該第一半導體晶片17與第一底充材料18a的第一封裝膠體19a。
如第1-15圖所示，以例如研磨之方式從該第一非作用面17b之側移除部分第一封裝膠體19a，並薄化該第一半導體晶片17。
如第1-16圖所示，於該第一半導體晶片17與第一封裝膠體19a上形成第三阻層20，且該第三阻層20具有複數外露該第一非作用面17b之第三阻層開孔200，各該第三阻層開孔200分別對應各該第一電極墊171。
如第1-17圖所示，移除該第三阻層開孔200中之部分第一半導體晶片17，以定義出複數外露該第一電極墊171的第一通孔170，並移除該第三阻層20。於其他實施例中，該第一通孔170亦可外露與該第一電極墊171電性連接之任一第三線路層174，如第1-17’圖所示。
如第1-18圖所示，於該第一非作用面17b、第一封裝膠體19a與第一電極墊171上形成第一絕緣層21，形成該第一絕緣層21之方式可為電漿增強式化學氣相沉積(PECVD)，且該第一絕緣層21之材質可為Si3N4或SiO2。
如第1-19圖所示，於該第一絕緣層21上形成第四阻層22，且該第四阻層22具有複數第四阻層開孔220，以對應外露該第一封裝膠體19a與部分該第一電極墊171上的第一絕緣層21。
如第1-20圖所示，藉由乾蝕刻移除未被該第四阻層22所覆蓋的第一絕緣層21，接著移除該第四阻層22，此時，各該第一通孔170之內表面形成有外露該第一電極墊171的第一絕緣層21。
要補充說明的是，於前述第1-18至1-20圖之步驟中，該第一絕緣層21之材質亦可改用感光型之BCB (Benzocyclo-buthene)、聚醯亞胺(polyimide)或PBO(polybenzoxazole)等材料並進行塗佈、曝光與顯影，以降低成本並使該第一絕緣層21具有彈性，進而吸收該第一半導體晶片17之第一通孔170中之導體的熱膨脹應力。
如第1-21圖所示，於該第一絕緣層21、第一封裝膠體19a與部分該第一電極墊171上形成作為阻障層及凸塊底下金屬層的第三導電層23。
如第1-22圖所示，於該第三導電層23上形成第五阻層24，且該第五阻層24具有複數對應該第一通孔170的第五阻層開孔240。
如第1-23圖所示，於各該第五阻層開孔240中形成第一凸塊25a，且該第一凸塊25a電性連接該第一電極墊171，形成該第一凸塊25a之方式可為電鍍、化鎳鈀浸金層製程或印刷錫膏，且該第一凸塊25a之材質可為鎳、錫、銀、銅、鈀、金、鋁之其中一者或其組合。
如第1-24圖所示，移除該第五阻層24及其所覆蓋的第三導電層23，並進行廻銲步驟。
如第1-25圖所示，提供一例如為第二半導體晶片26的電子元件，該第二半導體晶片26係具有相對之第二作用面26a與第二非作用面26b，該第二作用面26a具有複數第二電極墊261，且該第二電極墊261上形成有銅柱262與其上的第三銲料263。
要注意的是，前述第1-21至1-25圖之步驟亦可簡化為化鎳鈀浸金(Electroless-Nickel-Electroless-Palladium-Immersion-Gold，簡稱ENEPIG)之製程或類似製程，以方便後續與半導體晶片之銲料對接；例如，如第1-21’至1-22’圖所示，於該第一電極墊171上形成化鎳鈀浸金層175，並省去第1-24圖之廻銲步驟，且使該第一電極墊171藉由化鎳鈀浸金層175電性連接後續覆晶之第二半導體晶片26的第二電極墊261；或者，將第1-23圖之步驟改為化鎳鈀浸金(ENEPIG)之製程或類似製程，以增加後續與半導體晶片之銲料對接之面積，並可省去第1-24圖之廻銲步驟，惟此係本發明所屬技術領域之通常知識者依據本說明書所能瞭解，故不在此加以贅述與圖示。
如第1-26圖所示，將該第二半導體晶片26覆晶接置於該第一半導體晶片17之第一凸塊25a上，並重複前述第1-13至1-24圖之步驟，以形成第二底充材料18b、第二封裝膠體19b與第二凸塊25b等。
如第1-27圖所示，提供一例如為第三半導體晶片27的電子元件，該第三半導體晶片27係具有相對之第三作用面27a與第三非作用面27b，該第三作用面27a具有複數第三電極墊271，且該第三電極墊271上形成有銅柱272與其上的第三銲料273；要補充說明的是，於其他實施例中，該電子元件亦可為被動元件或封裝件。
如第1-28圖所示，將該第三半導體晶片27覆晶接置於該第二半導體晶片26之第二凸塊25b上，並重複前述第1-13至1-14圖之步驟，以形成第三底充材料18c與第三封裝膠體19c等。
如第1-29圖所示，從該第三半導體晶片27之側研磨移除部分該第三封裝膠體19c；於其他實施例中，亦可研磨至該第三半導體晶片27之第三非作用面27b外露，以增加散熱效果。
如第1-30圖所示，研磨移除部分該承載板10，若該該承載板10為矽晶圓，則可用乾蝕刻及化學機械研磨(CMP)之方式去除之。
如第1-31圖所示，藉由乾蝕刻或化學機械研磨(CMP)來完全移除該承載板10，以外露部分該第一導電層12a做為銲墊121。
如第1-32圖所示，於該銲墊121上設置銲球28；或者，亦可於該銲墊121形成多層之線路增層，再設置銲球28，如第1-32’圖所示，惟詳細之實施內容係本發明所屬技術領域之通常知識者依據本說明書所能瞭解，故不在此加以贅述。
如第1-33圖所示，進行切單(singulation)製程。
要補充說明的是，於第1-11、1-13、1-14、1-15、1-24或1-26圖之步驟後，可薄化該承載板10或於該承載板10之底面上塗佈一層BCB(Benzocyclo-buthene)、聚醯亞胺(polyimide)或PBO(polybenzoxazole)等之高分子絕緣材料、或者二氧化矽(SiO2)或氮化矽(Si3N4)等之絕緣材料，藉以調整該承載板10之表面應力，進而降低整體之翹曲。
第二實施例
請參閱第2-1至2-3圖，係本發明之半導體封裝件及其製法的第二實施例之剖視圖。
如第2-1圖所示，係接續自第1-21圖，於該第三導電層23上形成第五阻層24，且該第五阻層24具有複數對應該第一通孔170及部分第一非作用面17b的第五阻層開孔240，並於各該第五阻層開孔240中形成第一凸塊25a與電性連接該第一凸塊25a的第二線路層29。
如第2-2圖所示，移除該第五阻層24及其所覆蓋的第三導電層23。
如第2-3圖所示，於該第一絕緣層21、第一封裝膠體19a與第二線路層29上形成第三介電層30，該第三介電層30具有複數外露部分該第二線路層29的第三介電層開孔300，並於該第三介電層開孔300中形成凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)與第二銲料31。接著，可依循前一實施例之方式來進行堆疊半導體晶片、被動元件或封裝件等封裝步驟，故不在此加以贅述。
第三實施例
請參閱第3-1至3-10圖，係本發明之半導體封裝件及其製法的第三實施例之剖視圖。
如第3-1圖所示，係接續自第1-21圖，於該第三導電層23上形成第五阻層24，且該第五阻層24具有複數對應該第一通孔170、外露部分該第一非作用面17b與部分該第一封裝膠體19a的第五阻層開孔240。
如第3-2圖所示，於該第五阻層開孔240中各自形成材質例如為銅的第一凸塊25a與導熱層32，該第一凸塊25a係位於該第一通孔170中，該導熱層32係位於該第一非作用面17b與第一封裝膠體19a上。
如第3-3圖所示，移除該第五阻層24。
如第3-4圖所示，形成覆蓋該導熱層32的第六阻層33，且該第六阻層33具有外露該第一凸塊25a的第六阻層開孔330。
如第3-5圖所示，於該第六阻層開孔330中形成第三凸塊34與第二銲料31，該第三凸塊34之材質係為銅或鎳，該第二銲料31之材質係為錫銀。
如第3-6圖所示，移除該第六阻層33及其所覆蓋的第三導電層23。
如第3-7圖所示，於該第一絕緣層21、第一封裝膠體19a與導熱層32上形成第三介電層30，該第三介電層30具有複數外露該第三凸塊34、第二銲料31及部分第一封裝膠體19a的第三介電層開孔300。
如第3-8圖所示，進行廻銲步驟。
如第3-9圖所示，提供一第二半導體晶片26，該第二半導體晶片26係具有相對之第二作用面26a與第二非作用面26b，該第二作用面26a具有複數第二電極墊261。
如第3-10圖所示，將該第二半導體晶片26覆晶接置於該第三凸塊34上，並依據第一實施例之概念進行封裝與切單步驟，以形成第二底充材料18b、第二封裝膠體19b與銲球28等，且該導熱層32邊緣外露於封裝件之外；其中，該第二底充材料18b係填入該第三介電層開孔300中，以增加該第二底充材料18b與第一封裝膠體19a的接觸面積，而可避免脫層。
第四實施例
請參閱第4圖，係本發明之半導體封裝件的第四實施例之剖視圖。
本實施例大致相同於前一實施例，其主要不同點在於本實施例復於該第一封裝膠體19a、第二封裝膠體19b與第二非作用面26b外依序形成散熱膠35與設置一U形之散熱罩36。
要注意的是，該散熱罩36係可透過散熱膠35連接該導熱層32，且部分該第三凸塊34係可用來接地，而連接該導熱層32，如第4’圖所示。
第五實施例
請參閱第5-1至5-5圖，係本發明之半導體封裝件及其製法的第五實施例之剖視圖。
本實施例大致相同於第一實施例，其主要不同點在於本實施例之承載板係採用內部與表面具有線路的電路板或封裝基板，且最終並不移除該承載板，至於其他具體內容可參照第一實施例，故不在此加以贅述。
如第5-1圖所示，提供一承載板10與第一半導體晶片17，該承載板10係為內部與表面具有線路的電路板或封裝基板。
如第5-2圖所示，將該第一半導體晶片17覆晶接置於該承載板10上，於該第一半導體晶片17與承載板10之間形成第一底充材料18a，再於該承載板10上形成包覆該第一半導體晶片17與第一底充材料18a的第一封裝膠體19a，且進行研磨步驟。
如第5-3圖所示，於該第一半導體晶片17與第一封裝膠體19a上形成導熱層32與第三凸塊34。
如第5-4圖所示，於該第三凸塊34上覆晶接置第二半導體晶片26，並形成第二底充材料18b與第二封裝膠體19b。
如第5-5圖所示，進行研磨步驟，並設置銲球28，且進行切單步驟。
第六實施例
請參閱第6-1至6-6圖，係本發明之半導體封裝件及其製法的第六實施例之剖視圖，其中，第6-6’圖係第6-6圖之另一實施態樣。
本實施例大致相同於第一實施例，其主要不同點在於本實施例係未先形成有該線路增層，而直接於該承載板10上形成第一導電層12a與例如為第一銲料16或化鎳鈀浸金層的導電元件，接著，進行如第1-12至1-31圖所示的步驟，並於外露之該第一導電層12a上形成銲球28，而成為第6-6圖之結構；或者，於外露之該第一導電層12a上形成線路增層後，再形成銲球28，而成為第6-6’圖之結構。至於本實施例之其他具體實施內容可參照第一實施例，故不在此加以贅述。
第七實施例
請參閱第7-1至7-5圖，係本發明之半導體封裝件及其製法的第七實施例之剖視圖。
本實施例係延續自第1-11圖且大致相同於第一實施例，其主要不同點在於本實施例之第一半導體晶片17中係具有材質例如為銅的第一凸塊25a，且後續從該第一非作用面17b進行薄化製程以外露該第一凸塊25a，並於該第一非作用面17b與第一封裝膠體19a上形成外露該第一凸塊25a之第四介電層37，再藉由該第一凸塊25a電性連接後續堆疊之半導體晶片，本實施例之後續其他具體實施內容可參照第一實施例，故不在此加以圖示與贅述。
要注意的是，於第七實施例中，進行薄化製程時可僅薄化該第一半導體晶片17，使該第一凸塊25a突出於該第一非作用面17b，再於該第一非作用面17b、第一封裝膠體19a與第一凸塊25a上塗佈第四介電層37，並進行研磨製程，以移除部分該第一凸塊25a與第四介電層37，並外露該第一凸塊25a之頂端，以供後續電性連接半導體晶片之用，如第8-1至8-3圖所示。
此外，第七實施例之具有第一凸塊25a的第一半導體晶片17同樣可應用於第二實施例至第六實施例中，惟詳細之實施內容係本發明所屬技術領域之通常知識者依據本說明書所能瞭解，故不在此加以贅述。
要補充說明的是，本發明所述之半導體晶片可藉由銲錫、不導電膠(NCP)、異向性導電膜(ACF)或異方性導電膠(ACP)等以電性連接其他半導體晶片或電子元件；且於其他實施例中，可僅使用底充材料或封裝膠體來包覆各半導體晶片或電子元件；又本發明之半導體晶片亦可用層疊之半導體晶片來取代；再者，本發明之導電層的材質可為Ti、Cu、Ni、V、Al、W、Au、或其組合，但不侷限於上述之材質；而且，本發明所述之製程中，電鍍錫銀亦可含銅/鎳/鍺等。
本發明復提供一種半導體封裝件，係包括：線路增層，係具有複數外露於其頂面之電性連接墊131；第一半導體晶片17，係覆晶接置於該線路增層之頂面，且具有相對之第一作用面17a與第一非作用面17b，該第一作用面17a具有複數電性連接該電性連接墊131的第一電極墊171，於該第一非作用面17b之側形成有複數外露該第一電極墊171的第一通孔170，且於各該第一通孔170中形成有電性連接該第一電極墊171的第一凸塊25a；電子元件，係接置於該第一半導體晶片17上，且電性連接該第一凸塊25a；以及封裝膠體，係形成於該線路增層之頂面上，且包覆該第一半導體晶片17與電子元件。
本發明復提供另一種半導體封裝件，係包括：承載板10，係具有複數外露於其頂面之電性連接墊131；第一半導體晶片17，係覆晶接置於該承載板10之頂面，且具有相對之第一作用面17a與第一非作用面17b，該第一作用面17a具有複數電性連接該電性連接墊131的第一電極墊171，於該第一非作用面17b之側形成有複數第一通孔170，且於各該第一通孔170中形成有電性連接該第一電極墊171的第一凸塊25a，又於該第一半導體晶片17之第一非作用面17b上形成有導熱層32；電子元件，係接置於該第一半導體晶片17上，且電性連接該第一凸塊25a；以及封裝膠體，係形成於該承載板10之頂面上，且包覆該第一半導體晶片17與電子元件。
前述之半導體封裝件中，該第一通孔170係外露該第一電極墊171，該第一通孔170係外露與該第一電極墊171電性連接之任一線路層，且該第一凸塊25a之材質係鎳、錫、銀、銅、鈀、金、鋁之其中一者或其組合。
於本發明之半導體封裝件中，該線路增層係具有複數外露於底面的銲墊121，且若無線路增層，則該承載板10係為電路板或封裝基板。
所述之半導體封裝件中，該電子元件係為半導體晶片、被動元件或封裝件，該電性連接墊131之頂面復包括第二導電層14與其上的第一銲料16，該第一半導體晶片17與線路增層之間復形成有第一底充材料(underfill)18a，且該第一半導體晶片17與第二半導體晶片26之間復形成有第二底充材料18b。
又於前述之半導體封裝件中，該封裝膠體係包括包覆該第一半導體晶片17的第一封裝膠體19a與包覆該第二半導體晶片26的第二封裝膠體19b。
依上所述之半導體封裝件，該第一半導體晶片17與電子元件之間復設置有第二半導體晶片26，於該第一半導體晶片17之第一非作用面17b上復可形成有電性連接該第一凸塊25a的第二線路層29，且復可包括設於該封裝膠體外的散熱罩36。
又於本發明之半導體封裝件中，該散熱罩36與封裝膠體之間復形成有散熱膠35，且該散熱罩36之外形係呈U形。
又於所述之半導體封裝件中，於該第一半導體晶片17之第一非作用面17b上復形成有導熱層32，並復包括設於該封裝膠體外的散熱罩36，且該散熱罩36連接該導熱層32。
綜上所述，相較於習知技術，由於本發明係直接在承載板上開始進行製程，且後續並不使用去結合(debond)之步驟，所以可避免良率的減低；又本發明可先在該承載板上進行電性測試，並僅在電性測試無誤之處接置良品晶片，因此能減少良率的損失；再者，半導體晶片是在接置在承載板上後才進行薄化步驟，而能避免薄化後之半導體晶片不易進行堆疊或接合步驟的缺點；況且，本發明最終可無須承載板，所以能有效減少封裝件的厚度；此外，本發明復可設置有導熱層與散熱罩，故可提供較佳的散熱效率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10．．．承載板
10a．．．第一表面
10b．．．第二表面
11a．．．第一介電層
110a．．．第一介電層開孔
11b．．．第二介電層
110b．．．第二介電層開孔
12a．．．第一導電層
12b．．．第一線路層
121．．．銲墊
13．．．第一阻層
130．．．第一阻層開孔
131．．．電性連接墊
14．．．第二導電層
15．．．第二阻層
150．．．第二阻層開孔
16．．．第一銲料
161,175．．．化鎳鈀浸金層
17．．．第一半導體晶片
17a．．．第一作用面
17b．．．第一非作用面
170．．．第一通孔
171．．．第一電極墊
172,262,272．．．銅柱
173,263,273．．．第三銲料
174．．．第三線路層
18a．．．第一底充材料
18b．．．第二底充材料
18c．．．第三底充材料
19a．．．第一封裝膠體
19b．．．第二封裝膠體
19c．．．第三封裝膠體
20．．．第三阻層
200．．．第三阻層開孔
21．．．第一絕緣層
22．．．第四阻層
220．．．第四阻層開孔
23．．．第三導電層
24．．．第五阻層
240．．．第五阻層開孔
25a．．．第一凸塊
25b．．．第二凸塊
26．．．第二半導體晶片
26a．．．第二作用面
26b．．．第二非作用面
261．．．第二電極墊
27．．．第三半導體晶片
27a．．．第三作用面
27b．．．第三非作用面
271．．．第三電極墊
28．．．銲球
29．．．第二線路層
30．．．第三介電層
300．．．第三介電層開孔
31．．．第二銲料
32．．．導熱層
33．．．第六阻層
330．．．第六阻層開孔
34．．．第三凸塊
35．．．散熱膠
36．．．散熱罩
37．．．第四介電層
第1-1至1-33圖係本發明之半導體封裝件及其製法的第一實施例之剖視圖，其中，第1-7’至1-8’圖係為第1-7至1-12圖之另一實施方法，第1-12’與1-17’圖分別為第1-12與1-17圖之另一實施態樣，第1-21’至1-22’圖係為第1-21至1-25圖之另一實施方法，第1-32’圖係第1-32圖之另一實施態樣；
第2-1至2-3圖係本發明之半導體封裝件及其製法的第二實施例之剖視圖；
第3-1至3-10圖係本發明之半導體封裝件及其製法的第三實施例之剖視圖；
第4圖係本發明之半導體封裝件的第四實施例之剖視圖，其中，第4’圖係第4圖之另一實施態樣；
第5-1至5-5圖係本發明之半導體封裝件及其製法的第五實施例之剖視圖；
第6-1至6-6圖係本發明之半導體封裝件及其製法的第六實施例之剖視圖，其中，第6-6’圖係第6-6圖之另一實施態樣；以及
第7-1至7-5圖與第8-1至8-3圖係本發明之半導體封裝件及其製法的第七實施例之剖視圖，其中，第8-1至8-3圖係第7-4至7-5圖之另一實施方法。
10．．．承載板
11a．．．第一介電層
11b．．．第二介電層
12a．．．第一導電層
12b．．．第一線路層
121．．．銲墊
131．．．電性連接墊
14．．．第二導電層
16．．．第一銲料
17．．．第一半導體晶片
17a．．．第一作用面
17b．．．第一非作用面
171．．．第一電極墊
18a．．．第一底充材料
18b．．．第二底充材料
18c．．．第三底充材料
19a．．．第一封裝膠體
19b．．．第二封裝膠體
19c．．．第三封裝膠體
21．．．第一絕緣層
23．．．第三導電層
25a．．．第一凸塊
25b．．．第二凸塊
26．．．第二半導體晶片
261．．．第二電極墊
27．．．第三半導體晶片

Claims (36)

  1. 一種半導體封裝件，係包括：線路增層，係具有複數外露於其頂面之電性連接墊；第一半導體晶片，係覆晶接置於該線路增層之頂面，且具有相對之第一作用面與第一非作用面，該第一作用面具有複數電性連接該電性連接墊的第一電極墊，於該第一非作用面之側形成有複數第一通孔，且於各該第一通孔中形成有電性連接該第一電極墊的第一凸塊；電子元件，係接置於該第一半導體晶片上，且該電子元件藉由銲料結合該第一凸塊以電性連接該第一凸塊；以及封裝膠體，係形成於該線路增層之頂面上，且包覆該第一半導體晶片與電子元件。
  2. 一種半導體封裝件，係包括：承載板，係具有複數外露於其頂面之電性連接墊；第一半導體晶片，係覆晶接置於該承載板之頂面，且具有相對之第一作用面與第一非作用面，該第一作用面具有複數電性連接該電性連接墊的第一電極墊，於該第一非作用面之側形成有複數第一通孔，且於各該第一通孔中形成有電性連接該第一電極墊的第一凸塊，又於該第一半導體晶片之第一非作用面上形成有導熱層； 電子元件，係接置於該第一半導體晶片上，且該電子元件藉由銲料結合該第一凸塊以電性連接該第一凸塊；以及封裝膠體，係形成於該承載板之頂面上，且包覆該第一半導體晶片與電子元件，並外露該導熱層邊緣。
  3. 如申請專利範圍第1或2項所述之半導體封裝件，其中，該第一通孔係外露該第一電極墊。
  4. 如申請專利範圍第1或2項所述之半導體封裝件，其中，該第一通孔係外露與該第一電極墊電性連接之任一線路層。
  5. 如申請專利範圍第1或2項所述之半導體封裝件，其中，該第一凸塊之材質係鎳、錫、銀、銅、鈀、金、鋁之其中一者或其組合。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，該線路增層係具有複數外露於其底面的銲墊。
  7. 如申請專利範圍第1或2項所述之半導體封裝件，其中，該電子元件係為半導體晶片、被動元件或封裝件。
  8. 如申請專利範圍第2項所述之半導體封裝件，其中，該承載板係為電路板或封裝基板。
  9. 如申請專利範圍第1項所述之半導體封裝件，其中，該電性連接墊之頂面復包括導電層與其上的第一銲料。
  10. 如申請專利範圍第1或2項所述之半導體封裝件，其中，該封裝膠體係包括包覆該第一半導體晶片的第一 封裝膠體與包覆該電子元件的第二封裝膠體。
  11. 如申請專利範圍第1或2項所述之半導體封裝件，其中，該第一半導體晶片與電子元件之間復設置有第二半導體晶片。
  12. 如申請專利範圍第1或2項所述之半導體封裝件，其中，於該第一半導體晶片之第一非作用面上復形成有電性連接該第一凸塊的線路層。
  13. 如申請專利範圍第1或2項所述之半導體封裝件，復包括散熱罩，係設於該封裝膠體外。
  14. 如申請專利範圍第13項所述之半導體封裝件，其中，該散熱罩與封裝膠體之間復形成有散熱膠。
  15. 如申請專利範圍第1項所述之半導體封裝件，其中，於該第一半導體晶片之第一非作用面上復形成有導熱層。
  16. 如申請專利範圍第2或15項所述之半導體封裝件，復包括散熱罩，係設於該封裝膠體外，且該散熱罩連接該導熱層。
  17. 一種半導體封裝件之製法，係包括：提供一承載板，係具有相對之第一表面與第二表面，該第一表面上形成有線路增層，該線路增層係具有複數外露於該線路增層頂面之電性連接墊；於該線路增層上覆晶接置第一半導體晶片，該第一半導體晶片係具有相對之第一作用面與第一非作用面，該第一作用面具有複數電性連接該電性連接墊的 第一電極墊；從該第一非作用面之側薄化該第一半導體晶片；於該第一非作用面之側形成複數第一通孔；於各該第一通孔中形成電性連接該第一電極墊的第一凸塊；於該第一半導體晶片上接置電子元件，該電子元件係藉由銲料結合該第一凸塊以電性連接該第一凸塊；以及於該線路增層上形成包覆該第一半導體晶片與電子元件的封裝膠體。
  18. 一種半導體封裝件之製法，係包括：提供一承載板，係具有相對之第一表面與第二表面，該第一表面上形成有複數電性連接墊；於該第一表面上覆晶接置第一半導體晶片，該第一半導體晶片係具有相對之第一作用面與第一非作用面，該第一作用面具有複數電性連接該電性連接墊的第一電極墊；從該第一非作用面之側薄化該第一半導體晶片；於該第一非作用面之側形成複數第一通孔；於各該第一通孔中形成電性連接該第一電極墊的第一凸塊，並於該第一半導體晶片之第一非作用面上形成導熱層；於該第一半導體晶片上接置電子元件，該電子元件係藉由銲料結合該第一凸塊以電性連接該第一凸 塊；以及於該第一表面上形成包覆該第一半導體晶片與電子元件的封裝膠體。
  19. 一種半導體封裝件之製法，係包括：提供一承載板，係具有相對之第一表面與第二表面，該第一表面上形成有複數導電元件；於該第一表面上覆晶接置第一半導體晶片，該第一半導體晶片係具有相對之第一作用面與第一非作用面，該第一作用面具有複數電性連接該導電元件的第一電極墊；從該第一非作用面之側薄化該第一半導體晶片；於該第一非作用面之側形成複數第一通孔；於各該第一通孔中形成電性連接該第一電極墊的第一凸塊；於該第一半導體晶片上接置電子元件，該電子元件係藉由銲料結合該第一凸塊以電性連接該第一凸塊；以及於該第一表面上形成包覆該第一半導體晶片與電子元件的封裝膠體。
  20. 一種半導體封裝件之製法，係包括：提供一承載板，係具有相對之第一表面與第二表面，該第一表面上形成有線路增層，該線路增層係具有複數外露於該線路增層頂面之電性連接墊；於該線路增層上覆晶接置第一半導體晶片，該第 一半導體晶片係具有相對之第一作用面與第一非作用面，該第一作用面具有複數電性連接該電性連接墊的第一電極墊，該第一半導體晶片中係具有電性連接該第一電極墊的第一凸塊；從該第一非作用面之側薄化該第一半導體晶片，以令該第一凸塊外露於該第一非作用面；於該第一半導體晶片上接置電子元件，該電子元件係藉由銲料結合該第一凸塊以電性連接該第一凸塊；以及於該線路增層上形成包覆該第一半導體晶片與電子元件的封裝膠體。
  21. 如申請專利範圍第17、18或19項所述之半導體封裝件之製法，其中，該第一通孔係外露該第一電極墊。
  22. 如申請專利範圍第17、18或19項所述之半導體封裝件之製法，其中，該第一通孔係外露與該第一電極墊電性連接之任一線路層。
  23. 如申請專利範圍第17、18或19項所述之半導體封裝件之製法，其中，該第一凸塊係以電鍍、化鎳鈀浸金層製程或印刷錫膏並廻銲形成。
  24. 如申請專利範圍第17或20項所述之半導體封裝件之製法，其中，該線路增層係具有複數接觸該承載板之第一表面的銲墊，且該製法復包括移除該承載板，以外露該等銲墊。
  25. 如申請專利範圍第17、18、19或20項所述之半導體 封裝件之製法，其中，該電子元件係為半導體晶片、被動元件或封裝件。
  26. 如申請專利範圍第17、19或20項所述之半導體封裝件之製法，其中，該承載板係為矽晶圓、鍍鋁晶圓或玻璃薄板。
  27. 如申請專利範圍第18項所述之半導體封裝件之製法，其中，該承載板係為電路板或封裝基板。
  28. 如申請專利範圍第17或20項所述之半導體封裝件之製法，其中，該電性連接墊之頂面復包括第一銲料或化鎳鈀浸金層。
  29. 如申請專利範圍第17、18、19或20項所述之半導體封裝件之製法，其中，該封裝膠體係包括包覆該第一半導體晶片的第一封裝膠體與包覆該電子元件的第二封裝膠體。
  30. 如申請專利範圍第17、18、19或20項所述之半導體封裝件之製法，其中，該第一半導體晶片與電子元件之間復設置有第二半導體晶片。
  31. 如申請專利範圍第17、18、19或20項所述之半導體封裝件之製法，其中，復包括於該第一半導體晶片之第一非作用面上形成電性連接該第一凸塊的線路層。
  32. 如申請專利範圍第17、18、19或20項所述之半導體封裝件之製法，復包括於該封裝膠體外設置散熱罩。
  33. 如申請專利範圍第32項所述之半導體封裝件之製法，其中，該散熱罩與封裝膠體之間復形成有散熱膠。
  34. 如申請專利範圍第17、19或20項所述之半導體封裝件之製法，其中，復包括於該第一半導體晶片之第一非作用面上形成導熱層。
  35. 如申請專利範圍第18項所述之半導體封裝件之製法，復包括於該封裝膠體外設置散熱罩，且該散熱罩連接該導熱層。
  36. 如申請專利範圍第19項所述之半導體封裝件之製法，其中，該導電元件係為銲料或化鎳鈀浸金層。
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CN201210585201.3A CN103390600B (zh) 2012-05-11 2012-12-28 半导体封装件及其制法
US15/975,232 US10622323B2 (en) 2012-05-11 2018-05-09 Fabrication method of semiconductor package with stacked semiconductor chips
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI692281B (zh) * 2019-03-13 2020-04-21 中華精測科技股份有限公司 多層電路板及其製造方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI527170B (zh) * 2012-05-11 2016-03-21 矽品精密工業股份有限公司 半導體封裝件及其製法
KR101970291B1 (ko) * 2012-08-03 2019-04-18 삼성전자주식회사 반도체 패키지의 제조 방법
US8963336B2 (en) 2012-08-03 2015-02-24 Samsung Electronics Co., Ltd. Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
US9698079B2 (en) * 2014-01-03 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier structures between external electrical connectors
CN104766844B (zh) * 2014-01-07 2017-12-19 日月光半导体制造股份有限公司 半导体结构及其制造方法
TWI555167B (zh) * 2014-01-29 2016-10-21 矽品精密工業股份有限公司 半導體封裝件及其製法
TWI557865B (zh) * 2014-01-29 2016-11-11 矽品精密工業股份有限公司 堆疊組及其製法與基板結構
TWI654723B (zh) * 2015-02-06 2019-03-21 矽品精密工業股份有限公司 封裝結構之製法
US9576918B2 (en) * 2015-05-20 2017-02-21 Intel IP Corporation Conductive paths through dielectric with a high aspect ratio for semiconductor devices
TWI550814B (zh) * 2015-07-31 2016-09-21 矽品精密工業股份有限公司 承載體、封裝基板、電子封裝件及其製法
US10535585B2 (en) * 2017-08-23 2020-01-14 Semiconductor Components Industries, Llc Integrated passive device and fabrication method using a last through-substrate via
US11152274B2 (en) * 2017-09-11 2021-10-19 Advanced Semiconductor Engineering, Inc. Multi-moldings fan-out package and process
JP2020038943A (ja) * 2018-09-05 2020-03-12 株式会社東芝 半導体装置および半導体装置の製造方法
KR20210050951A (ko) * 2019-10-29 2021-05-10 삼성전자주식회사 반도체 패키지 및 그 제조 방법
TWI732538B (zh) * 2020-04-24 2021-07-01 矽品精密工業股份有限公司 電子封裝件
US11930590B2 (en) * 2020-12-31 2024-03-12 Texas Instruments Incorporated Stress relief for flip-chip packaged devices
CN112968007B (zh) * 2021-02-03 2023-03-24 重庆大学 功率半导体结构及断路器转移支路组件
US11488883B1 (en) * 2021-04-13 2022-11-01 Western Digital Technologies, Inc. Semiconductor device package having thermally conductive layers for heat dissipation

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5270261A (en) 1991-09-13 1993-12-14 International Business Machines Corporation Three dimensional multichip package methods of fabrication
US5202754A (en) 1991-09-13 1993-04-13 International Business Machines Corporation Three-dimensional multichip packages and methods of fabrication
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US6599775B2 (en) * 2001-05-18 2003-07-29 Advanpack Solutions Pte Ltd Method for forming a flip chip semiconductor package, a semiconductor package formed thereby, and a substrate therefor
US20030006062A1 (en) * 2001-07-06 2003-01-09 Stone William M. Interconnect system and method of fabrication
KR100537892B1 (ko) * 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
JP4441328B2 (ja) * 2004-05-25 2010-03-31 株式会社ルネサステクノロジ 半導体装置及びその製造方法
TWI249232B (en) * 2004-10-20 2006-02-11 Siliconware Precision Industries Co Ltd Heat dissipating package structure and method for fabricating the same
US7928590B2 (en) * 2006-08-15 2011-04-19 Qimonda Ag Integrated circuit package with a heat dissipation device
TWI331371B (en) * 2007-04-19 2010-10-01 Siliconware Precision Industries Co Ltd Semiconductor device and manufacturing method thereof
US8263437B2 (en) * 2008-09-05 2012-09-11 STATS ChiPAC, Ltd. Semiconductor device and method of forming an IPD over a high-resistivity encapsulant separated from other IPDS and baseband circuit
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US8176628B1 (en) * 2008-12-23 2012-05-15 Amkor Technology, Inc. Protruding post substrate package structure and method
US8338945B2 (en) * 2010-10-26 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Molded chip interposer structure and methods
US8664760B2 (en) * 2011-05-30 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Connector design for packaging integrated circuits
JP5357241B2 (ja) * 2011-08-10 2013-12-04 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
US20130249101A1 (en) * 2012-03-23 2013-09-26 Stats Chippac, Ltd. Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units
TWI527170B (zh) * 2012-05-11 2016-03-21 矽品精密工業股份有限公司 半導體封裝件及其製法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI692281B (zh) * 2019-03-13 2020-04-21 中華精測科技股份有限公司 多層電路板及其製造方法

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