TWI730629B - 封裝結構及其形成方法 - Google Patents

封裝結構及其形成方法 Download PDF

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TWI730629B
TWI730629B TW109104943A TW109104943A TWI730629B TW I730629 B TWI730629 B TW I730629B TW 109104943 A TW109104943 A TW 109104943A TW 109104943 A TW109104943 A TW 109104943A TW I730629 B TWI730629 B TW I730629B
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semiconductor die
conductive
interposer substrate
redistribution structure
forming
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TW109104943A
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TW202036739A (zh
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蔡柏豪
林孟良
莊博堯
翁得期
鄭心圃
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台灣積體電路製造股份有限公司
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01—ELECTRIC ELEMENTS
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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

本揭露一些實施例提供一種封裝結構及一種形成封裝結構的方法。所述方法包括在承載基板之上形成重分佈結構以及將半導體晶粒放置在重分佈結構之上。所述方法還包括將中介層基板堆疊在重分佈結構之上。中介層基板延伸跨越半導體晶粒的邊緣。所述方法更包括將一或多個裝置元件放置在中介層基板之上。此外，所述方法還包括形成包圍半導體晶粒的保護層。

Description

封裝結構及其形成方法
本揭露一些實施例係有關於半導體晶粒封裝技術，特別係有關於半導體晶粒封裝結構及其形成方法。
半導體積體電路(integrated circuit，IC)產業已經歷了快速的成長。由於半導體製造製程技術的不斷進步，產生了具有更精細特徵及/或更高整合度的半導體裝置。功能密度(即，每一晶片區域內互連元件的數目)通常增加，而特徵尺寸(即，可以使用製造製程產出的最小構件)則縮小。此種尺寸縮小的製程通常藉由生產效率增加及製造成本降低而提供好處。
晶片封裝不僅為半導體裝置提供保護以免受環境汙染，也為封裝在其中的半導體裝置提供連接介面。已經開發出利用更少的面積或更低的高度的更小的封裝結構來封裝半導體裝置。
已經開發了新的封裝技術以進一步提高半導體晶粒(dies)的密度和功能。這些相對較新的半導體晶粒封裝技術目前面對許多製造挑戰。
本揭露的一些實施例提供一種形成封裝結構的方法，包括在承載基板之上形成重分佈結構以及將半導體晶粒放置在重分佈結構之上。所述形成封裝結構的方法還包括將中介層基板堆疊在重分佈結構之上。中介層基板延伸跨越半導體晶粒的邊緣。所述形成封裝結構的方法更包括將至少一裝置元件放置在中介層基板之上。此外，所述形成封裝結構的方法還包括形成包圍半導體晶粒的保護層。
本揭露的一些實施例提供一種形成封裝結構的方法，包括將第一半導體晶粒堆疊在重分佈結構之上。所述形成封裝結構的方法還包括將中介層基板接合到重分佈結構之上。中介層基板比第一半導體晶粒寬。所述形成封裝結構的方法更包括將第二半導體晶粒堆疊在中介層基板之上。此外，所述形成封裝結構的方法還包括形成包圍第一半導體晶粒的保護層。
本揭露的一些實施例提供一種封裝結構，包括重分佈結構、中介層基板、半導體晶粒以及保護層。中介層基板位於重分佈結構之上，且中介層基板比重分佈結構包含更多的填料。半導體晶粒位於重分佈結構與中介層基板之間。保護層包圍半導體晶粒，且保護層的一部分位於半導體晶粒與中介層基板之間。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下描述具體的構件及其排列方式的實施例以闡述本揭露。當然，這些實施例僅作為範例，而不該以此限定本揭露的範圍。例如，在說明書中敘述了一第一特徵形成於一第二特徵之上或上方，其可能包含第一特徵與第二特徵是直接接觸的實施例，亦可能包含了有附加特徵形成於第一特徵與第二特徵之間，而使得第一特徵與第二特徵可能未直接接觸的實施例。另外，在本揭露不同範例中可能使用重複的參考符號及/或標記，此重複係為了簡化與清晰的目的，並非用以限定所討論的各個實施例及/或結構之間有特定的關係。
除此之外，所使用到的空間相關用語，例如“在…下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用語，係為了便於描述圖示中一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外，這些空間相關用語意欲包含使用中或操作中的裝置之不同方位。設備/裝置可能被轉向不同方位(旋轉90度或其他方位)，則在此使用的空間相關詞也可依此相同解釋。
說明書中的用語「基本上(substantially)」，例如「基本上平坦」或「基本上共平面」等可為本領域技術人員所能理解。在一些實施例中，形容詞基本上可以被去除。在適用的情況下，用語「基本上」還可以包括「全部(entirely)」、「完全(completely)」、「所有(all)」等的實施例。在適用的情況下，用語「基本上」還可以涉及90%或更高，例如95%或更高，特別是99%或更高，包括100%。此外，例如「基本上平行」或「基本上垂直」之類的用語應解釋為不排除相較於特定佈置的微小偏差，並且例如可包括高達10°的偏差。用語「基本上」不排除「完全」，例如「基本上不含(substantially free)」Y的組合物可以是完全不含Y。
與特定距離或尺寸結合使用的例如「約」的用語應解釋為不排除相較於特定距離或尺寸的微小偏差，並且例如可包括高達10%的偏差。相對於數值X的用語「約」可能表示X ±5或10%。
以下描述本揭露的一些實施例。可以在這些實施例中描述的階段之前、之中及/或之後提供額外的操作。在不同的實施例中，可以替換或消除所述的某些階段。可以將附加特徵添加到版導體裝置結構中。在不同的實施例中，可以替換或消除所述的某些特徵。儘管下文中以特定順序執行的操作來討論一些實施例，但是也可以其他的邏輯順序來執行這些操作。
本揭露的實施例可以涉及3D封裝或3D-IC裝置。也可以包括其他特徵或製程。例如，可以包括測試結構以幫助對3D封裝或3D-IC裝置進行驗證測試。測試結構可以包括例如形成在重分佈層(redistribution layer)中或基板上的測試墊(pads)，其允許測試3D封裝或3D-IC裝置、使用探針及/或探針卡等。可以對中間結構以及最終結構執行驗證測試。另外，本文中揭露的結構以及方法可以與結合已知良好的晶粒的中間驗證的測試方法一起使用，從而提高產率並降低成本。
第1A至1G圖係根據本揭露一些實施例之形成一封裝結構的製程之各個階段的剖視圖。如第1A圖所示，根據一些實施例，在承載基板100之上形成重分佈結構102。承載基板100可為玻璃基板、半導體基板或另一種合適的基板。重分佈結構102可以用於佈線(routing)。重分佈結構102包括多個絕緣層104以及被絕緣層104包圍的多個導電特徵106。導電特徵106可以包括導線、導電通孔(vias)及/或導電墊。在一些實施例中，一些導電通孔彼此堆疊。上方的導電通孔與下方的導電通孔基本上對準。在一些實施例中，一些導電通孔為交錯排列的(staggered)通孔。上方的導電通孔與下方的導電通孔未對準。
重分佈結構102還包括用於保持或接收其他元件的導電元件108和導電元件110。在一些實施例中，導電元件108和導電元件110暴露於絕緣層104的最頂表面或從絕緣層104的最頂表面突出。導電元件108可以用於保持或接收一或多個半導體晶粒。導電元件110可以用於保持或接收例如導電柱及/或導電球的導電特徵。
絕緣層104可以由一或多種聚合物材料製成或包括一或多種聚合物材料。聚合物材料可以包括聚苯噁唑(polybenzoxazole，PBO)、聚醯亞胺(polyimide，PI)、環氧基樹脂或上述之組合。在一些實施例中，聚合物材料是光敏性的。因此，光微影製程可以用於在絕緣層104中形成具有期望圖案的開口。
在一些其他實施例中，絕緣層104的一部分或全部由聚合物材料以外的介電質材料製成或包括介電質材料。介電質材料可以包括氧化矽、碳化矽、氮化矽、氮氧化矽、一或多種其他合適的材料或上述之組合。
導電特徵106可以包括在水平方向上提供電連接的導線以及在垂直方向上提供電連接的導電通孔。導電特徵106可以包括或由銅、鋁、金、鈷、鈦、鎳、銀、石墨烯、一或多種其他合適的導電材料或上述之組合製成。在一些實施例中，導電特徵106包括多個子層。例如，每個導電特徵106包含多個子層，包括鈦/銅、鈦/鎳/銅、鈦/銅/鈦、鋁/鈦/鎳/銀、其他合適的多個子層或上述之組合。
重分佈結構102的形成可以涉及多個沉積或塗布製程、多個圖案化製程及/或多個平坦化製程。
沉積或塗布製程可以用於形成絕緣層及/或導電層。沉積或塗布製程可以包括旋轉塗布製程、電鍍製程、化學鍍製程(electroless process)、化學氣相沉積(chemical vapor deposition，CVD)製程、物理氣相沉積(physical vapor deposition，PVD)製程、原子層沉積(atomic layer deposition，ALD)製程、一或多種其他適用的製程或上述之組合。
圖案化製程可以用於圖案化形成的絕緣層及/或形成的導電層。圖案化製程可以包括光微影製程、能量束鑽孔製程(例如，雷射束鑽孔製程、離子束鑽孔製程或電子束鑽孔製程)、蝕刻製程、機械鑽孔製程、一或多種其他適用的製程或上述之組合。
平坦化製程可以用於為形成的絕緣層及/或形成的導電層提供平坦的頂表面，以利於後續的製程。平坦化製程可以包括機械研磨製程、化學機械研磨(chemical mechanical polishing ，CMP)製程、一或多種其他適用的製程或上述之組合。
之後，根據一些實施例，在重分佈結構102之上形成導電柱112，如第1A圖所示。每個導電柱112可以電性連接到一個導電特徵106。在一些實施例中，導電柱112中之一或多者具有垂直側壁。垂直側壁中之一者的延伸方向可以基本上垂直於重分佈結構102的底表面。
導電柱112可以包括或由銅、鋁、金、鈷、鈦、錫、一或多種其他合適的材料或上述之組合製成。可以使用電鍍製程、化學鍍製程、放置製程(placement process)、印刷製程、物理氣相沉積(PVD)製程、化學氣相沉積(CVD)製程、一或多種其他適用的製程或上述之組合來形成導電柱112。
如第1B圖所示，根據一些實施例，半導體晶粒114堆疊在重分佈結構102之上。半導體晶粒114可以包括應用處理器、電源管理積體電路、記憶體裝置、一或多個其他合適的電路或上述之組合。在一些實施例中，半導體晶粒114通過導電特徵116接合到導電元件108上。導電特徵116可以包括導電柱、焊料凸塊(solder bumps)、一或多個其他合適的接合結構或上述之組合。在一些實施例中，形成底膠材料(underfill material)118以包圍及保護導電特徵116。
在一些實施例中，如第1B圖所示，在重分佈結構102之上放置一或多個裝置元件120。裝置元件120可以接合到重分佈結構102的一些導電特徵106上。在一些實施例中，裝置元件120通過焊料凸塊、導電柱、一或多個其他合適的導電元件或上述之組合接合到重分佈結構102的墊區域(由一些導電特徵106構成)上。裝置元件120可以包括一或多個被動元件，例如電阻、電容、電感、一或多個其他合適的元件或上述之組合。在一些其他實施例中，裝置元件120包括記憶體裝置。在一些實施例中，裝置元件120包括電極121a及電極121b。在一些實施例中，裝置元件120的電極121a及電極121b焊接到重分佈結構102的墊區域上。
如第1C圖所示，根據一些實施例，中介層基板(interposer substrate)122堆疊在重分佈結構102之上。在一些實施例中，中介層基板122延伸跨越半導體晶粒114的邊緣。在一些實施例中，中介層基板122比半導體晶粒114寬。在一些實施例中，中介層基板122延伸跨越裝置元件120的邊緣。在一些實施例中，中介層基板122被導電柱112包圍或環繞。
在一些實施例中，如第1C圖所示，中介層基板122通過導電結構128接合到導電元件110上。導電結構128可以包括焊料凸塊、導電柱、其他合適的導電元件或上述之組合。在一些實施例中，中介層基板122與半導體晶粒114隔開一間隙，如第1C圖所示。
在一些實施例中，中介層基板122包括板124以及導電元件126。導電元件126可以包括或由銅、鋁、鈷、鎳、金、銀、鎢、一或多種其他合適的材料或上述之組合製成。板124可以包括或由聚合物材料、陶瓷材料、金屬材料、半導體材料、一或多種其他合適的材料或上述之組合製成。例如，板124包括樹脂、膠片(prepreg)、玻璃及/或陶瓷。在板124由金屬材料或半導體材料製成的情況下，可以在板124與導電元件126之間形成介電層以防止短路。
在板124由聚合物材料製成或包括聚合物材料的情況下，板124可以進一步包括分散在聚合物材料中的填料。聚合物材料可以包括環氧基樹脂、聚醯亞胺基樹脂、一或多種其他合適的聚合物材料或上述之組合。填料的範例可以包括纖維(例如，二氧化矽纖維及/或含碳纖維)、顆粒(例如，二氧化矽顆粒及/或含碳顆粒)或上述之組合。
在一些實施例中，中介層基板122比重分佈結構102包含更多的填料。在一些實施例中，板124具有比重分佈結構102的絕緣層104更大的填料重量百分比。在一些實施例中，重分佈結構102的絕緣層104包括或由聚合物材料製成。在一些實施例中，重分佈結構102的絕緣層104不包含填料。在這些情況下，重分佈結構102不包含填料。
在一些實施例中，中介層基板122和承載基板100在高溫下彼此擠壓。結果，中介層基板122通過導電結構128接合到重分佈結構102上。在一些實施例中，使用熱壓合製程來達成上述接合製程。
如第1C圖所示，根據一些實施例，裝置元件130堆疊在重分佈結構102之上。裝置元件130可以電性連接到重分佈結構102的一個導電特徵106。裝置元件130可以包括被動元件及/或記憶體裝置。
如第1D圖所示，根據一些實施例，在中介層基板122之上放置裝置元件132。裝置元件132可以接合或電性連接到中介層基板122的一些導電元件126。裝置元件132可以包括一或多個被動元件，例如電阻、電容、電感、一或多個其他合適的元件或上述之組合。在一些其他實施例中，裝置元件132包括記憶體裝置。一些裝置元件132具有相同或相似的功能。例如，它們用作電阻或電容。一些裝置元件132具有不同的功能。例如，一些裝置元件132包括被動元件，而一些其他裝置元件132包括記憶體裝置。
如第1E圖所示，根據一些實施例，由互連結構136承載的模組134堆疊在中介層基板122之上。在一些實施例中，模組134延伸跨越中介層基板122的邊緣。在一些實施例中，互連結構136延伸跨越中介層基板122的邊緣。
在一些實施例中，模組134通過導電柱112及焊料元件142接合到重分佈結構102上。焊料元件142可以由含錫材料製成。含錫材料可以進一步包括銅、銀、金、鋁、鉛、一或多種其他合適的材料或上述之組合。在一些實施例中，焊料元件142是無鉛的。
在一些實施例中，模組134是具有一或多個半導體晶粒的封裝模組。例如，此封裝模組包括多個記憶體晶粒。在一些實施例中，模組134是一半導體晶粒。例如，此半導體晶粒包括多個記憶體裝置。
在一些實施例中，互連結構136是承載模組134的中介層基板。在這些情況下，互連結構136具有與中介層基板122相似的結構。在一些實施例中，互連結構136包括板138以及導電元件140。板138的材料可以與中介層基板122的板124的材料相同或相似。導電元件140的材料可以與中介層基板122的導電元件126的材料相同或相似。
然而，本揭露的實施例不限於此。可以對本揭露的實施例進行許多變化及/或修改。在一些其他實施例中，互連結構136具有與重分佈結構102相似的結構。
如第1F圖所示，根據一些實施例，形成保護層144以包圍及保護半導體晶粒114。在一些實施例中，保護層144也包護及保護中介層基板122。在一些實施例中，保護層144還包圍及保護安裝在中介層基板122上的裝置元件132。在一些實施例中，保護層144包圍及保護導電柱112和焊料元件142。在一些實施例中，保護層144的一部分位於互連結構136與中介層基板122之間，如第1F圖所示。在一些實施例中，保護層144的一部分位於半導體晶粒114與中介層基板122之間。
在一些實施例中，保護層144藉由底膠材料118與半導體晶粒114下方的導電特徵116分離。然而，本揭露的實施例不限於此。可以對本揭露的實施例進行許多變化及/或修改。在一些其他實施例中，未形成底膠材料118。在這些情況下，保護層144可以與半導體晶粒114下方的導電特徵116直接接觸。
在一些實施例中，保護層144包括或由絕緣材料製成，例如模製材料(molding material)。模製材料可以包括聚合物材料，例如其中分散有填料的環氧基樹脂。在一些實施例中，模製材料(例如，液體模製材料)被引入或注入到互連結構136與重分佈結構102之間的空間中。在一些實施例中，然後使用熱處理來固化液體模製材料並將其轉變成保護層144。
之後，根據一些實施例，去除承載基板100以暴露出重分佈結構102的表面，如第1F圖所示。
如第1G圖所示，根據一些實施例，在重分佈結構102的原來由承載基板100覆蓋的表面之上形成導電凸塊146。每個導電凸塊146可以電性連接到重分佈結構102的一個導電特徵106。在一些實施例中，導電凸塊146是或包括例如含錫焊料凸塊的焊料凸塊。含錫焊料凸塊可以進一步包括銅、銀、金、鋁、鉛、一或多種其他合適的材料或上述之組合。在一些實施例中，含錫焊料凸塊是無鉛的。
在一些實施例中，在去除承載基板100之後，將焊球(或焊料元件)放置在暴露的導電特徵106上。然後進行回焊(reflow)製程以將焊球熔化成導電凸塊146。在一些其他實施例中，在放置焊球之前，在暴露的導電特徵106之上形成凸塊下金屬化(under bump metallization，UBM)元件。在一些其他實施例中，焊料元件被電鍍到暴露的導電特徵106上。然後使用回焊製程將焊料元件熔化以形成導電凸塊146。
如第1G圖所示，根據一些實施例，然後將半導體晶粒148堆疊在重分佈結構102的原來由承載基板100覆蓋的表面之上。半導體晶粒148可以包括應用處理器、電源管理積體電路、記憶體裝置、一或多個其他合適的電路或上述之組合。在一些實施例中，半導體晶粒148通過導電特徵150接合到重分佈結構102上。導電特徵150可以包括導電柱、焊料凸塊、一或多個其他合適的接合結構或上述之組合。在一些實施例中，形成底膠材料152以包圍及保護導電特徵150。
在一些其他實施例中，在重分佈結構102的原來由承載基板100覆蓋的表面之上形成一或多個其他表面安裝裝置(surface mounted devices)。表面安裝裝置可以包括被動元件及/或記憶體裝置。
在一些實施例中，然後執行分割(singulation)製程。結果，形成多個分開的封裝結構。在第1G圖中，示出了其中一個封裝結構。如第1G圖所示，半導體晶粒114位於半導體晶粒148的正上方。半導體晶粒114和半導體晶粒148可以通過重分佈結構102的一些導電特徵106彼此通信。因此，RC延遲及/或信號雜訊被顯著降低，並且信號傳輸速度得到改善。
可以對本揭露的實施例進行許多變化及/或修改。第2圖係根據一些實施例的封裝結構的剖視圖。在一些實施例中，半導體晶粒148未接合到重分佈結構102上。
可以對本揭露的實施例進行許多變化及/或修改。第3A至3H圖係根據一些實施例之形成一封裝結構的製程之各個階段的剖視圖。
如第3A圖所示，根據一些實施例，導電柱112’形成在由承載基板100承載的重分佈結構102之上(類似於第1A圖所示的實施例)。導電柱112’的材料和形成方法可以與第1A圖所示的導電柱112的材料和形成方法相同或相似。
如第3B圖所示，根據一些實施例，半導體晶粒302堆疊在重分佈結構102之上。半導體晶粒302可以包括應用處理器、電源管理積體電路、記憶體裝置、一或多個其他合適的電路或上述之組合。在一些實施例中，半導體晶粒302通過導電特徵304接合到導電元件108上。導電特徵304可以包括導電柱、焊料凸塊、一或多個其他合適的接合結構或上述之組合。在一些實施例中，形成底膠材料306以包圍及保護導電特徵304。
在一些實施例中，如第3B圖所示，在重分佈結構102之上放置一或多個裝置元件308。裝置元件308可以接合到重分佈結構102的一些導電特徵106上。裝置元件308可以類似於第1B圖所示的裝置元件120。
如第3C圖所示，根據一些實施例，中介層基板310堆疊在重分佈結構102之上。在一些實施例中，中介層基板310延伸跨越半導體晶粒302的邊緣。在一些實施例中，中介層基板310比半導體晶粒302寬。在一些實施例中，中介層基板310延伸跨越裝置元件308的邊緣。在一些實施例中，中介層基板310延伸跨越導電柱112’的邊緣。
在一些實施例中，如第3C圖所示，中介層基板310通過導電結構316接合到導電柱112’上。導電結構316可以包括焊料凸塊、導電柱、其他合適的導電元件或上述之組合。在一些實施例中，中介層基板310與半導體晶粒302隔開一間隙，如第3C圖所示。
在一些實施例中，中介層基板310包括板314以及導電元件312。板314的材料可以與第1C圖所示的板124的材料相同或相似。導電元件312的材料可以與導電元件126的材料相同或相似。
在一些實施例中，中介層基板310和承載基板100在高溫下彼此擠壓。因此，中介層基板310通過導電結構316接合到重分佈結構102上。在一些實施例中，使用熱壓合製程來達成上述接合製程。
如第3D圖所示，根據一些實施例，形成保護層318以包圍及保護半導體晶粒302。在一些實施例中，保護層318位於中介層基板310與重分佈結構102之間。在一些實施例中，保護層318還包圍及保護安裝在重分佈結構102上的裝置元件308。在一些實施例中，保護層318包圍及保護導電柱112’和導電結構316。在一些實施例中，保護層318的一部分位於半導體晶粒302與中介層基板310之間，如第3D圖所示。保護層318的材料和形成方法可以與第1F圖所示的保護層144的材料和形成方法相同或相似。
如第3E圖所示，根據一些實施例，承載基板320接合到中介層基板310上。之後，如第3E圖所示，去除承載基板100以暴露出重分佈結構102的表面。
如第3F圖所示，根據一些實施例，在重分佈結構102的原來由承載基板100覆蓋的表面之上形成導電凸塊322。每個導電凸塊322可以電性連接到重分佈結構102的一個導電特徵106。導電凸塊322的材料和形成方法可以與第1G圖所示的導電凸塊146的材料和形成方法相同或相似。
如第3F圖所示，根據一些實施例，然後將半導體晶粒324堆疊在重分佈結構102的原來由承載基板100覆蓋的表面之上。半導體晶粒324可以包括應用處理器、電源管理積體電路、記憶體裝置、一或多個其他合適的電路或上述之組合。在一些實施例中，半導體晶粒324通過導電特徵326接合到重分佈結構102上。導電特徵326可以包括導電柱、焊料凸塊、一或多個其他合適的接合結構或上述之組合。在一些實施例中，形成底膠材料328以包圍及保護導電特徵326。
在一些其他實施例中，在重分佈結構102的原來由承載基板100覆蓋的表面之上形成一或多個其他表面安裝裝置。表面安裝裝置可以包括被動元件及/或記憶體裝置。
如第3G圖所示，根據一些實施例，去除承載基板320以暴露出中介層基板310。在一些實施例中，在去除承載基板320之前，第3F圖所示的結構被貼附到膠帶載體(tape carrier)上。
如第3H圖所示，根據一些實施例，在中介層基板310之上放置半導體晶粒330及裝置元件336。半導體晶粒330可以包括應用處理器、電源管理積體電路、記憶體裝置、一或多個其他合適的電路或上述之組合。在一些實施例中，半導體晶粒330通過導電特徵332接合到中介層基板310上。導電特徵332可以包括導電柱、焊料凸塊、一或多個其他合適的接合結構或上述之組合。在一些實施例中，形成底膠材料334以包圍及保護導電特徵332。裝置元件336可以接合並電性連接到中介層基板310的一些導電元件312。裝置元件336可以包括被動元件及/或記憶體裝置。
在一些實施例中，然後執行分割製程。結果，形成多個分開的封裝結構。之後，將封裝結構從膠帶載體上去除。在第3H圖中，示出了其中一個封裝結構。
可以對本揭露的實施例進行許多變化及/或修改。第4A至4F圖係根據一些實施例之形成一封裝結構的製程之各個階段的剖視圖。
如第4A圖所示，根據一些實施例，在承載基板100之上形成重分佈結構102(類似於第1A圖所示的實施例)。在一些實施例中，在形成重分佈結構102之前，在承載基板100之上形成離型膜(release film)101。離型膜101是暫時性接合材料，其有助於承載基板100與重分佈結構102之間的後續分離操作。離型膜101也可在第1A至1G圖、第2圖和第3A至3G圖所示的實施例中使用。
如第4B圖所示，根據一些實施例，半導體晶粒402堆疊在重分佈結構102之上。半導體晶粒402可以包括應用處理器、電源管理積體電路、記憶體裝置、一或多個其他合適的電路或上述之組合。在一些實施例中，半導體晶粒402通過導電特徵404接合到導電元件108上。導電特徵404可以包括導電柱、焊料凸塊、一或多個其他合適的接合結構或上述之組合。在一些實施例中，形成底膠材料406以包圍及保護導電特徵404。
在一些實施例中，如第4B圖所示，在重分佈結構102之上放置一或多個裝置元件408。裝置元件408可以接合到重分佈結構102的一些導電特徵106上。裝置元件408可以包括被動元件及/或記憶體裝置。
如第4C圖所示，根據一些實施例，由互連結構410承載的模組416堆疊在重分佈結構102之上。在一些實施例中，模組416延伸跨越半導體晶粒402的邊緣。
在一些實施例中，模組416通過導電結構418接合到重分佈結構102的導電元件110上。導電結構418可以包括焊料凸塊、導電柱、其他合適的導電元件或上述之組合。在一些實施例中，互連結構410與半導體晶粒402隔開一間隙，如第4C圖所示。
在一些實施例中，模組416是具有一或多個半導體晶粒的封裝模組。例如，此封裝模組包括多個記憶體晶粒。在一些實施例中，模組416是一半導體晶粒。例如，此半導體晶粒包括多個記憶體裝置。
在一些實施例中，互連結構410是承載模組416的中介層基板。在這些情況下，互連結構410具有與第1C圖所示的中介層基板122相似的結構。在一些實施例中，互連結構410包括板4以及導電元件414。板412的材料可以與中介層基板122的板124的材料相同或相似。導電元件414的材料可以與中介層基板122的導電元件126的材料相同或相似。
然而，本揭露的實施例不限於此。可以對本揭露的實施例進行許多變化及/或修改。在一些其他實施例中，互連結構410具有與重分佈結構102相似的結構。
如第4C圖所示，根據一些實施例，形成保護層420以包圍及保護半導體晶粒402。在一些實施例中，保護層420也包圍及保護安裝在重分佈結構102上的裝置元件408。在一些實施例中，保護層420還包圍及保護導電結構418。在一些實施例中，保護層420的一部分位於互連結構410與重分佈結構102之間，如第4C圖所示。保護層420的材料和形成方法可以與第1F圖所示的保護層144的材料和形成方法相同或相似。
如第4D圖所示，根據一些實施例，第4C圖所示的結構被上下顛倒並貼附到膠帶載體422上。之後，去除承載基板100和離型膜101以暴露出重分佈結構102的表面。
如第4E圖所示，根據一些實施例，在重分佈結構102的原來由承載基板100覆蓋的表面之上形成導電凸塊424。每個導電凸塊424可以電性連接到重分佈結構102的一個導電特徵106。導電凸塊424的材料和形成方法可以與第1G圖所示的導電凸塊146的材料和形成方法相同或相似。
如第4E圖所示，根據一些實施例，然後將半導體晶粒426堆疊在重分佈結構102的原來由承載基板100覆蓋的表面之上。半導體晶粒426可以包括應用處理器、電源管理積體電路、記憶體裝置、一或多個其他合適的電路或上述之組合。在一些實施例中，半導體晶粒426通過導電特徵428接合到重分佈結構102上。導電特徵428可以包括導電柱、焊料凸塊、一或多個其他合適的接合元件或上述之組合。在一些實施例中，形成底膠材料430以包圍及保護導電特徵428。
在一些其他實施例中，在重分佈結構102的原來由承載基板100覆蓋的表面之上形成一或多個其他表面安裝裝置。表面安裝裝置可以包括被動元件及/或記憶體裝置。
在一些實施例中，然後執行分割製程。結果，形成多個分開的封裝結構。然後，將封裝結構從膠帶載體422上去除。在第4F圖中，示出了其中一個封裝結構。
可以對本揭露的實施例進行許多變化及/或修改。第5A至5F圖係根據一些實施例之形成一封裝結構的製程之各個階段的剖視圖。
如第5A圖所示，提供或接收類似於第4A圖所示的結構。根據一些實施例，之後，導電柱502形成在重分佈結構102之上。
如第5B圖所示，根據一些實施例，使用黏合元件506將半導體晶粒503貼附到重分佈結構102上。例如，黏合元件506是晶粒貼附膠帶。如第5B圖所示，半導體晶粒503的導電柱504面向上。半導體晶粒503可以包括應用處理器、電源管理積體電路、記憶體裝置、一或多個其他合適的電路或上述之組合。
之後，根據一些實施例，形成保護層508以包圍及保護半導體晶粒503和導電柱502，如第5B圖所示。保護層508的材料和形成方法可以與第1F圖所示的保護層144的材料和形成方法相同或相似。在一些實施例中，在保護層508上進行平坦化製程以部分地去除保護層508。結果，導電柱502和導電柱504的頂表面被暴露(如第5B圖所示)。在一些實施例中，保護層508的頂表面與導電柱502和導電柱504的頂表面基本上齊平。平坦化製程可以包括機械研磨製程、化學機械研磨(CMP)製程、蝕刻製程、乾式研磨製程、一或多種其他適用的製程或上述之組合。
如第5C圖所示，根據一些實施例，在保護層508之上形成重分佈結構510。類似於第1A圖所示的重分佈結構102，重分佈結構510包括多個絕緣層512、導電特徵514以及導電元件516和導電元件518。重分佈結構510的材料和形成方法可以與第1A圖所示的重分佈結構102的材料和形成方法相同或相似。
如第5D圖所示，根據一些實施例，半導體晶粒520堆疊在重分佈結構510之上。在一些實施例中，半導體晶粒520通過導電特徵522接合到導電元件516上。在一些實施例中，形成底膠材料524以包圍及保護導電特徵522。在一些實施例中，如第5B圖所示，在重分佈結構510之上放置一或多個裝置元件526。裝置元件526可以接合到重分佈結構510的一些導電特徵514上。裝置元件526可以包括被動元件及/或記憶體裝置。
如第5E圖所示，根據一些實施例，由互連結構528承載的模組534堆疊在重分佈結構510之上。在一些實施例中，模組534延伸跨越半導體晶粒520的邊緣。
在一些實施例中，模組534通過導電結構536接合到重分佈結構510的導電元件518上。導電結構536可以包括焊料凸塊、導電柱、其他合適的導電元件或上述之組合。在一些實施例中，互連結構528與半導體晶粒520隔開一間隙，如第5E圖所示。
在一些實施例中，模組534是具有一或多個半導體晶粒的封裝模組。例如，此封裝模組包括多個記憶體晶粒。在一些實施例中，模組534是一半導體晶粒。例如，此半導體晶粒包括多個記憶體裝置。
在一些實施例中，互連結構528是承載模組534的中介層基板。在這些情況下，互連結構528具有與第1C圖所示的中介層基板122相似的結構。在一些實施例中，互連結構528包括板530以及導電元件532。板530的材料可以與中介層基板122的板124的材料相同或相似。導電元件532的材料可以與中介層基板122的導電元件126的材料相同或相似。
然而，本揭露的實施例不限於此。可以對本揭露的實施例進行許多變化及/或修改。在一些其他實施例中，互連結構528具有與重分佈結構510相似的結構。
之後，根據一些實施例，形成保護層538以包圍及保護半導體晶粒520，如第5E圖所示。在一些實施例中，保護層538也包圍及保護安裝在重分佈結構510上的裝置元件526。在一些實施例中，保護層538還包圍及保護導電結構536。在一些實施例中，保護層538的一部分位於互連結構528與重分佈結構510之間，如第5E圖所示。保護層538的材料和形成方法可以與第1F圖所示的保護層144的材料和形成方法相同或相似。
如第5F圖所示，根據一些實施例，去除承載基板100和離型膜101以暴露出重分佈結構102的表面。之後，根據一些實施例，在重分佈結構102的原來由承載基板100覆蓋的表面之上形成導電凸塊540，如第5F圖所示。每個導電凸塊540可以電性連接到重分佈結構102的一個導電特徵106。導電凸塊540的材料和形成方法可以與第1G圖所示的導電凸塊146的材料和形成方法相同或相似。
在一些實施例中，然後執行分割製程。結果，形成多個分開的封裝結構。在第5F圖中，示出了其中一個封裝結構。
可以對本揭露的實施例進行許多變化及/或修改。第6A至6D圖係根據一些實施例之形成一封裝結構的製程之各個階段的剖視圖。如第6A圖所示，根據一些實施例，提供或接收類似於第5D圖所示的結構。
如第6B圖所示，根據一些實施例，中介層基板602堆疊在重分佈結構510之上。在一些實施例中，中介層基板602延伸跨越半導體晶粒520的邊緣。在一些實施例中，中介層基板602比半導體晶粒520寬。在一些實施例中，中介層基板602延伸跨越裝置元件526的邊緣。
在一些實施例中，如第6B圖所示，中介層基板602通過導電結構608接合到導電元件518上。導電結構608可以包括焊料凸塊、導電柱、其他合適的導電元件或上述之組合。在一些實施例中，中介層基板602與半導體晶粒520隔開一間隙，如第6B圖所示。
在一些實施例中，中介層基板602包括板604以及導電元件606。板604的材料可以與第1C圖所示的板124的材料相同或相似。導電元件606的材料可以與導電元件126的材料相同或相似。
在一些實施例中，中介層基板602與承載基板100在高溫下彼此擠壓。結果，中介層基板602通過導電結構608接合到重分佈結構510上。在一些實施例中，使用熱壓合製程來達成上述接合製程。
如第6B圖所示，根據一些實施例，形成保護層610以包圍及保護半導體晶粒520。在一些實施例中，保護層610位於中介層基板602與重分佈結構510之間。在一些實施例中，保護層610還包圍及保護安裝在重分佈結構510上的裝置元件526。在一些實施例中，保護層610包圍及保護導電元件518和導電結構608。在一些實施例中，保護層610的一部分位於半導體晶粒520與中介層基板602之間，如第6B圖所示。保護層610的材料和形成方法可以與第1F圖所示的保護層144的材料和形成方法相同或相似。
如第6C圖所示，根據一些實施例，由互連結構612承載的模組618堆疊在中介層基板602之上。在一些實施例中，模組618通過導電結構620接合到中介層基板602的導電元件606上。導電結構620可以包括焊料凸塊、導電柱、其他合適的導電元件或上述之組合。在一些實施例中，互連結構612與中介層基板602隔開一間隙，如第6C圖所示。在一些實施例中，形成底膠材料622以填充間隙並保護導電結構620。
在一些實施例中，模組618是具有一或多個半導體晶粒的封裝模組。例如，此封裝模組包括多個記憶體晶粒。在一些實施例中，模組618是一半導體晶粒。例如，此半導體晶粒包括多個記憶體裝置。
在一些實施例中，互連結構612是承載模組618的中介層基板。在這些情況下，互連結構612具有與第1C圖所示的中介層基板122相似的結構。在一些實施例中，互連結構612包括板614以及導電元件616。板614的材料可以與中介層基板122的板124的材料相同或相似。導電元件616的材料可以與中介層基板122的導電元件126的材料相同或相似。
然而，本揭露的實施例不限於此。可以對本揭露的實施例進行許多變化及/或修改。在一些其他實施例中，互連結構612具有與重分佈結構102相似的結構。
如第6D圖所示，根據一些實施例，去除承載基板100和離型膜101以暴露出重分佈結構102的表面。之後，根據一些實施例，在重分佈結構102的原來由承載基板100覆蓋的表面之上形成導電凸塊624，如第6D圖所示。每個導電凸塊624可以電性連接到重分佈結構102的一個導電特徵106。導電凸塊624的材料和形成方法可以與第1G圖所示的導電凸塊146的材料和形成方法相同或相似。
在一些實施例中，然後執行分割製程。結果，形成多個分開的封裝結構。在第6D圖中，示出了其中一個封裝結構。
可以對本揭露的實施例進行許多變化及/或修改。第7A至7G圖係根據一些實施例之形成一封裝結構的製程之各個階段的剖視圖。
如第7A圖所示，提供或接收類似於第4A圖所示的結構。之後，根據一些實施例，半導體晶粒702以及裝置元件708堆疊在重分佈結構102之上。在一些實施例中，半導體晶粒702通過導電特徵704接合到重分佈結構102的導電元件108上。在一些實施例中，形成底膠材料706以包圍及保護導電特徵704。裝置元件708可以包括被動元件及/或記憶體裝置。
如第7B圖所示，根據一些實施例，中介層基板710堆疊在重分佈結構102之上。在一些實施例中，中介層基板710延伸跨越半導體晶粒702的邊緣。在一些實施例中，中介層基板710比半導體晶粒702寬。在一些實施例中，中介層基板710延伸跨越裝置元件708的邊緣。
在一些實施例中，如第7B圖所示，中介層基板710通過導電結構716接合到導電元件110上。導電結構716可以包括焊料凸塊、導電柱、其他合適的導電元件或上述之組合。在一些實施例中，中介層基板710與半導體晶粒702隔開一間隙，如第7B圖所示。
在一些實施例中，中介層基板710包括板712以及導電元件714。板712的材料可以與第1C圖所示的板124的材料相同或相似。導電元件714可以與導電元件126的材料相同或相似。
在一些實施例中，中介層基板710與承載基板100在高溫下彼此擠壓。因此，中介層基板710通過導電結構716接合到重分佈結構102上。在一些實施例中，使用熱壓合製程來達成上述接合製程。
如第7B圖所示，根據一些實施例，形成保護層718以包圍及保護半導體晶粒702。在一些實施例中，保護層718位於中介層基板710與重分佈結構102之間。在一些實施例中，保護層718還包圍及保護安裝在重分佈結構102上的裝置元件708。在一些實施例中，保護層718包圍及保護導電結構716。在一些實施例中，保護層718的一部分位於半導體晶粒702與中介層基板710之間，如第7B圖所示。保護層718的材料和形成方法可以與第1F圖所示的保護層144的材料和形成方法相同或相似。
如第7C圖所示，根據一些實施例，第7B圖所示的結構被上下顛倒並通過離型膜722貼附到承載基板720上。之後，去除承載基板100和離型膜101。結果，重分佈結構102的原來由承載基板100覆蓋的表面被暴露(如第7C圖所示)。
如第7D圖所示，根據一些實施例，在重分佈結構102之上形成導電柱724。每個導電柱724電性連接到重分佈結構102的一個導電特徵106。導電柱724的材料和形成方法可以與第1A圖所示的導電柱112的材料和形成方法相同或相似。在一些實施例中，在形成導電柱724之前，使用圖案化製程在重分佈結構102中形成開口以暴露一些導電特徵106。
之後，根據一些實施例，半導體晶粒726堆疊在重分佈結構102之上，如第7D圖所示。在一些實施例中，半導體晶粒726通過導電特徵728接合到重分佈結構102上。每個導電特徵728可以電性連接到重分佈結構102的一個導電特徵106。在一些實施例中，如第7D圖所示，導電柱724的高度高於半導體晶粒726的高度。
如第7E圖所示，根據一些實施例，形成保護層730以包圍及保護半導體晶粒726和導電柱724。保護層730的材料和形成方法可以與第1F圖所示的保護層144的材料和形成方法相同或相似。在一些實施例中，使用平坦化製程來使保護層730變薄。結果，保護層730具有基本上平坦的頂表面，其有助於後續的製程。在一些實施例中，保護層730的頂表面與導電柱724的頂表面基本上齊平。平坦化製程可以包括機械研磨製程、化學機械研磨(CMP)製程、蝕刻製程、乾式研磨製程、一或多種其他適用的製程或上述之組合。
之後，根據一些實施例，在保護層730之上形成重分佈結構732，如第7E圖所示。類似於第1A圖所示的重分佈結構102，重分佈結構732包括多個絕緣層734以及導電特徵736。重分佈結構732的材料和形成方法可以與第1A圖所示的重分佈結構102的材料和形成方法相同或相似。
如第7F圖所示，根據一些實施例，在重分佈結構732之上形成導電凸塊738。每個導電凸塊738可以電性連接到重分佈結構732的一個導電特徵736。導電凸塊738的材料和形成方法可以與第1G圖所示的導電凸塊146的材料和形成方法相同或相似。
如第7G圖所示，根據一些實施例，第7F圖所示的結構被上下顛倒並貼附到膠帶載體740上。之後，去除承載基板720和離型膜722。結果，中介層基板710的原來由承載基板720覆蓋的表面被暴露(如第7G圖所示)。
之後，根據一些實施例，由互連結構742承載的模組748堆疊在中介層基板710之上，如第7G圖所示。在一些實施例中，模組748通過導電結構750接合到中介層基板710上。導電結構750可以包括焊料凸塊、導電柱、其他合適的導電元件或上述之組合。在一些實施例中，互連結構742與中介層基板710隔開一間隙，如第7G圖所示。在一些實施例中，形成底膠材料752以填充間隙並保護導電結構750。
在一些實施例中，模組748是具有一或多個半導體晶粒的封裝模組。例如，此封裝模組包括多個記憶體晶粒。在一些實施例中，模組748是一半導體晶粒。例如，此半導體晶粒包括多個記憶體裝置。
在一些實施例中，互連結構742是承載模組748的中介層基板。在這些情況下，互連結構742具有與第1C圖所示的中介層基板122相似的結構。在一些實施例中，互連結構742包括板744以及導電元件746。板744的材料可以與中介層基板122的板124的材料相同或相似。導電元件746的材料可以與中介層基板122的導電元件126的材料相同或相似。
然而，本揭露的實施例不限於此。可以對本揭露的實施例進行許多變化及/或修改。在一些其他實施例中，互連結構742具有與重分佈結構102相似的結構。
在一些實施例中，然後執行分割製程。結果，形成多個分開的封裝結構。之後，將封裝結構從膠帶載體上去除。
可以對本揭露的實施例進行許多變化及/或修改。第8A至8G圖係根據本揭露一些實施例之形成一封裝結構的製程之各個階段的剖視圖。如第8A圖所示，類似於第7A圖所示的實施例，在承載基板100之上形成重分佈結構102。重分佈結構102與承載基板100之間的離型膜101用於促進承載基板100與重分佈結構102之間的後續分離製程。
如第8B圖所示，根據一些實施例，中介層基板802堆疊在重分佈結構102之上。在一些實施例中，在堆疊中介層基板802之前，半導體晶粒808通過導電特徵810接合到中介層基板802上。形成底膠材料812以包圍及保護導電特徵810。在中介層基板802的堆疊期間，半導體晶粒808被佈置在重分佈結構102之上並且位於中介層基板802與重分佈結構102之間。在一些實施例中，中介層基板802延伸跨越半導體晶粒808的邊緣。在一些實施例中，中介層基板802比半導體晶粒808寬。
在一些實施例中，如第8B圖所示，中介層基板802通過導電結構814接合到重分佈結構102上。導電結構814可以包括焊料凸塊、導電柱、其他合適的導電元件或上述之組合。每個導電結構814可以電性連接到重分佈結構102的一個導電特徵106。在一些實施例中，在中介層基板802接合到重分佈結構102上之後，半導體晶粒808與重分佈結構102隔開一間隙，如第8B圖所示。
在一些實施例中，中介層基板802包括板8以及導電元件806。板804的材料可以與第1C圖所示的板124的材料相同或相似。導電元件806的材料可以與導電材料126的材料相同或相似。
在一些實施例中，中介層基板802與承載基板100在高溫下彼此擠壓。結果，中介層基板802通過導電結構814接合到重分佈結構102上。在一些實施例中，使用熱壓合製程來達成上述接合製程。
如第8B圖所示，根據一些實施例，形成保護層816以包圍及保護半導體晶粒808。在一些實施例中，保護層816位於中介層基板802與重分佈結構102之間。在一些實施例中，保護層816包圍及保護導電結構814。在一些實施例中，保護層816的一部分位於半導體晶粒808與重分佈結構102之間，如第8B圖所示。保護層816的材料和形成方法可以與第1F圖所示的保護層144的材料和形成方法相同或相似。
之後，根據一些實施例，在中介層基板802之上形成介電層818，如第8B圖所示。介電層818可以包括或由聚合物材料製成。聚合物材料可以包括聚醯亞胺、聚苯噁唑、一或多種其他合適的材料或上述之組合。或者，介電層818可以包括或由氧化矽、氮化矽、氮氧化矽、碳化矽、一或多種其他合適的材料或上述之組合。可以使用旋轉塗布製程、噴灑塗布製程、化學氣相沉積(CVD)製程、層壓製程、一或多種其他適用的製程或上述之組合來形成介電層818。
在一些實施例中，在介電層818上進行平坦化製程。結果，介電層818具有基本上平坦的頂表面，其有助於後續的製程。平坦化製程可以包括機械研磨製程、化學機械研磨(CMP)製程、蝕刻製程、乾式研磨製程、一或多種其他適用的製程或上述之組合。
如第8C圖所示，根據一些實施例，導電柱820形成在中介層基板802之上。每個導電柱820電性連接到中介層基板802的一個導電元件806。導電柱820的材料和形成方法可以與第1A圖所示的導電柱112的材料和形成方法相同或相似。在一些實施例中，在形成導電柱820之前，使用圖案化製程在介電層818中形成開口以暴露中介層基板802的一個導電元件806。一些暴露的導電元件806是用於保持導電柱820。一些暴露的導電元件806可以用於保持隨後堆疊的半導體晶粒及/或隨後堆疊的裝置元件。
之後，根據一些實施例，半導體晶粒822堆疊在中介層基板802之上，如第8C圖所示。在一些實施例中，半導體晶粒822通過導電特徵826接合到中介層基板802上。每個導電特徵826可以電性連接到中介層基板802的一個導電元件806。在一些實施例中，導電柱820的高度高於半導體晶粒822的高度，如第8C圖所示。在一些實施例中，裝置元件830接合到中介層基板802上。裝置元件830可以包括一或多個被動元件及/或一或多個記憶體裝置。
如第8D圖所示，根據一些實施例，形成保護層832以包圍及保護半導體晶粒822、裝置元件830以及導電柱820。保護層832的材料和形成方法可以與第1F圖所示的保護層144的材料和形成方法相同或相似。在一些實施例中，使用平坦化製程來使保護層832變薄。結果，保護層832具有基本上平坦的頂表面，其有助於後續的製程。在一些實施例中，保護層832的頂表面與導電柱820的頂表面基本上齊平。平坦化製程可以包括機械研磨製程、化學機械研磨(CMP)製程、蝕刻製程、乾式研磨製程、一或多種其他適用的製程或上述之組合。
如第8E圖所示，根據一些實施例，在保護層832及導電柱820之上形成重分佈結構834。類似於第1圖所示的重分佈結構102，重分佈結構834包括多個絕緣層836以及導電特徵838。重分佈結構834的材料和形成方法可以與第1A圖所示的重分佈結構102的材料和形成方法相同或相似。
如第8F圖所示，根據一些實施例，由互連結構840承載的模組846堆疊在重分佈結構834之上。在一些實施例中，模組846通過導電結構848接合到重分佈結構834上。導電結構848可以包括焊料凸塊、導電柱、其他合適的導電元件或上述之組合。在一些實施例中，互連結構840與重分佈結構834隔開一間隙，如第8F圖所示。在一些實施例中，形成底膠材料850以填充間隙並保護導電結構848。
在一些實施例中，模組846是具有一或多個半導體晶粒的封裝模組。例如，此封裝模組包括多個記憶體晶粒。在一些實施例中，模組846是一半導體晶粒。例如，此半導體晶粒包括多個記憶體裝置。
在一些實施例中，互連結構840是承載模組846的中介層基板。在這些情況下，互連結構840具有與第1C圖所示的中介層基板122相似的結構。在一些實施例中，互連結構840包括板842以及導電元件844。板842的材料可以與中介層基板122的板124的材料相同或相似。導電元件844的材料可以與中介層基板122的導電元件126的材料相同或相似。
然而，本揭露的實施例不限於此。可以對本揭露的實施例進行許多變化及/或修改。在一些其他實施例中，互連結構840具有與重分佈結構102相似的結構。
如第8G圖所示，根據一些實施例，去除承載基板100和離型膜101，然後在重分佈結構102之上形成導電凸塊852。每個導電凸塊852可以電性連接到重分佈結構102的一個導電特徵106。導電凸塊852的材料和形成方法可以與第1G圖所示的導電凸塊146的材料和形成方法相同或相似。
在一些實施例中，然後執行分割製程。結果，形成多個分開的封裝結構。在第8G圖中，示出了其中一個封裝結構。
第9圖係根據本揭露一些實施例之一封裝結構的剖視圖。在一些實施例中，第9圖係示出裝置元件120附近的封裝結構的放大圖。第1至8圖中所示的其他裝置元件可以具有與第9圖所示相同或相似的結構。如第9圖所示，在一些實施例中，裝置元件120包括電極121a’和電極121b’。在一些實施例中，電極121a’和電極121b’的剖視圖具有C型輪廓，如第9圖所示。電極121a’和電極121b’可以接合到形成在重分佈結構102中的墊區域902a和墊區域902b上。在一些實施例中，形成底膠元件904以包圍及保護電極121a’和電極121b’與墊區域902a和墊區域902b之間的接點。
本揭露的實施例形成一種封裝結構，包括重分佈結構、中介層基板、以及在重分佈結構與中介層基板之間的半導體晶粒。一或多個導電特徵被佈置在重分佈結構與中介層基板之間。保護層用於包圍及保護導電特徵及半導體晶粒。多個半導體晶粒及/或裝置元件接合到重分佈結構及/或中介層基板上。信號傳輸效率被顯著提高。因此，改善了封裝結構的可靠性及性能。
根據本揭露的一些實施例，提供一種形成封裝結構的方法，包括在承載基板之上形成重分佈結構以及將半導體晶粒放置在重分佈結構之上。所述形成封裝結構的方法還包括將中介層基板堆疊在重分佈結構之上。中介層基板延伸跨越半導體晶粒的邊緣。所述形成封裝結構的方法更包括將至少一裝置元件放置在中介層基板之上。此外，所述形成封裝結構的方法還包括形成包圍半導體晶粒的保護層。
在一些實施例中，所述形成封裝結構的方法更包括將封裝模組堆疊在重分佈結構之上，其中封裝模組延伸跨越中介層基板的邊緣。在一些實施例中，保護層係在封裝模組被堆疊之後形成。在一些實施例中，中介層基板比重分佈結構包含更多的填料。在一些實施例中，所述形成封裝結構的方法更包括將第二半導體晶粒堆疊在重分佈結構之上，使得重分佈結構位於半導體晶粒與第二半導體晶粒之間。在一些實施例中，所述形成封裝結構的方法更包括形成包圍第二半導體晶粒的第二保護層，以及在第二半導體晶粒和第二保護層之上形成第二重分佈結構。在一些實施例中，中介層基板位於封裝模組的正下方。在一些實施例中，所述形成封裝結構的方法更包括在形成重分佈結構之前，在承載基板之上形成第二重分佈結構，以及在形成重分佈結構之前，將第二半導體晶粒放置在第二重分佈結構之上，以及在形成重分佈結構之後，形成包圍第二半導體晶粒的第二保護層，其中重分佈結構延伸跨越第二半導體晶粒的邊緣。在一些實施例中，所述形成封裝結構的方法更包括在將半導體晶粒放置在重分佈結構之上和將中介層基板堆疊在重分佈結構之上之前，將半導體晶粒接合到中介層基板上。在一些實施例中，所述形成封裝結構的方法更包括將第二半導體晶粒堆疊在中介層基板之上，使得中介層基板位於半導體晶粒與第二半導體晶粒之間。在一些實施例中，所述形成封裝結構的方法更包括在堆疊第二半導體晶粒之前，在中介層基板之上形成介電層，其中介電層具有基本上平坦的頂表面。在一些實施例中，所述形成封裝結構的方法更包括形成包圍第二半導體晶粒的第二保護層，以及在第二保護層和第二半導體晶粒之上形成第二重分佈結構。在一些實施例中，所述形成封裝結構的方法更包括將封裝模組堆疊在第二重分佈結構之上。在一些實施例中，封裝模組係通過導電凸塊接合到第二重分佈結構上，且所述形成封裝結構的方法更包括形成包圍導電凸塊的底膠元件。
根據本揭露的一些實施例，提供一種形成封裝結構的方法，包括將第一半導體晶粒堆疊在重分佈結構之上。所述形成封裝結構的方法還包括將中介層基板接合到重分佈結構之上。中介層基板比第一半導體晶粒寬。所述形成封裝結構的方法更包括將第二半導體晶粒堆疊在中介層基板之上。此外，所述形成封裝結構的方法還包括形成包圍第一半導體晶粒的保護層。
在一些實施例中，所述形成封裝結構的方法更包括將封裝模組接合到重分佈結構之上，其中封裝模組延伸跨越中介層基板的邊緣。在一些實施例中，保護層係在將封裝模組接合到重分佈結構之上之後形成，且保護層包圍中介層基板。
根據本揭露的一些實施例，提供一種封裝結構，包括重分佈結構、中介層基板、半導體晶粒以及保護層。中介層基板位於重分佈結構之上，且中介層基板比重分佈結構包含更多的填料。半導體晶粒位於重分佈結構與中介層基板之間。保護層包圍半導體晶粒，且保護層的一部分位於半導體晶粒與中介層基板之間。
在一些實施例中，封裝結構更包括接合到重分佈結構上的裝置元件。在一些實施例中，封裝結構更包括在中介層基板之上的第二半導體晶粒，其中中介層基板位於半導體晶粒與第二半導體晶粒之間，且保護層包圍中介層基板和第二半導體晶粒。
前面概述數個實施例之特徵，使得本技術領域中具有通常知識者可更好地理解本揭露之各方面。本技術領域中具有通常知識者應理解的是，可輕易地使用本揭露作為設計或修改其他製程以及結構的基礎，以實現在此介紹的實施例之相同目的及/或達到相同優點。本技術領域中具有通常知識者亦應理解的是，這樣的等效配置並不背離本揭露之精神以及範疇，且在不背離本揭露之精神以及範疇的情形下，可對本揭露進行各種改變、替換以及更改。
100、320、720:承載基板 101、722:離型膜 102、510、732、834:重分佈結構 104、512、734、836:絕緣層 106、116、150、304、326、332、404、428、514、522、704、728、736、810、826、838:導電特徵 108、110、126、140、312、414、516、518、532、606、616、714、746、844:導電元件 112、112’、502、504、724、820:導電柱 114、148、302、324、330、402、426、503、520、702、726、808、822:半導體晶粒 118、152、306、328、334、406、430、524、622、706、752、812、850:底膠材料 120、130、132、308、336、408、526、708、806、830:裝置元件 121a、121b、121a’、121b’:電極 122、310、602、710、802:中介層基板 124、138、314、412、530、604、614、712、744、804、842:板 128、316、418、536、608、620、716、750、814、848:導電結構 134、416、534、618、748、846:模組 136、410、528、612、742、840:互連結構 142:焊料元件 144、318、420、508、538、610、718、730、816、832:保護層 146、322、424、540、624、738、852:導電凸塊 422、740:膠帶載體 506:黏合元件 818:介電層 902a、902b:墊區域 904:底膠元件
當閱讀所附圖式時，從以下的詳細描述能最佳理解本揭露之各方面。應注意的是，各種特徵並不一定按照比例繪製。事實上，可能任意地放大或縮小各種特徵之尺寸，以做清楚的說明。 第1A至1G圖係根據本揭露一些實施例之形成一封裝結構的製程之各個階段的剖視圖。 第2圖係根據本揭露一些實施例之一封裝結構的剖視圖。 第3A至3H圖係根據本揭露一些實施例之形成一封裝結構的製程之各個階段的剖視圖。 第4A至4F圖係根據本揭露一些實施例之形成一封裝結構的製程之各個階段的剖視圖。 第5A至5F圖係根據本揭露一些實施例之形成一封裝結構的製程之各個階段的剖視圖。 第6A至6D圖係根據本揭露一些實施例之形成一封裝結構的製程之各個階段的剖視圖。 第7A至7G圖係根據本揭露一些實施例之形成一封裝結構的製程之各個階段的剖視圖。 第8A至8G圖係根據本揭露一些實施例之形成一封裝結構的製程之各個階段的剖視圖。 第9圖係根據本揭露一些實施例之一封裝結構的剖視圖。
102:重分佈結構
104:絕緣層
106、116:導電特徵
108、110、126、140:導電元件
112:導電柱
114:半導體晶粒
118:底膠材料
120、130、132:裝置元件
122:中介層基板
124、138:板
128:導電結構
134:模組
136:互連結構
142:焊料元件
144:保護層
146:導電凸塊

Claims (9)

  1. 一種形成一封裝結構的方法，包括：在一承載基板之上形成一重分佈結構；將一半導體晶粒放置在該重分佈結構之上；將一中介層基板堆疊在該重分佈結構之上，其中，該中介層基板延伸跨越該半導體晶粒的邊緣；將至少一裝置元件放置在該中介層基板之上；形成包圍該半導體晶粒的一保護層；以及將一封裝模組堆疊在該重分佈結構之上，其中該封裝模組延伸跨越該中介層基板的邊緣。
  2. 如申請專利範圍第1項所述之形成一封裝結構的方法，其中該保護層係在該封裝模組被堆疊之後形成。
  3. 如申請專利範圍第1項所述之形成一封裝結構的方法，更包括將一第二半導體晶粒堆疊在該重分佈結構之上，使得該重分佈結構位於該半導體晶粒與該第二半導體晶粒之間。
  4. 如申請專利範圍第1項所述之形成一封裝結構的方法，更包括：在形成該重分佈結構之前，在該承載基板之上形成一第二重分佈結構；在形成該重分佈結構之前，將一第二半導體晶粒放置在該第二重分佈結構之上；以及在形成該重分佈結構之後，形成包圍該第二半導體晶粒的一第二保護層，其中該重分佈結構延伸跨越該第二半導體晶粒的邊緣。
  5. 如申請專利範圍第1項所述之形成一封裝結構的方法，更包括：在 將該半導體晶粒放置在該重分佈結構之上和將該中介層基板堆疊在該重分佈結構之上之前，將該半導體晶粒接合到該中介層基板上；以及將一第二半導體晶粒堆疊在該中介層基板之上，使得該中介層基板位於該半導體晶粒與該第二半導體晶粒之間。
  6. 如申請專利範圍第5項所述之形成一封裝結構的方法，更包括在堆疊該第二半導體晶粒之前，在該中介層基板之上形成一介電層，其中該介電層具有一基本上平坦的頂表面。
  7. 一種形成一封裝結構的方法，包括：在一承載基板之上形成一重分佈結構；將一半導體晶粒接合到一中介層基板上；在該中介層基板之上形成一介電層，其中該介電層具有一基本上平坦的頂表面；將一第二半導體晶粒堆疊在該中介層基板之上；將該半導體晶粒以及該中介層基板堆疊在該重分佈結構之上，其中，該中介層基板延伸跨越該半導體晶粒的邊緣，且該中介層基板位於該半導體晶粒與該第二半導體晶粒之間；將至少一裝置元件放置在該中介層基板之上；形成包圍該半導體晶粒的一保護層；形成包圍該第二半導體晶粒的一第二保護層；在該第二保護層和該第二半導體晶粒之上形成一第二重分佈結構；以及將一封裝模組堆疊在該第二重分佈結構之上。
  8. 一種形成一封裝結構的方法，包括： 將一第一半導體晶粒堆疊在一重分佈結構之上；將一中介層基板接合到該重分佈結構之上，其中該中介層基板比該第一半導體晶粒寬；將一第二半導體晶粒堆疊在該中介層基板之上；形成包圍該第一半導體晶粒的一保護層；以及將一封裝模組堆疊在該重分佈結構之上，其中該封裝模組延伸跨越該中介層基板的邊緣。
  9. 一種封裝結構，包括：一重分佈結構；一中介層基板，位於該重分佈結構之上，其中該中介層基板比該重分佈結構包含更多的填料；一半導體晶粒，位於該重分佈結構與該中介層基板之間；一保護層，包圍該半導體晶粒，其中該保護層的一部分位於該半導體晶粒與該中介層基板之間；以及一封裝模組，位在該重分佈結構之上，其中該封裝模組延伸跨越該中介層基板的邊緣。
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