CN111755344B - 封装结构及其形成方法 - Google Patents
封装结构及其形成方法 Download PDFInfo
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- CN111755344B CN111755344B CN202010084354.4A CN202010084354A CN111755344B CN 111755344 B CN111755344 B CN 111755344B CN 202010084354 A CN202010084354 A CN 202010084354A CN 111755344 B CN111755344 B CN 111755344B
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- semiconductor die
- interposer substrate
- redistribution structure
- conductive
- forming
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- 238000000034 method Methods 0.000 title claims abstract description 187
- 239000000758 substrate Substances 0.000 claims abstract description 246
- 239000004065 semiconductor Substances 0.000 claims abstract description 206
- 239000011241 protective layer Substances 0.000 claims abstract description 100
- 239000000463 material Substances 0.000 claims description 131
- 239000010410 layer Substances 0.000 claims description 43
- 239000000945 filler Substances 0.000 claims description 12
- 238000002161 passivation Methods 0.000 claims 6
- 230000008569 process Effects 0.000 description 93
- 229910000679 solder Inorganic materials 0.000 description 34
- 238000012986 modification Methods 0.000 description 14
- 230000004048 modification Effects 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 13
- 238000007517 polishing process Methods 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 238000004806 packaging method and process Methods 0.000 description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000011218 segmentation Effects 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- 229910052719 titanium Inorganic materials 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000012778 molding material Substances 0.000 description 6
- 238000005498 polishing Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- 229910052718 tin Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000007906 compression Methods 0.000 description 5
- 238000005553 drilling Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000000835 fiber Substances 0.000 description 3
- 229920002577 polybenzoxazole Polymers 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000010200 validation analysis Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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- H01L25/0657—Stacked arrangements of devices
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
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Abstract
本公开一些实施例提供一种封装结构及一种形成封装结构的方法。所述方法包括在承载基板之上形成重分布结构以及将半导体晶粒放置在重分布结构之上。所述方法还包括将中介层基板堆叠在重分布结构之上。中介层基板延伸跨越半导体晶粒的边缘。所述方法还包括将一或多个装置元件放置在中介层基板之上。此外,所述方法还包括形成包围半导体晶粒的保护层。
Description
技术领域
本公开一些实施例涉及半导体晶粒封装技术,特别涉及半导体晶粒封装结构及其形成方法。
背景技术
半导体集成电路(integrated circuit,IC)产业已经历了快速的成长。由于半导体制造工艺技术的不断进步,产生了具有更精细特征及/或更高整合度的半导体装置。功能密度(即,每一芯片区域内互连元件的数目)通常增加,而特征尺寸(即,可以使用制造工艺产出的最小构件)则缩小。这种尺寸缩小的工艺通常通过生产效率增加及制造成本降低而提供好处。
芯片封装不仅为半导体装置提供保护以免受环境污染,也为封装在其中的半导体装置提供连接接口。已经开发出利用更少的面积或更低的高度的更小的封装结构来封装半导体装置。
已经开发了新的封装技术以进一步提高半导体晶粒(dies)的密度和功能。这些相对较新的半导体晶粒封装技术目前面对许多制造挑战。
发明内容
本公开的一些实施例提供一种形成封装结构的方法,包括在承载基板之上形成重分布结构以及将半导体晶粒放置在重分布结构之上。所述形成封装结构的方法还包括将中介层基板堆叠在重分布结构之上。中介层基板延伸跨越半导体晶粒的边缘。所述形成封装结构的方法还包括将至少一装置元件放置在中介层基板之上。此外,所述形成封装结构的方法还包括形成包围半导体晶粒的保护层。
本公开的一些实施例提供一种形成封装结构的方法,包括将第一半导体晶粒堆叠在重分布结构之上。所述形成封装结构的方法还包括将中介层基板接合到重分布结构之上。中介层基板比第一半导体晶粒宽。所述形成封装结构的方法还包括将第二半导体晶粒堆叠在中介层基板之上。此外,所述形成封装结构的方法还包括形成包围第一半导体晶粒的保护层。
本公开的一些实施例提供一种封装结构,包括重分布结构、中介层基板、半导体晶粒以及保护层。中介层基板位于重分布结构之上,且中介层基板比重分布结构包含更多的填料。半导体晶粒位于重分布结构与中介层基板之间。保护层包围半导体晶粒,且保护层的一部分位于半导体晶粒与中介层基板之间。
附图说明
当阅读说明书附图时,从以下的详细描述能最佳理解本公开的各方面。应注意的是,各种特征并不一定按照比例绘制。事实上,可能任意地放大或缩小各种特征的尺寸,以做清楚的说明。
图1A至图1G是根据本公开一些实施例的形成一封装结构的工艺的各个阶段的剖视图。
图2是根据本公开一些实施例的一封装结构的剖视图。
图3A至图3H是根据本公开一些实施例的形成一封装结构的工艺的各个阶段的剖视图。
图4A至图4F是根据本公开一些实施例的形成一封装结构的工艺的各个阶段的剖视图。
图5A至图5F是根据本公开一些实施例的形成一封装结构的工艺的各个阶段的剖视图。
图6A至图6D是根据本公开一些实施例的形成一封装结构的工艺的各个阶段的剖视图。
图7A至图7G是根据本公开一些实施例的形成一封装结构的工艺的各个阶段的剖视图。
图8A至图8G是根据本公开一些实施例的形成一封装结构的工艺的各个阶段的剖视图。
图9是根据本公开一些实施例的一封装结构的剖视图。
附图标记说明:
100、320、720~承载基板;
101、722~离型膜;
102、510、732、834~重分布结构;
104、512、734、836~绝缘层;
106、116、150、304、326、332、404、428、514、522、704、728、736、810、826、838~导电特征;
108、110、126、140、312、414、516、518、532、606、616、714、746、844~导电元件;
112、112’、502、504、724、820~导电柱;
114、148、302、324、330、402、426、503、520、702、726、808、822~半导体晶粒;
118、152、306、328、334、406、430、524、622、706、752、812、850~底胶材料;
120、130、132、308、336、408、526、708、806、830~装置元件;
121a、121b、121a’、121b’~电极;
122、310、602、710、802~中介层基板;
124、138、314、412、530、604、614、712、744、804、842~板;
128、316、418、536、608、620、716、750、814、848~导电结构;
134、416、534、618、748、846~模块;
136、410、528、612、742、840~互连结构;
142~焊料元件;
144、318、420、508、538、610、718、730、816、832~保护层;
146、322、424、540、624、738、852~导电凸块;
422、740~胶带载体;
506~黏合元件;
818~介电层;
902a、902b~垫区域;
904~底胶元件。
具体实施方式
以下的公开内容提供许多不同的实施例或范例以实施本公开的不同特征。以下描述具体的构件及其排列方式的实施例以阐述本公开。当然,这些实施例仅作为范例,而不该以此限定本公开的范围。例如,在说明书中叙述了一第一特征形成于一第二特征之上或上方,其可能包含第一特征与第二特征是直接接触的实施例,亦可能包含了有附加特征形成于第一特征与第二特征之间,而使得第一特征与第二特征可能未直接接触的实施例。另外,在本公开不同范例中可能使用重复的参考符号及/或标记,此重复为了简化与清晰的目的,并非用以限定所讨论的各个实施例及/或结构之间有特定的关系。
除此之外,所使用到的空间相关用语,例如“在…下方”、“下方”、“较低的”、“上方”、“较高的”及类似的用语,为了便于描述图示中一个元件或特征与另一个(些)元件或特征之间的关系。除了在附图中示出的方位外,这些空间相关用语意欲包含使用中或操作中的装置的不同方位。设备/装置可能被转向不同方位(旋转90度或其他方位),则在此使用的空间相关词也可依此相同解释。
说明书中的用语“基本上(substantially)”,例如“基本上平坦”或“基本上共平面”等可为本领域技术人员所能理解。在一些实施例中,形容词基本上可以被去除。在适用的情况下,用语“基本上”还可以包括“全部(entirely)”、“完全(completely)”、“所有(all)”等的实施例。在适用的情况下,用语“基本上”还可以涉及90%或更高,例如95%或更高,特别是99%或更高,包括100%。此外,例如“基本上平行”或“基本上垂直”的类的用语应解释为不排除相较于特定布置的微小偏差,并且例如可包括高达10°的偏差。用语“基本上”不排除“完全”,例如“基本上不含(substantially free)”Y的组合物可以是完全不含Y。
与特定距离或尺寸结合使用的例如“约”的用语应解释为不排除相较于特定距离或尺寸的微小偏差,并且例如可包括高达10%的偏差。相对于数值X的用语“约”可能表示X±5或10%。
以下描述本公开的一些实施例。可以在这些实施例中描述的阶段之前、之中及/或之后提供额外的操作。在不同的实施例中,可以替换或消除所述的某些阶段。可以将附加特征添加到版导体装置结构中。在不同的实施例中,可以替换或消除所述的某些特征。尽管下文中以特定顺序执行的操作来讨论一些实施例,但是也可以其他的逻辑顺序来执行这些操作。
本公开的实施例可以涉及3D封装或3D-IC装置。也可以包括其他特征或工艺。例如,可以包括测试结构以帮助对3D封装或3D-IC装置进行验证测试。测试结构可以包括例如形成在重分布层(redistribution layer)中或基板上的测试垫(pads),其允许测试3D封装或3D-IC装置、使用探针及/或探针卡等。可以对中间结构以及最终结构执行验证测试。另外,本文中公开的结构以及方法可以与结合已知良好的晶粒的中间验证的测试方法一起使用,从而提高产率并降低成本。
图1A至图1G是根据本公开一些实施例的形成一封装结构的工艺的各个阶段的剖视图。如图1A所示,根据一些实施例,在承载基板100之上形成重分布结构102。承载基板100可为玻璃基板、半导体基板或另一种合适的基板。重分布结构102可以用于布线(routing)。重分布结构102包括多个绝缘层104以及被绝缘层104包围的多个导电特征106。导电特征106可以包括导线、导电通孔(vias)及/或导电垫。在一些实施例中,一些导电通孔彼此堆叠。上方的导电通孔与下方的导电通孔基本上对准。在一些实施例中,一些导电通孔为交错排列的(staggered)通孔。上方的导电通孔与下方的导电通孔未对准。
重分布结构102还包括用于保持或接收其他元件的导电元件108和导电元件110。在一些实施例中,导电元件108和导电元件110暴露于绝缘层104的最顶表面或从绝缘层104的最顶表面突出。导电元件108可以用于保持或接收一或多个半导体晶粒。导电元件110可以用于保持或接收例如导电柱及/或导电球的导电特征。
绝缘层104可以由一或多种聚合物材料制成或包括一或多种聚合物材料。聚合物材料可以包括聚苯恶唑(polybenzoxazole,PBO)、聚酰亚胺(polyimide,PI)、环氧基树脂或上述的组合。在一些实施例中,聚合物材料是光敏性的。因此,光刻工艺可以用于在绝缘层104中形成具有期望图案的开口。
在一些其他实施例中,绝缘层104的一部分或全部由聚合物材料以外的介电质材料制成或包括介电质材料。介电质材料可以包括氧化硅、碳化硅、氮化硅、氮氧化硅、一或多种其他合适的材料或上述的组合。
导电特征106可以包括在水平方向上提供电连接的导线以及在垂直方向上提供电连接的导电通孔。导电特征106可以包括或由铜、铝、金、钴、钛、镍、银、石墨烯、一或多种其他合适的导电材料或上述的组合制成。在一些实施例中,导电特征106包括多个子层。例如,每个导电特征106包含多个子层,包括钛/铜、钛/镍/铜、钛/铜/钛、铝/钛/镍/银、其他合适的多个子层或上述的组合。
重分布结构102的形成可以涉及多个沉积或涂布工艺、多个图案化工艺及/或多个平坦化工艺。
沉积或涂布工艺可以用于形成绝缘层及/或导电层。沉积或涂布工艺可以包括旋转涂布工艺、电镀工艺、化学镀工艺(electroless process)、化学气相沉积(chemicalvapor deposition,CVD)工艺、物理气相沉积(physical vapor deposition,PVD)工艺、原子层沉积(atomic layer deposition,ALD)工艺、一或多种其他适用的工艺或上述的组合。
图案化工艺可以用于图案化形成的绝缘层及/或形成的导电层。图案化工艺可以包括光刻工艺、能量束钻孔工艺(例如,激光束钻孔工艺、离子束钻孔工艺或电子束钻孔工艺)、蚀刻工艺、机械钻孔工艺、一或多种其他适用的工艺或上述的组合。
平坦化工艺可以用于为形成的绝缘层及/或形成的导电层提供平坦的顶表面,以利于后续的工艺。平坦化工艺可以包括机械研磨工艺、化学机械研磨(chemicalmechanical polishing,CMP)工艺、一或多种其他适用的工艺或上述的组合。
之后,根据一些实施例,在重分布结构102之上形成导电柱112,如图1A所示。每个导电柱112可以电性连接到一个导电特征106。在一些实施例中,导电柱112中的一或多者具有垂直侧壁。垂直侧壁中的一者的延伸方向可以基本上垂直于重分布结构102的底表面。
导电柱112可以包括或由铜、铝、金、钴、钛、锡、一或多种其他合适的材料或上述的组合制成。可以使用电镀工艺、化学镀工艺、放置工艺(placement process)、印刷工艺、物理气相沉积(PVD)工艺、化学气相沉积(CVD)工艺、一或多种其他适用的工艺或上述的组合来形成导电柱112。
如图1B所示,根据一些实施例,半导体晶粒114堆叠在重分布结构102之上。半导体晶粒114可以包括应用处理器、电源管理集成电路、存储器装置、一或多个其他合适的电路或上述的组合。在一些实施例中,半导体晶粒114通过导电特征116接合到导电元件108上。导电特征116可以包括导电柱、焊料凸块(solder bumps)、一或多个其他合适的接合结构或上述的组合。在一些实施例中,形成底胶材料(underfill material)118以包围及保护导电特征116。
在一些实施例中,如图1B所示,在重分布结构102之上放置一或多个装置元件120。装置元件120可以接合到重分布结构102的一些导电特征106上。在一些实施例中,装置元件120通过焊料凸块、导电柱、一或多个其他合适的导电元件或上述的组合接合到重分布结构102的垫区域(由一些导电特征106构成)上。装置元件120可以包括一或多个被动元件(无源元件),例如电阻、电容、电感、一或多个其他合适的元件或上述的组合。在一些其他实施例中,装置元件120包括存储器装置。在一些实施例中,装置元件120包括电极121a及电极121b。在一些实施例中,装置元件120的电极121a及电极121b焊接到重分布结构102的垫区域上。
如图1C所示,根据一些实施例,中介层基板(interposer substrate)122堆叠在重分布结构102之上。在一些实施例中,中介层基板122延伸跨越半导体晶粒114的边缘。在一些实施例中,中介层基板122比半导体晶粒114宽。在一些实施例中,中介层基板122延伸跨越装置元件120的边缘。在一些实施例中,中介层基板122被导电柱112包围或环绕。
在一些实施例中,如图1C所示,中介层基板122通过导电结构128接合到导电元件110上。导电结构128可以包括焊料凸块、导电柱、其他合适的导电元件或上述的组合。在一些实施例中,中介层基板122与半导体晶粒114隔开一间隙,如图1C所示。
在一些实施例中,中介层基板122包括板124以及导电元件126。导电元件126可以包括或由铜、铝、钴、镍、金、银、钨、一或多种其他合适的材料或上述的组合制成。板124可以包括或由聚合物材料、陶瓷材料、金属材料、半导体材料、一或多种其他合适的材料或上述的组合制成。例如,板124包括树脂、胶片(prepreg)、玻璃及/或陶瓷。在板124由金属材料或半导体材料制成的情况下,可以在板124与导电元件126之间形成介电层以防止短路。
在板124由聚合物材料制成或包括聚合物材料的情况下,板124可以进一步包括分散在聚合物材料中的填料。聚合物材料可以包括环氧基树脂、聚酰亚胺基树脂、一或多种其他合适的聚合物材料或上述的组合。填料的范例可以包括纤维(例如,二氧化硅纤维及/或含碳纤维)、颗粒(例如,二氧化硅颗粒及/或含碳颗粒)或上述的组合。
在一些实施例中,中介层基板122比重分布结构102包含更多的填料。在一些实施例中,板124具有比重分布结构102的绝缘层104更大的填料重量百分比。在一些实施例中,重分布结构102的绝缘层104包括或由聚合物材料制成。在一些实施例中,重分布结构102的绝缘层104不包含填料。在这些情况下,重分布结构102不包含填料。
在一些实施例中,中介层基板122和承载基板100在高温下彼此挤压。结果,中介层基板122通过导电结构128接合到重分布结构102上。在一些实施例中,使用热压合工艺来实现上述接合工艺。
如图1C所示,根据一些实施例,装置元件130堆叠在重分布结构102之上。装置元件130可以电性连接到重分布结构102的一个导电特征106。装置元件130可以包括被动元件及/或存储器装置。
如图1D所示,根据一些实施例,在中介层基板122之上放置装置元件132。装置元件132可以接合或电性连接到中介层基板122的一些导电元件126。装置元件132可以包括一或多个被动元件,例如电阻、电容、电感、一或多个其他合适的元件或上述的组合。在一些其他实施例中,装置元件132包括存储器装置。一些装置元件132具有相同或相似的功能。例如,它们用作电阻或电容。一些装置元件132具有不同的功能。例如,一些装置元件132包括被动元件,而一些其他装置元件132包括存储器装置。
如图1E所示,根据一些实施例,由互连结构136承载的模块134堆叠在中介层基板122之上。在一些实施例中,模块134延伸跨越中介层基板122的边缘。在一些实施例中,互连结构136延伸跨越中介层基板122的边缘。
在一些实施例中,模块134通过导电柱112及焊料元件142接合到重分布结构102上。焊料元件142可以由含锡材料制成。含锡材料可以进一步包括铜、银、金、铝、铅、一或多种其他合适的材料或上述的组合。在一些实施例中,焊料元件142是无铅的。
在一些实施例中,模块134是具有一或多个半导体晶粒的封装模块。例如,此封装模块包括多个存储器晶粒。在一些实施例中,模块134是一半导体晶粒。例如,此半导体晶粒包括多个存储器装置。
在一些实施例中,互连结构136是承载模块134的中介层基板。在这些情况下,互连结构136具有与中介层基板122相似的结构。在一些实施例中,互连结构136包括板138以及导电元件140。板138的材料可以与中介层基板122的板124的材料相同或相似。导电元件140的材料可以与中介层基板122的导电元件126的材料相同或相似。
然而,本公开的实施例不限于此。可以对本公开的实施例进行许多变化及/或修改。在一些其他实施例中,互连结构136具有与重分布结构102相似的结构。
如图1F所示,根据一些实施例,形成保护层144以包围及保护半导体晶粒114。在一些实施例中,保护层144也包护及保护中介层基板122。在一些实施例中,保护层144还包围及保护安装在中介层基板122上的装置元件132。在一些实施例中,保护层144包围及保护导电柱112和焊料元件142。在一些实施例中,保护层144的一部分位于互连结构136与中介层基板122之间,如图1F所示。在一些实施例中,保护层144的一部分位于半导体晶粒114与中介层基板122之间。
在一些实施例中,保护层144通过底胶材料118与半导体晶粒114下方的导电特征116分离。然而,本公开的实施例不限于此。可以对本公开的实施例进行许多变化及/或修改。在一些其他实施例中,未形成底胶材料118。在这些情况下,保护层144可以与半导体晶粒114下方的导电特征116直接接触。
在一些实施例中,保护层144包括或由绝缘材料制成,例如模制材料(moldingmaterial)。模制材料可以包括聚合物材料,例如其中分散有填料的环氧基树脂。在一些实施例中,模制材料(例如,液体模制材料)被引入或注入到互连结构136与重分布结构102之间的空间中。在一些实施例中,然后使用热处理来固化液体模制材料并将其转变成保护层144。
之后,根据一些实施例,去除承载基板100以暴露出重分布结构102的表面,如图1F所示。
如图1G所示,根据一些实施例,在重分布结构102的原来由承载基板100覆盖的表面之上形成导电凸块146。每个导电凸块146可以电性连接到重分布结构102的一个导电特征106。在一些实施例中,导电凸块146是或包括例如含锡焊料凸块的焊料凸块。含锡焊料凸块可以进一步包括铜、银、金、铝、铅、一或多种其他合适的材料或上述的组合。在一些实施例中,含锡焊料凸块是无铅的。
在一些实施例中,在去除承载基板100之后,将焊球(或焊料元件)放置在暴露的导电特征106上。然后进行回焊(reflow)工艺以将焊球熔化成导电凸块146。在一些其他实施例中,在放置焊球之前,在暴露的导电特征106之上形成凸块下金属化(under bumpmetallization,UBM)元件。在一些其他实施例中,焊料元件被电镀到暴露的导电特征106上。然后使用回焊工艺将焊料元件熔化以形成导电凸块146。
如图1G所示,根据一些实施例,然后将半导体晶粒148堆叠在重分布结构102的原来由承载基板100覆盖的表面之上。半导体晶粒148可以包括应用处理器、电源管理集成电路、存储器装置、一或多个其他合适的电路或上述的组合。在一些实施例中,半导体晶粒148通过导电特征150接合到重分布结构102上。导电特征150可以包括导电柱、焊料凸块、一或多个其他合适的接合结构或上述的组合。在一些实施例中,形成底胶材料152以包围及保护导电特征150。
在一些其他实施例中,在重分布结构102的原来由承载基板100覆盖的表面之上形成一或多个其他表面安装装置(surface mounted devices)。表面安装装置可以包括被动元件及/或存储器装置。
在一些实施例中,然后执行分割(singulation)工艺。结果,形成多个分开的封装结构。在图1G中,示出了其中一个封装结构。如图1G所示,半导体晶粒114位于半导体晶粒148的正上方。半导体晶粒114和半导体晶粒148可以通过重分布结构102的一些导电特征106彼此通信。因此,RC延迟及/或信号噪声被显着降低,并且信号传输速度得到改善。
可以对本公开的实施例进行许多变化及/或修改。图2是根据一些实施例的封装结构的剖视图。在一些实施例中,半导体晶粒148未接合到重分布结构102上。
可以对本公开的实施例进行许多变化及/或修改。图3A至图3H是根据一些实施例的形成一封装结构的工艺的各个阶段的剖视图。
如图3A所示,根据一些实施例,导电柱112’形成在由承载基板100承载的重分布结构102之上(类似于图1A所示的实施例)。导电柱112’的材料和形成方法可以与图1A所示的导电柱112的材料和形成方法相同或相似。
如图3B所示,根据一些实施例,半导体晶粒302堆叠在重分布结构102之上。半导体晶粒302可以包括应用处理器、电源管理集成电路、存储器装置、一或多个其他合适的电路或上述的组合。在一些实施例中,半导体晶粒302通过导电特征304接合到导电元件108上。导电特征304可以包括导电柱、焊料凸块、一或多个其他合适的接合结构或上述的组合。在一些实施例中,形成底胶材料306以包围及保护导电特征304。
在一些实施例中,如图3B所示,在重分布结构102之上放置一或多个装置元件308。装置元件308可以接合到重分布结构102的一些导电特征106上。装置元件308可以类似于图1B所示的装置元件120。
如图3C所示,根据一些实施例,中介层基板310堆叠在重分布结构102之上。在一些实施例中,中介层基板310延伸跨越半导体晶粒302的边缘。在一些实施例中,中介层基板310比半导体晶粒302宽。在一些实施例中,中介层基板310延伸跨越装置元件308的边缘。在一些实施例中,中介层基板310延伸跨越导电柱112’的边缘。
在一些实施例中,如图3C所示,中介层基板310通过导电结构316接合到导电柱112’上。导电结构316可以包括焊料凸块、导电柱、其他合适的导电元件或上述的组合。在一些实施例中,中介层基板310与半导体晶粒302隔开一间隙,如图3C所示。
在一些实施例中,中介层基板310包括板314以及导电元件312。板314的材料可以与图1C所示的板124的材料相同或相似。导电元件312的材料可以与导电元件126的材料相同或相似。
在一些实施例中,中介层基板310和承载基板100在高温下彼此挤压。因此,中介层基板310通过导电结构316接合到重分布结构102上。在一些实施例中,使用热压合工艺来实现上述接合工艺。
如图3D所示,根据一些实施例,形成保护层318以包围及保护半导体晶粒302。在一些实施例中,保护层318位于中介层基板310与重分布结构102之间。在一些实施例中,保护层318还包围及保护安装在重分布结构102上的装置元件308。在一些实施例中,保护层318包围及保护导电柱112’和导电结构316。在一些实施例中,保护层318的一部分位于半导体晶粒302与中介层基板310之间,如图3D所示。保护层318的材料和形成方法可以与图1F所示的保护层144的材料和形成方法相同或相似。
如图3E所示,根据一些实施例,承载基板320接合到中介层基板310上。之后,如图3E所示,去除承载基板100以暴露出重分布结构102的表面。
如图3F所示,根据一些实施例,在重分布结构102的原来由承载基板100覆盖的表面之上形成导电凸块322。每个导电凸块322可以电性连接到重分布结构102的一个导电特征106。导电凸块322的材料和形成方法可以与图1G所示的导电凸块146的材料和形成方法相同或相似。
如图3F所示,根据一些实施例,然后将半导体晶粒324堆叠在重分布结构102的原来由承载基板100覆盖的表面之上。半导体晶粒324可以包括应用处理器、电源管理集成电路、存储器装置、一或多个其他合适的电路或上述的组合。在一些实施例中,半导体晶粒324通过导电特征326接合到重分布结构102上。导电特征326可以包括导电柱、焊料凸块、一或多个其他合适的接合结构或上述的组合。在一些实施例中,形成底胶材料328以包围及保护导电特征326。
在一些其他实施例中,在重分布结构102的原来由承载基板100覆盖的表面之上形成一或多个其他表面安装装置。表面安装装置可以包括被动元件及/或存储器装置。
如图3G所示,根据一些实施例,去除承载基板320以暴露出中介层基板310。在一些实施例中,在去除承载基板320之前,图3F所示的结构被贴附到胶带载体(tape carrier)上。
如图3H所示,根据一些实施例,在中介层基板310之上放置半导体晶粒330及装置元件336。半导体晶粒330可以包括应用处理器、电源管理集成电路、存储器装置、一或多个其他合适的电路或上述的组合。在一些实施例中,半导体晶粒330通过导电特征332接合到中介层基板310上。导电特征332可以包括导电柱、焊料凸块、一或多个其他合适的接合结构或上述的组合。在一些实施例中,形成底胶材料334以包围及保护导电特征332。装置元件336可以接合并电性连接到中介层基板310的一些导电元件312。装置元件336可以包括被动元件及/或存储器装置。
在一些实施例中,然后执行分割工艺。结果,形成多个分开的封装结构。之后,将封装结构从胶带载体上去除。在图3H中,示出了其中一个封装结构。
可以对本公开的实施例进行许多变化及/或修改。图4A至图4F是根据一些实施例的形成一封装结构的工艺的各个阶段的剖视图。
如图4A所示,根据一些实施例,在承载基板100之上形成重分布结构102(类似于图1A所示的实施例)。在一些实施例中,在形成重分布结构102之前,在承载基板100之上形成离型膜(release film)101。离型膜101是暂时性接合材料,其有助于承载基板100与重分布结构102之间的后续分离操作。离型膜101也可在图1A至图1G、图2和第3A至3G图所示的实施例中使用。
如图4B所示,根据一些实施例,半导体晶粒402堆叠在重分布结构102之上。半导体晶粒402可以包括应用处理器、电源管理集成电路、存储器装置、一或多个其他合适的电路或上述的组合。在一些实施例中,半导体晶粒402通过导电特征404接合到导电元件108上。导电特征404可以包括导电柱、焊料凸块、一或多个其他合适的接合结构或上述的组合。在一些实施例中,形成底胶材料406以包围及保护导电特征404。
在一些实施例中,如图4B所示,在重分布结构102之上放置一或多个装置元件408。装置元件408可以接合到重分布结构102的一些导电特征106上。装置元件408可以包括被动元件及/或存储器装置。
如图4C所示,根据一些实施例,由互连结构410承载的模块416堆叠在重分布结构102之上。在一些实施例中,模块416延伸跨越半导体晶粒402的边缘。
在一些实施例中,模块416通过导电结构418接合到重分布结构102的导电元件110上。导电结构418可以包括焊料凸块、导电柱、其他合适的导电元件或上述的组合。在一些实施例中,互连结构410与半导体晶粒402隔开一间隙,如图4C所示。
在一些实施例中,模块416是具有一或多个半导体晶粒的封装模块。例如,此封装模块包括多个存储器晶粒。在一些实施例中,模块416是一半导体晶粒。例如,此半导体晶粒包括多个存储器装置。
在一些实施例中,互连结构410是承载模块416的中介层基板。在这些情况下,互连结构410具有与图1C所示的中介层基板122相似的结构。在一些实施例中,互连结构410包括板4以及导电元件414。板412的材料可以与中介层基板122的板124的材料相同或相似。导电元件414的材料可以与中介层基板122的导电元件126的材料相同或相似。
然而,本公开的实施例不限于此。可以对本公开的实施例进行许多变化及/或修改。在一些其他实施例中,互连结构410具有与重分布结构102相似的结构。
如图4C所示,根据一些实施例,形成保护层420以包围及保护半导体晶粒402。在一些实施例中,保护层420也包围及保护安装在重分布结构102上的装置元件408。在一些实施例中,保护层420还包围及保护导电结构418。在一些实施例中,保护层420的一部分位于互连结构410与重分布结构102之间,如图4C所示。保护层420的材料和形成方法可以与图1F所示的保护层144的材料和形成方法相同或相似。
如图4D所示,根据一些实施例,图4C所示的结构被上下颠倒并贴附到胶带载体422上。之后,去除承载基板100和离型膜101以暴露出重分布结构102的表面。
如图4E所示,根据一些实施例,在重分布结构102的原来由承载基板100覆盖的表面之上形成导电凸块424。每个导电凸块424可以电性连接到重分布结构102的一个导电特征106。导电凸块424的材料和形成方法可以与图1G所示的导电凸块146的材料和形成方法相同或相似。
如图4E所示,根据一些实施例,然后将半导体晶粒426堆叠在重分布结构102的原来由承载基板100覆盖的表面之上。半导体晶粒426可以包括应用处理器、电源管理集成电路、存储器装置、一或多个其他合适的电路或上述的组合。在一些实施例中,半导体晶粒426通过导电特征428接合到重分布结构102上。导电特征428可以包括导电柱、焊料凸块、一或多个其他合适的接合元件或上述的组合。在一些实施例中,形成底胶材料430以包围及保护导电特征428。
在一些其他实施例中,在重分布结构102的原来由承载基板100覆盖的表面之上形成一或多个其他表面安装装置。表面安装装置可以包括被动元件及/或存储器装置。
在一些实施例中,然后执行分割工艺。结果,形成多个分开的封装结构。然后,将封装结构从胶带载体422上去除。在图4F中,示出了其中一个封装结构。
可以对本公开的实施例进行许多变化及/或修改。图5A至图5F是根据一些实施例的形成一封装结构的工艺的各个阶段的剖视图。
如图5A所示,提供或接收类似于图4A所示的结构。根据一些实施例,之后,导电柱502形成在重分布结构102之上。
如图5B所示,根据一些实施例,使用粘合元件506将半导体晶粒503贴附到重分布结构102上。例如,黏合元件506是晶粒贴附胶带。如图5B所示,半导体晶粒503的导电柱504面向上。半导体晶粒503可以包括应用处理器、电源管理集成电路、存储器装置、一或多个其他合适的电路或上述的组合。
之后,根据一些实施例,形成保护层508以包围及保护半导体晶粒503和导电柱502,如图5B所示。保护层508的材料和形成方法可以与图1F所示的保护层144的材料和形成方法相同或相似。在一些实施例中,在保护层508上进行平坦化工艺以部分地去除保护层508。结果,导电柱502和导电柱504的顶表面被暴露(如图5B所示)。在一些实施例中,保护层508的顶表面与导电柱502和导电柱504的顶表面基本上齐平。平坦化工艺可以包括机械研磨工艺、化学机械研磨(CMP)工艺、蚀刻工艺、干式研磨工艺、一或多种其他适用的工艺或上述的组合。
如图5C所示,根据一些实施例,在保护层508之上形成重分布结构510。类似于图1A所示的重分布结构102,重分布结构510包括多个绝缘层512、导电特征514以及导电元件516和导电元件518。重分布结构510的材料和形成方法可以与图1A所示的重分布结构102的材料和形成方法相同或相似。
如图5D所示,根据一些实施例,半导体晶粒520堆叠在重分布结构510之上。在一些实施例中,半导体晶粒520通过导电特征522接合到导电元件516上。在一些实施例中,形成底胶材料524以包围及保护导电特征522。在一些实施例中,如图5B所示,在重分布结构510之上放置一或多个装置元件526。装置元件526可以接合到重分布结构510的一些导电特征514上。装置元件526可以包括被动元件及/或存储器装置。
如图5E所示,根据一些实施例,由互连结构528承载的模块534堆叠在重分布结构510之上。在一些实施例中,模块534延伸跨越半导体晶粒520的边缘。
在一些实施例中,模块534通过导电结构536接合到重分布结构510的导电元件518上。导电结构536可以包括焊料凸块、导电柱、其他合适的导电元件或上述的组合。在一些实施例中,互连结构528与半导体晶粒520隔开一间隙,如图5E所示。
在一些实施例中,模块534是具有一或多个半导体晶粒的封装模块。例如,此封装模块包括多个存储器晶粒。在一些实施例中,模块534是一半导体晶粒。例如,此半导体晶粒包括多个存储器装置。
在一些实施例中,互连结构528是承载模块534的中介层基板。在这些情况下,互连结构528具有与图1C所示的中介层基板122相似的结构。在一些实施例中,互连结构528包括板530以及导电元件532。板530的材料可以与中介层基板122的板124的材料相同或相似。导电元件532的材料可以与中介层基板122的导电元件126的材料相同或相似。
然而,本公开的实施例不限于此。可以对本公开的实施例进行许多变化及/或修改。在一些其他实施例中,互连结构528具有与重分布结构510相似的结构。
之后,根据一些实施例,形成保护层538以包围及保护半导体晶粒520,如图5E所示。在一些实施例中,保护层538也包围及保护安装在重分布结构510上的装置元件526。在一些实施例中,保护层538还包围及保护导电结构536。在一些实施例中,保护层538的一部分位于互连结构528与重分布结构510之间,如图5E所示。保护层538的材料和形成方法可以与图1F所示的保护层144的材料和形成方法相同或相似。
如图5F所示,根据一些实施例,去除承载基板100和离型膜101以暴露出重分布结构102的表面。之后,根据一些实施例,在重分布结构102的原来由承载基板100覆盖的表面之上形成导电凸块540,如图5F所示。每个导电凸块540可以电性连接到重分布结构102的一个导电特征106。导电凸块540的材料和形成方法可以与图1G所示的导电凸块146的材料和形成方法相同或相似。
在一些实施例中,然后执行分割工艺。结果,形成多个分开的封装结构。在图5F中,示出了其中一个封装结构。
可以对本公开的实施例进行许多变化及/或修改。图6A至图6D是根据一些实施例的形成一封装结构的工艺的各个阶段的剖视图。如图6A所示,根据一些实施例,提供或接收类似于图5D所示的结构。
如图6B所示,根据一些实施例,中介层基板602堆叠在重分布结构510之上。在一些实施例中,中介层基板602延伸跨越半导体晶粒520的边缘。在一些实施例中,中介层基板602比半导体晶粒520宽。在一些实施例中,中介层基板602延伸跨越装置元件526的边缘。
在一些实施例中,如图6B所示,中介层基板602通过导电结构608接合到导电元件518上。导电结构608可以包括焊料凸块、导电柱、其他合适的导电元件或上述的组合。在一些实施例中,中介层基板602与半导体晶粒520隔开一间隙,如图6B所示。
在一些实施例中,中介层基板602包括板604以及导电元件606。板604的材料可以与图1C所示的板124的材料相同或相似。导电元件606的材料可以与导电元件126的材料相同或相似。
在一些实施例中,中介层基板602与承载基板100在高温下彼此挤压。结果,中介层基板602通过导电结构608接合到重分布结构510上。在一些实施例中,使用热压合工艺来实现上述接合工艺。
如图6B所示,根据一些实施例,形成保护层610以包围及保护半导体晶粒520。在一些实施例中,保护层610位于中介层基板602与重分布结构510之间。在一些实施例中,保护层610还包围及保护安装在重分布结构510上的装置元件526。在一些实施例中,保护层610包围及保护导电元件518和导电结构608。在一些实施例中,保护层610的一部分位于半导体晶粒520与中介层基板602之间,如图6B所示。保护层610的材料和形成方法可以与图1F所示的保护层144的材料和形成方法相同或相似。
如图6C所示,根据一些实施例,由互连结构612承载的模块618堆叠在中介层基板602之上。在一些实施例中,模块618通过导电结构620接合到中介层基板602的导电元件606上。导电结构620可以包括焊料凸块、导电柱、其他合适的导电元件或上述的组合。在一些实施例中,互连结构612与中介层基板602隔开一间隙,如图6C所示。在一些实施例中,形成底胶材料622以填充间隙并保护导电结构620。
在一些实施例中,模块618是具有一或多个半导体晶粒的封装模块。例如,此封装模块包括多个存储器晶粒。在一些实施例中,模块618是一半导体晶粒。例如,此半导体晶粒包括多个存储器装置。
在一些实施例中,互连结构612是承载模块618的中介层基板。在这些情况下,互连结构612具有与图1C所示的中介层基板122相似的结构。在一些实施例中,互连结构612包括板614以及导电元件616。板614的材料可以与中介层基板122的板124的材料相同或相似。导电元件616的材料可以与中介层基板122的导电元件126的材料相同或相似。
然而,本公开的实施例不限于此。可以对本公开的实施例进行许多变化及/或修改。在一些其他实施例中,互连结构612具有与重分布结构102相似的结构。
如图6D所示,根据一些实施例,去除承载基板100和离型膜101以暴露出重分布结构102的表面。之后,根据一些实施例,在重分布结构102的原来由承载基板100覆盖的表面之上形成导电凸块624,如图6D所示。每个导电凸块624可以电性连接到重分布结构102的一个导电特征106。导电凸块624的材料和形成方法可以与图1G所示的导电凸块146的材料和形成方法相同或相似。
在一些实施例中,然后执行分割工艺。结果,形成多个分开的封装结构。在图6D中,示出了其中一个封装结构。
可以对本公开的实施例进行许多变化及/或修改。图7A至图7G是根据一些实施例的形成一封装结构的工艺的各个阶段的剖视图。
如图7A所示,提供或接收类似于图4A所示的结构。之后,根据一些实施例,半导体晶粒702以及装置元件708堆叠在重分布结构102之上。在一些实施例中,半导体晶粒702通过导电特征704接合到重分布结构102的导电元件108上。在一些实施例中,形成底胶材料706以包围及保护导电特征704。装置元件708可以包括被动元件及/或存储器装置。
如图7B所示,根据一些实施例,中介层基板710堆叠在重分布结构102之上。在一些实施例中,中介层基板710延伸跨越半导体晶粒702的边缘。在一些实施例中,中介层基板710比半导体晶粒702宽。在一些实施例中,中介层基板710延伸跨越装置元件708的边缘。
在一些实施例中,如图7B所示,中介层基板710通过导电结构716接合到导电元件110上。导电结构716可以包括焊料凸块、导电柱、其他合适的导电元件或上述的组合。在一些实施例中,中介层基板710与半导体晶粒702隔开一间隙,如图7B所示。
在一些实施例中,中介层基板710包括板712以及导电元件714。板712的材料可以与图1C所示的板124的材料相同或相似。导电元件714可以与导电元件126的材料相同或相似。
在一些实施例中,中介层基板710与承载基板100在高温下彼此挤压。因此,中介层基板710通过导电结构716接合到重分布结构102上。在一些实施例中,使用热压合工艺来实现上述接合工艺。
如图7B所示,根据一些实施例,形成保护层718以包围及保护半导体晶粒702。在一些实施例中,保护层718位于中介层基板710与重分布结构102之间。在一些实施例中,保护层718还包围及保护安装在重分布结构102上的装置元件708。在一些实施例中,保护层718包围及保护导电结构716。在一些实施例中,保护层718的一部分位于半导体晶粒702与中介层基板710之间,如图7B所示。保护层718的材料和形成方法可以与图1F所示的保护层144的材料和形成方法相同或相似。
如图7C所示,根据一些实施例,图7B所示的结构被上下颠倒并通过离型膜722贴附到承载基板720上。之后,去除承载基板100和离型膜101。结果,重分布结构102的原来由承载基板100覆盖的表面被暴露(如图7C所示)。
如图7D所示,根据一些实施例,在重分布结构102之上形成导电柱724。每个导电柱724电性连接到重分布结构102的一个导电特征106。导电柱724的材料和形成方法可以与图1A所示的导电柱112的材料和形成方法相同或相似。在一些实施例中,在形成导电柱724之前,使用图案化工艺在重分布结构102中形成开口以暴露一些导电特征106。
之后,根据一些实施例,半导体晶粒726堆叠在重分布结构102之上,如图7D所示。在一些实施例中,半导体晶粒726通过导电特征728接合到重分布结构102上。每个导电特征728可以电性连接到重分布结构102的一个导电特征106。在一些实施例中,如图7D所示,导电柱724的高度高于半导体晶粒726的高度。
如图7E所示,根据一些实施例,形成保护层730以包围及保护半导体晶粒726和导电柱724。保护层730的材料和形成方法可以与图1F所示的保护层144的材料和形成方法相同或相似。在一些实施例中,使用平坦化工艺来使保护层730变薄。结果,保护层730具有基本上平坦的顶表面,其有助于后续的工艺。在一些实施例中,保护层730的顶表面与导电柱724的顶表面基本上齐平。平坦化工艺可以包括机械研磨工艺、化学机械研磨(CMP)工艺、蚀刻工艺、干式研磨工艺、一或多种其他适用的工艺或上述的组合。
之后,根据一些实施例,在保护层730之上形成重分布结构732,如图7E所示。类似于图1A所示的重分布结构102,重分布结构732包括多个绝缘层734以及导电特征736。重分布结构732的材料和形成方法可以与图1A所示的重分布结构102的材料和形成方法相同或相似。
如图7F所示,根据一些实施例,在重分布结构732之上形成导电凸块738。每个导电凸块738可以电性连接到重分布结构732的一个导电特征736。导电凸块738的材料和形成方法可以与图1G所示的导电凸块146的材料和形成方法相同或相似。
如图7G所示,根据一些实施例,图7F所示的结构被上下颠倒并贴附到胶带载体740上。之后,去除承载基板720和离型膜722。结果,中介层基板710的原来由承载基板720覆盖的表面被暴露(如图7G所示)。
之后,根据一些实施例,由互连结构742承载的模块748堆叠在中介层基板710之上,如图7G所示。在一些实施例中,模块748通过导电结构750接合到中介层基板710上。导电结构750可以包括焊料凸块、导电柱、其他合适的导电元件或上述的组合。在一些实施例中,互连结构742与中介层基板710隔开一间隙,如图7G所示。在一些实施例中,形成底胶材料752以填充间隙并保护导电结构750。
在一些实施例中,模块748是具有一或多个半导体晶粒的封装模块。例如,此封装模块包括多个存储器晶粒。在一些实施例中,模块748是一半导体晶粒。例如,此半导体晶粒包括多个存储器装置。
在一些实施例中,互连结构742是承载模块748的中介层基板。在这些情况下,互连结构742具有与图1C所示的中介层基板122相似的结构。在一些实施例中,互连结构742包括板744以及导电元件746。板744的材料可以与中介层基板122的板124的材料相同或相似。导电元件746的材料可以与中介层基板122的导电元件126的材料相同或相似。
然而,本公开的实施例不限于此。可以对本公开的实施例进行许多变化及/或修改。在一些其他实施例中,互连结构742具有与重分布结构102相似的结构。
在一些实施例中,然后执行分割工艺。结果,形成多个分开的封装结构。之后,将封装结构从胶带载体上去除。
可以对本公开的实施例进行许多变化及/或修改。图8A至图8G是根据本公开一些实施例的形成一封装结构的工艺的各个阶段的剖视图。如图8A所示,类似于图7A所示的实施例,在承载基板100之上形成重分布结构102。重分布结构102与承载基板100之间的离型膜101用于促进承载基板100与重分布结构102之间的后续分离工艺。
如图8B所示,根据一些实施例,中介层基板802堆叠在重分布结构102之上。在一些实施例中,在堆叠中介层基板802之前,半导体晶粒808通过导电特征810接合到中介层基板802上。形成底胶材料812以包围及保护导电特征810。在中介层基板802的堆叠期间,半导体晶粒808被布置在重分布结构102之上并且位于中介层基板802与重分布结构102之间。在一些实施例中,中介层基板802延伸跨越半导体晶粒808的边缘。在一些实施例中,中介层基板802比半导体晶粒808宽。
在一些实施例中,如图8B所示,中介层基板802通过导电结构814接合到重分布结构102上。导电结构814可以包括焊料凸块、导电柱、其他合适的导电元件或上述的组合。每个导电结构814可以电性连接到重分布结构102的一个导电特征106。在一些实施例中,在中介层基板802接合到重分布结构102上之后,半导体晶粒808与重分布结构102隔开一间隙,如图8B所示。
在一些实施例中,中介层基板802包括板8以及导电元件806。板804的材料可以与图1C所示的板124的材料相同或相似。导电元件806的材料可以与导电材料126的材料相同或相似。
在一些实施例中,中介层基板802与承载基板100在高温下彼此挤压。结果,中介层基板802通过导电结构814接合到重分布结构102上。在一些实施例中,使用热压合工艺来实现上述接合工艺。
如图8B所示,根据一些实施例,形成保护层816以包围及保护半导体晶粒808。在一些实施例中,保护层816位于中介层基板802与重分布结构102之间。在一些实施例中,保护层816包围及保护导电结构814。在一些实施例中,保护层816的一部分位于半导体晶粒808与重分布结构102之间,如图8B所示。保护层816的材料和形成方法可以与图1F所示的保护层144的材料和形成方法相同或相似。
之后,根据一些实施例,在中介层基板802之上形成介电层818,如图8B所示。介电层818可以包括或由聚合物材料制成。聚合物材料可以包括聚酰亚胺、聚苯恶唑、一或多种其他合适的材料或上述的组合。或者,介电层818可以包括或由氧化硅、氮化硅、氮氧化硅、碳化硅、一或多种其他合适的材料或上述的组合。可以使用旋转涂布工艺、喷洒涂布工艺、化学气相沉积(CVD)工艺、层压工艺、一或多种其他适用的工艺或上述的组合来形成介电层818。
在一些实施例中,在介电层818上进行平坦化工艺。结果,介电层818具有基本上平坦的顶表面,其有助于后续的工艺。平坦化工艺可以包括机械研磨工艺、化学机械研磨(CMP)工艺、蚀刻工艺、干式研磨工艺、一或多种其他适用的工艺或上述的组合。
如图8C所示,根据一些实施例,导电柱820形成在中介层基板802之上。每个导电柱820电性连接到中介层基板802的一个导电元件806。导电柱820的材料和形成方法可以与图1A所示的导电柱112的材料和形成方法相同或相似。在一些实施例中,在形成导电柱820之前,使用图案化工艺在介电层818中形成开口以暴露中介层基板802的一个导电元件806。一些暴露的导电元件806是用于保持导电柱820。一些暴露的导电元件806可以用于保持随后堆叠的半导体晶粒及/或随后堆叠的装置元件。
之后,根据一些实施例,半导体晶粒822堆叠在中介层基板802之上,如图8C所示。在一些实施例中,半导体晶粒822通过导电特征826接合到中介层基板802上。每个导电特征826可以电性连接到中介层基板802的一个导电元件806。在一些实施例中,导电柱820的高度高于半导体晶粒822的高度,如图8C所示。在一些实施例中,装置元件830接合到中介层基板802上。装置元件830可以包括一或多个被动元件及/或一或多个存储器装置。
如图8D所示,根据一些实施例,形成保护层832以包围及保护半导体晶粒822、装置元件830以及导电柱820。保护层832的材料和形成方法可以与图1F所示的保护层144的材料和形成方法相同或相似。在一些实施例中,使用平坦化工艺来使保护层832变薄。结果,保护层832具有基本上平坦的顶表面,其有助于后续的工艺。在一些实施例中,保护层832的顶表面与导电柱820的顶表面基本上齐平。平坦化工艺可以包括机械研磨工艺、化学机械研磨(CMP)工艺、蚀刻工艺、干式研磨工艺、一或多种其他适用的工艺或上述的组合。
如图8E所示,根据一些实施例,在保护层832及导电柱820之上形成重分布结构834。类似于图1所示的重分布结构102,重分布结构834包括多个绝缘层836以及导电特征838。重分布结构834的材料和形成方法可以与图1A所示的重分布结构102的材料和形成方法相同或相似。
如图8F所示,根据一些实施例,由互连结构840承载的模块846堆叠在重分布结构834之上。在一些实施例中,模块846通过导电结构848接合到重分布结构834上。导电结构848可以包括焊料凸块、导电柱、其他合适的导电元件或上述的组合。在一些实施例中,互连结构840与重分布结构834隔开一间隙,如图8F所示。在一些实施例中,形成底胶材料850以填充间隙并保护导电结构848。
在一些实施例中,模块846是具有一或多个半导体晶粒的封装模块。例如,此封装模块包括多个存储器晶粒。在一些实施例中,模块846是一半导体晶粒。例如,此半导体晶粒包括多个存储器装置。
在一些实施例中,互连结构840是承载模块846的中介层基板。在这些情况下,互连结构840具有与图1C所示的中介层基板122相似的结构。在一些实施例中,互连结构840包括板842以及导电元件844。板842的材料可以与中介层基板122的板124的材料相同或相似。导电元件844的材料可以与中介层基板122的导电元件126的材料相同或相似。
然而,本公开的实施例不限于此。可以对本公开的实施例进行许多变化及/或修改。在一些其他实施例中,互连结构840具有与重分布结构102相似的结构。
如图8G所示,根据一些实施例,去除承载基板100和离型膜101,然后在重分布结构102之上形成导电凸块852。每个导电凸块852可以电性连接到重分布结构102的一个导电特征106。导电凸块852的材料和形成方法可以与图1G所示的导电凸块146的材料和形成方法相同或相似。
在一些实施例中,然后执行分割工艺。结果,形成多个分开的封装结构。在图8G中,示出了其中一个封装结构。
图9是根据本公开一些实施例的一封装结构的剖视图。在一些实施例中,图9是示出装置元件120附近的封装结构的放大图。第1至8图中所示的其他装置元件可以具有与图9所示相同或相似的结构。如图9所示,在一些实施例中,装置元件120包括电极121a’和电极121b’。在一些实施例中,电极121a’和电极121b’的剖视图具有C型轮廓,如图9所示。电极121a’和电极121b’可以接合到形成在重分布结构102中的垫区域902a和垫区域902b上。在一些实施例中,形成底胶元件904以包围及保护电极121a’和电极121b’与垫区域902a和垫区域902b之间的接点。
本公开的实施例形成一种封装结构,包括重分布结构、中介层基板、以及在重分布结构与中介层基板之间的半导体晶粒。一或多个导电特征被布置在重分布结构与中介层基板之间。保护层用于包围及保护导电特征及半导体晶粒。多个半导体晶粒及/或装置元件接合到重分布结构及/或中介层基板上。信号传输效率被显着提高。因此,改善了封装结构的可靠性及性能。
根据本公开的一些实施例,提供一种形成封装结构的方法,包括在承载基板之上形成重分布结构以及将半导体晶粒放置在重分布结构之上。所述形成封装结构的方法还包括将中介层基板堆叠在重分布结构之上。中介层基板延伸跨越半导体晶粒的边缘。所述形成封装结构的方法还包括将至少一装置元件放置在中介层基板之上。此外,所述形成封装结构的方法还包括形成包围半导体晶粒的保护层。
在一些实施例中,所述形成封装结构的方法还包括将封装模块堆叠在重分布结构之上,其中封装模块延伸跨越中介层基板的边缘。在一些实施例中,保护层是在封装模块被堆叠之后形成。在一些实施例中,中介层基板比重分布结构包含更多的填料。在一些实施例中,所述形成封装结构的方法还包括将第二半导体晶粒堆叠在重分布结构之上,使得重分布结构位于半导体晶粒与第二半导体晶粒之间。在一些实施例中,所述形成封装结构的方法还包括形成包围第二半导体晶粒的第二保护层,以及在第二半导体晶粒和第二保护层之上形成第二重分布结构。在一些实施例中,中介层基板位于封装模块的正下方。在一些实施例中,所述形成封装结构的方法还包括在形成重分布结构之前,在承载基板之上形成第二重分布结构,以及在形成重分布结构之前,将第二半导体晶粒放置在第二重分布结构之上,以及在形成重分布结构之后,形成包围第二半导体晶粒的第二保护层,其中重分布结构延伸跨越第二半导体晶粒的边缘。在一些实施例中,所述形成封装结构的方法还包括在将半导体晶粒放置在重分布结构之上和将中介层基板堆叠在重分布结构之上之前,将半导体晶粒接合到中介层基板上。在一些实施例中,所述形成封装结构的方法还包括将第二半导体晶粒堆叠在中介层基板之上,使得中介层基板位于半导体晶粒与第二半导体晶粒之间。在一些实施例中,所述形成封装结构的方法还包括在堆叠第二半导体晶粒之前,在中介层基板之上形成介电层,其中介电层具有基本上平坦的顶表面。在一些实施例中,所述形成封装结构的方法还包括形成包围第二半导体晶粒的第二保护层,以及在第二保护层和第二半导体晶粒之上形成第二重分布结构。在一些实施例中,所述形成封装结构的方法还包括将封装模块堆叠在第二重分布结构之上。在一些实施例中,封装模块是通过导电凸块接合到第二重分布结构上,且所述形成封装结构的方法还包括形成包围导电凸块的底胶元件。
根据本公开的一些实施例,提供一种形成封装结构的方法,包括将第一半导体晶粒堆叠在重分布结构之上。所述形成封装结构的方法还包括将中介层基板接合到重分布结构之上。中介层基板比第一半导体晶粒宽。所述形成封装结构的方法还包括将第二半导体晶粒堆叠在中介层基板之上。此外,所述形成封装结构的方法还包括形成包围第一半导体晶粒的保护层。
在一些实施例中,所述形成封装结构的方法还包括将封装模块接合到重分布结构之上,其中封装模块延伸跨越中介层基板的边缘。在一些实施例中,保护层是在将封装模块接合到重分布结构之上之后形成,且保护层包围中介层基板。
根据本公开的一些实施例,提供一种封装结构,包括重分布结构、中介层基板、半导体晶粒以及保护层。中介层基板位于重分布结构之上,且中介层基板比重分布结构包含更多的填料。半导体晶粒位于重分布结构与中介层基板之间。保护层包围半导体晶粒,且保护层的一部分位于半导体晶粒与中介层基板之间。
在一些实施例中,封装结构还包括接合到重分布结构上的装置元件。在一些实施例中,封装结构还包括在中介层基板之上的第二半导体晶粒,其中中介层基板位于半导体晶粒与第二半导体晶粒之间,且保护层包围中介层基板和第二半导体晶粒。
前面概述数个实施例的特征,使得本技术领域中技术人员可更好地理解本公开的各方面。本技术领域中技术人员应理解的是,可轻易地使用本公开作为设计或修改其他工艺以及结构的基础,以实现在此介绍的实施例的相同目的及/或达到相同优点。本技术领域中技术人员亦应理解的是,这样的等效配置并不背离本公开的构思以及范围,且在不背离本公开的构思以及范围的情形下,可对本公开进行各种改变、替换以及更改。
Claims (15)
1.一种形成一封装结构的方法,包括:
在一承载基板之上形成一第一重分布结构;
将一第一半导体晶粒及至少一导电结构放置在一中介层基板的一第一侧上;
随后将该中介层基板堆叠在该承载基板之上的该第一重分布结构之上,使得该第一半导体晶粒及该至少一导电结构位于该中介层基板与该第一重分布结构之间,其中该至少一导电结构将该中介层基板电性连接到该第一重分布结构,且其中该中介层基板延伸跨越该第一半导体晶粒的边缘,且该第一半导体晶粒是在将该中介层基板堆叠在该第一重分布结构之上之前就设置在该中介层基板上,且在该中介层基板通过该至少一导电结构接合到该第一重分布结构上之后,该第一半导体晶粒与该第一重分布结构隔开一间隙并且彼此电性隔绝;
将至少一装置元件放置在该中介层基板之上;
形成包围该第一半导体晶粒与该至少一导电结构的一第一保护层,其中该第一保护层是在该中介层基板通过该至少一导电结构电性连接到该第一重分布结构之后才形成,且其中该第一保护层的一部分位于该第一半导体晶粒与该第一重分布结构之间的该间隙中;
形成一第二保护层,以包围该至少一装置元件;以及
在该第二保护层之上形成一第二重分布结构,其中该至少一装置元件与第二重分布结构被该第二保护层分隔开。
2.如权利要求1所述的形成一封装结构的方法,还包括将一封装模块堆叠在该第一重分布结构之上,其中该封装模块延伸跨越该中介层基板的边缘。
3.如权利要求2所述的形成一封装结构的方法,其中该第一保护层是在该封装模块被堆叠之前形成。
4.如权利要求1所述的形成一封装结构的方法,其中该中介层基板比该第一重分布结构包含更多的填料。
5.如权利要求1所述的形成一封装结构的方法,还包括将一第二半导体晶粒堆叠在该第一重分布结构之上,使得该第一半导体晶粒位于该第一重分布结构与该第二半导体晶粒之间,其中该第二半导体晶粒与该至少一装置元件位于该中介层基板的一第二侧上,该第二侧与该中介层基板的该第一侧相对。
6.如权利要求1所述的形成一封装结构的方法,其中该中介层基板位于一封装模块的正下方。
7.如权利要求1所述的形成一封装结构的方法,还包括将一第二半导体晶粒堆叠在该中介层基板之上,使得该中介层基板位于该第一半导体晶粒与该第二半导体晶粒之间。
8.如权利要求7所述的形成一封装结构的方法,还包括在堆叠该第二半导体晶粒之前,在该中介层基板之上形成一介电层,其中该介电层具有一平坦的顶表面。
9.如权利要求7所述的形成一封装结构的方法,还包括:
在该中介层基板之上形成多个导电柱,其中该些导电柱的高度高于该第二半导体晶粒的高度;
形成包围该第二半导体晶粒与该些导电柱的一第二保护层;以及
在该第二保护层和该第二半导体晶粒之上形成一第二重分布结构,其中该第二重分布结构通过该些导电柱接合到该中介层基板上。
10.如权利要求9所述的形成一封装结构的方法,还包括将一封装模块堆叠在该第二重分布结构之上。
11.如权利要求10所述的形成一封装结构的方法,其中该封装模块是通过多个导电凸块接合到该第二重分布结构上,且该形成一封装结构的方法还包括形成包围该些导电凸块的一底胶元件。
12.一种形成一封装结构的方法,包括:
将一第一半导体晶粒堆叠在一重分布结构之上,且在该重分布结构之上形成多个导电柱;
将一中介层基板接合到该重分布结构之上,其中该第一半导体晶粒位于该重分布结构与该中介层基板之间并与该中介层基板隔开一间隙,该中介层基板比该第一半导体晶粒宽,且该中介层基板被该些导电柱包围,一第一导电特征直接连接该重分布结构以及该第一半导体晶粒,且该第一导电特征被一第一底胶材料围绕;
将至少一装置元件放置堆叠在该中介层基板之上,其中该中介层基板位于该至少一装置元件与该第一半导体晶粒之间;
将一封装模块通过该些导电柱接合到该重分布结构之上,其中该封装模块延伸跨越该中介层基板的边缘;
形成包围该第一半导体晶粒的一保护层,其中该保护层的一部分位于该第一半导体晶粒与该中介层基板之间的该间隙中;以及
将一第二半导体晶粒叠置在该重分布结构之上,使得该重分布结构位于该第一半导体晶粒与该第二半导体晶粒之间,且该第二半导体晶粒从该封装结构露出,其中一第二导电特征直接连接该重分布结构以及该第二半导体晶粒,该第二导电特征被一第二底胶材料围绕,该第一导电特征以及该第二导电特征位于该第一半导体晶粒与该第二半导体晶粒之间,该第一导电特征、以及该第二导电特征分別直接接触该重分布结构的两个相反的表面,该第一底胶材料、该第二底胶材料分別直接接触该重分布结构的两个相反的表面,且该第一半导体晶粒与该第二半导体晶粒直接通过该重分布结构、该第一导电特征、以及该第二导电特征彼此通信。
13.如权利要求12所述的形成一封装结构的方法,其中该保护层是在将该封装模块接合到该重分布结构之上之后形成,且该保护层包围该中介层基板、该至少一装置元件及该些导电柱。
14.一种封装结构,包括:
一重分布结构;
一中介层基板,位于且接合到该重分布结构之上,其中该中介层基板比该重分布结构包含更多的填料;
一第一半导体晶粒,位于该重分布结构与该中介层基板之间,其中该中介层基板延伸跨越该第一半导体晶粒的边缘,其中该第一半导体晶粒与该中介层基板隔开一间隙;
一第一导电特征,直接连接该重分布结构以及该第一半导体晶粒;
一第一底胶材料,围绕该第一导电特征;
至少一装置元件,位于该中介层基板上;
多个导电柱,形成在该重分布结构上且包围该中介层基板;
一封装模块,通过该些导电柱接合到该重分布结构之上;
一保护层,位于该封装模块与该重分布结构之间以包围该中介层基板、该第一半导体晶粒、该至少一装置元件以及该些导电柱,其中该保护层的一部分位于该第一半导体晶粒与该中介层基板之间的该间隙中;
一第二半导体晶粒,位于该重分布结构之上,从该封装结构露出;
一第二导电特征,直接连接该重分布结构以及该第二半导体晶粒,其中该第一导电特征以及该第二导电特征皆位于该第一半导体晶粒与该第二半导体晶粒之间;以及
一第二底胶材料,围绕该第二导电特征,其中该第一底胶材料、该第二底胶材料分別直接接触该重分布结构的两个相反的表面;
其中该第二半导体晶粒与该第一半导体晶粒位于该重分布结构的相反侧上,且该第一半导体晶粒与该第二半导体晶粒直接通过该重分布结构、该第一导电特征、以及该第二导电特征彼此通信。
15.如权利要求14所述的封装结构,其中该些导电柱的高度高于该中介层基板的高度。
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