CN104253058A - 在扇出型wlcsp上堆叠半导体小片的方法及半导体装置 - Google Patents

在扇出型wlcsp上堆叠半导体小片的方法及半导体装置 Download PDF

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CN104253058A
CN104253058A CN201410299294.2A CN201410299294A CN104253058A CN 104253058 A CN104253058 A CN 104253058A CN 201410299294 A CN201410299294 A CN 201410299294A CN 104253058 A CN104253058 A CN 104253058A
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semiconductor chip
semiconductor
conductive layer
interconnection structure
middle section
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CN104253058B (zh
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包旭升
司徒国强
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

半导体装置具有第一半导体小片。第一互连结构，诸如导电柱，其包括形成在导电柱之上的凸点，以及第二互连结构形成在所述第一半导体小片的外围区域。第二半导体小片布置在第一互连结构和第二互连结构之间的第一半导体小片之上。第二半导体小片的高度低于第一互连结构的高度。第二半导体小片的占用空间小于第一半导体小片的中央区域。密封体沉积在第一半导体小片和第二半导体小片之上。备选地，第二半导体小片布置在包括多个互连结构的半导体封装之上。实现来自单侧FO-WLCSP的外部连通性而没有使用导电通孔以提供高的产量及装置可靠性。

Description

在扇出型WLCSP上堆叠半导体小片的方法及半导体装置
本申请要求于2013年6月28日递交的美国临时专利申请No.61/841,059的权益，通过引用将其申请结合于此。
技术领域
本发明一般涉及半导体装置，并且更具体地涉及堆叠半导体小片(die)或使用单侧扇出型晶圆级芯片规模封装(FO-WLCSP)的半导体封装的半导体装置及方法。
背景技术
半导体装置广泛存在于现代电子产品中。半导体装置在电元件的数量和密度上变化。离散的半导体装置通常包含一种类型的电元件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器和功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体装置典型地包含数以百计到数百万的电元件。集成半导体装置的示例包括微控制器、微处理器、电荷-耦合装置(CCD)、太阳能电池和数字式微-反射镜装置(DMD)。
半导体装置执行广泛范围的功能，诸如信号处理、高速计算、发射及接收电磁信号、控制电子装置、将太阳光转变为电以及产生用于电视显示器的视觉投影。半导体装置存在于娱乐、通信、功率转换、网络、计算机以及消费产品的领域中。半导体装置也存在于军事应用、航空、汽车、工业控制器以及办公设备中。
半导体装置利用半导体材料的电属性。半导体材料的结构允许通过电场或基极电流的应用或经由掺杂的过程来操纵半导体材料的电导率。掺杂将杂质引入半导体材料以操纵并控制半导体装置的导电性。
半导体装置包含有源的和无源的电结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变掺杂的水平以及电场或基极电流的应用，晶体管或是促进或是限制电流的流动。包括电阻器、电容器和电感器的无源结构产生执行多种电功能所必需的、电压和电流之间的关系。将无源及有源结构电连接以形成电路，该电路使得半导体装置能够执行高速操作和其他有用的功能。
半导体装置一般使用两种复杂的制造工艺(即前端制造和后端制造)来制造，每一制造工艺潜在地包括数以百计的步骤。前端制造包括在半导体晶圆表面上的多个小片的形成。每一半导体小片典型地是相同的并且包含由电连接的有源和无源元件形成的电路。后端制造包括从已完成的晶圆分割个体半导体小片并且封装小片以提供结构的支持和环境隔离。本文使用的术语“半导体小片”既指该单词的单一形式又指其复数形式，并且因而能够既指单个半导体装置又指多个半导体装置。
半导体制造的一个目的是生产较小的半导体装置。较小的半导体装置典型地消耗较少功率、具有较高性能并且能够更有效地生产。另外，较小的半导体装置具有较少的占用空间，这是较小的最终产品所期望的。能够通过前端工艺中的改进来实现较小的半导体小片尺寸，这导致具有较小、较高密度有源及无源元件的半导体小片。后端工艺可通过电互连和封装材料中的改进而导致具有较少占用空间的半导体装置封装。
较小半导体装置的制造依赖于对在多个水平上(3-D装置集成)的多个半导体装置之间的水平的及垂直的电互连实施改进。水平的电互连包括形成为FO-WLCSP或嵌入式晶圆级球栅阵列(eWLB)的部分的重新分配层(RDLs)，其提供半导体小片和封装外部的点之间的电连接。垂直的互连能够以导电的直通硅通孔(TSV)或直通孔通孔(THV)实现。然而，TSV和THV的使用通常涉及相当多的时间及设备，这减少了每小时件数(UPH)产量并且增加了成本。而且，通孔形成可能包括空隙的形成，该空隙减少装置可靠性，并且可能提出半导体小片放置精度和翘曲控制的问题。
发明内容
存在着以某种方式增加半导体小片封装的密度来实现较低的成本、较高的UPH产量并且增加的装置可靠性的需求。因而，在一种实施例中，本发明是制作半导体装置的方法，其包括如下步骤：提供第一半导体小片，在所述第一半导体小片的外围区域形成多个互连结构，并且将第二半导体小片布置在所述互连结构之间的所述第一半导体小片之上。
在另一实施例中，本发明是制作半导体装置的方法，其包括如下步骤：提供第一半导体小片，形成第一互连结构和第二互连结构，并且将第二半导体小片布置在所述第一互连结构和所述第二互连结构之间的所述第一半导体小片之上。
在另一实施例中，本发明是半导体装置，其包括第一半导体小片。第一互连结构和第二互连结构形成在所述第一半导体小片的外围区域中。第二半导体小片布置在所述第一互连结构和所述第二互连结构之间的所述第一半导体小片之上。
在另一实施例中，本发明是半导体装置，其包括第一半导体小片。第一互连结构和第二互连结构形成在所述第一半导体小片之上。第二半导体小片布置在所述第一互连结构和所述第二互连结构之间的所述第一半导体小片之上。
附图说明
图1示出印刷电路板(PCB)，其具有装配在PCB表面的不同类型的封装；
图2a-2l示出半导体晶圆，其具有由切割道(saw street)分开的多个半导体小片；
图3a-3c以平面图示出图2a-2l的半导体小片；
图4a-4f示出半导体晶圆，其具有由切割道分开的多个半导体小片；
图5a-5i示出堆叠使用单侧FO-WLCSP的图2a-2l和图4a-4f的半导体小片的过程；以及
图6a-6g示出堆叠具有使用单侧FO-WLCSP的图4a-4f的半导体小片的半导体封装的过程。
具体实施方式
在下面的说明中参考附图在一个或多个实施例中描述本发明，其中相似的数字表示相同或类似的元件。尽管按照实现本发明目的的最佳模式描述本发明，本领域技术人员将理解说明书意在覆盖备选方案、修正方案以及等价方案，正如它们可包括在由附随的权利要求以及由下列公开和附图所支持的权利要求的等价方案所限定的、本发明的精神和范围内。
半导体装置一般使用两种复杂的制造工艺来制造：前端制造和后端制造。前端制造包括在半导体晶圆表面上的多个小片的形成。晶圆上的每一半导体小片包含有源和无源电元件，该些电元件电连接以形成功能的电路。诸如晶体管和二极管的有源电元件具有控制电流流动的能力。诸如电容器、电感器和电阻器的无源电元件产生执行电路功能所必需的、电压和电流之间的关系。
无源及有源元件通过一系列工艺步骤(包括掺杂、沉积、光刻、刻蚀和平坦化)形成在半导体晶圆的表面上。掺杂通过诸如离子注入或热扩散的技术将杂质引入半导体材料中。掺杂工艺通过响应电场或基极电流而动态地改变半导体材料导电性来修正有源装置中半导体材料的电导率。晶体管包含变化的掺杂类型和程度的区域，这些区域根据需要布置为使得晶体管能够在施加电场或基极电流时促进或限制电流的流动。
有源和无源的元件由具有不同电属性的材料的层来形成。这些层能够由多种沉积技术形成，这些沉积技术部分地由被沉积材料的类型确定。例如，薄膜沉积能够包括化学气相沉积(CVD)、物理气相沉积(PVD)、电解电镀和非电镀工艺。通常对每一层图案化以形成有源元件、无源元件或元件之间电连接的部分。
后端制造指将已完成的晶圆切割或分割成个体半导体小片并且随后封装该半导体小片来用于结构支撑和环境隔离。为分割半导体小片，沿着晶圆的非功能区(称为切割道或划痕)对晶圆进行刻划并且割裂。使用激光切割工具或锯条分割晶圆。在分割后，将个体半导体小片装配到包括引脚或接触焊盘的封装衬底以供与其他系统元件的互连。形成在半导体小片上的接触焊盘随后连接到封装内的接触焊盘。电连接能够以焊料凸点、钉头凸点(stud bump)、导电胶或丝焊(wirebond)来制作。在封装之上沉积密封材料或其他成型材料以提供物理支撑和电隔离。所完成的封装随后插入到电系统中并且半导体装置的功能性对于其他系统元件变得可用。
图1示出具有芯片载体衬底或PCB52的电子装置50，多个半导体封装装配在PCB52的表面。电子装置50能够具有一种类型的半导体封装或多种类型的半导体封装，这取决于应用。
电子装置50能够为单独(stand-alone)系统，其使用半导体封装来执行一个或多个电功能。备选地，电子装置50能够为较大系统的次级元件。例如，电子装置50能够为蜂窝电话、个人数字助手(PDA)、数字式视频相机(DVC)或其他电子通信装置的部分。备选地，电子装置50能够为可插入计算机中的显卡、网络接口卡或其他信号处理卡。半导体封装能够包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、射频(RF)电路、分离装置或其他半导体小片或电子元件。小型化和重量减轻对于将被市场接受的产品而言是至关重要的。可减少半导体装置之间的距离以实现更高密度。
图1中，PCB52提供通用衬底用于装配在PCB上的半导体封装的结构支撑和电互连。导电信号迹线54使用蒸发、电解电镀、非电镀、丝网印刷或其他适当的金属沉积工艺形成在PCB52的表面上或在PCB52的层内。信号迹线54为半导体封装、装配的元件以及其他外部系统元件的每个之间的电通信作准备。迹线54也向半导体封装的每个提供功率和地连接。
在一些实施例中，半导体装置具有两个封装级。第一级封装是用于机械地并且电气地将半导体小片附着到中间载体的技术。第二级封装包括机械地并且电气地将中间载体附着到PCB。在其他实施例中，半导体装置可仅具有第一级封装，其中小片机械地并且电气地直接装配到PCB。
为了例示的目的，在PCB52上示出几种类型的第一级封装，包括接合线(bond wire)封装56和倒装芯片(flipchip)58。此外，几种类型的第二级封装，包括球栅阵列(BGA)60、凸点芯片载体(BCC)62、栅格阵列(LGA)66、多芯片模块(MCM)68、扁平无引线封装(QFN)70、扁平封装72、eWLB74和晶圆级芯片规模封装(WLCSP)76被示出装配在PCB52上。eWLB74为扇出型晶圆级封装并且WLCSP76为扇入型晶圆级封装(FI-WLP)。取决于系统需求，以第一和第二级封装式样的任何组合配置的半导体封装以及其他电子元件的任何组合能够连接到PCB52。一些实施例中，电子装置50包括单个附着的半导体封装，而其他实施例要求多个互连的封装。通过在单个衬底上组合一个或多个半导体封装，厂商能够将预先制造的元件结合到电子装置和系统中。由于半导体封装包括成熟的功能性，电子装置能够使用较不昂贵的元件以及高效率的制造工艺来制造。所产生的装置较少可能地失效并且制造较不昂贵，这导致消费者较低的费用。
图2a-2i，相对于图1，示出形成减薄的半导体小片的工艺，在半导体小片的外围区域具有复合的互连结构。RDL将来自半导体小片中央区域中的电路的信号发送到该半导体小片的外围区域。在一个实施例中，半导体小片的中央区域的一部分没有复合的互连结构以在后续的处理步骤中容纳布置在该半导体小片之上的较小的半导体小片。在另一实施例中，复合互连结构的行可将中央区域划分成较小区域来容纳将多于一个的较小半导体小片堆叠在该半导体小片之上。
图2a示出半导体晶圆120，其具有基础衬底材料122，诸如硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟或碳化硅或其他用于结构支撑的大块半导体材料。在一个实施例中，半导体晶圆120具有100-450mm的宽度或直径。多个半导体小片或元件124形成在由如上所述的非有源的、交互-小片晶圆区域或切割道126所分隔的晶圆120上。切割道126提供切割区域以将半导体晶圆120分割成个体半导体小片124。每一半导体小片124具有中央区域128和外围区域130。在一个实施例中，中央区域128具有正方形或矩形形状。
图2b示出半导体晶圆120的一部分的截面图。每一半导体小片124具有背部或非有源表面132以及包含模拟或数字电路的有源表面134，该些模拟或数字电路实现为形成在小片中并且根据小片的电设计和功能而电互连的有源装置、无源装置、导电层以及介电层。例如，电路可包括一个或多个晶体管、二极管和其他形成在有源表面134内的电路元件以实现模拟电路或数字电路，诸如数字信号处理器(DSP)、ASIC、存储器或其他信号处理电路。半导体小片124还可包含集成的无源装置(IPD)，诸如电感器、电容器和电阻器，以供射频信号处理。
导电层136使用PVD、CVD、电解电镀、非电镀工艺或其他适合的金属沉积工艺形成在有源表面134上。导电层136能够为铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Cu)、银(Ag)或其他适合的导电材料的一层或多层。导电层136作为电连接到有源表面134上的电路的接触焊盘进行操作。导电层136能够形成为在距离半导体小片124的边缘第一距离处并肩布置的接触焊盘，如图2b所示。备选地，导电层136能够形成为接触焊盘，该些接触焊盘成多行错位(offset)以使得接触焊盘的第一行在距离小片边缘第一距离处布置，而与该第一行交错的、接触焊盘的第二行在距离小片边缘第二距离处布置。
绝缘或钝化层138使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化形成在有源表面134和导电层136上。绝缘层138包含二氧化硅(SiO2)、氮化硅(Si3N4)、氧氮化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)或其他具有类似绝缘和结构属性的材料的一层或多层。绝缘层138覆盖有源表面134并且为其提供保护。通过刻蚀、激光直接烧蚀(LDA)、或其他适合的工艺来移除绝缘层138的一部分来暴露导电层136以用于后来的电互连。
图2c中，半导体晶圆120经历作为质量控制工艺部分的电测试及检查。人工视觉检查及自动光学系统用于对半导体晶圆120执行检查。能够在半导体晶圆120的自动化光学分析中使用软件。视觉检查方法可以使用诸如扫描电子显微镜、高亮度的光或紫外线、或金相显微镜的设备。检查半导体晶圆120的结构特性，包括：翘曲、厚度变化、表面微粒、不规则性、裂缝、层离以及污染(discoloration)。
半导体小片124内的有源和无源元件在晶圆级经历测试以获得电性能和电路功能。使用包括多个探针或测试导线140、或其他测试装置的测试探头142，来测试每一半导体小片124以获得功能性和电参数，如图2c所示。探针140用于与每一半导体小片124上的节点或接触焊盘136进行电接触并且提供对接触焊盘的电激励。半导体小片124响应该电激励，该电激励由计算机测试系统144测量并且与期望的响应进行比较以测试半导体小片的功能性。电测试可包括电路功能性、导线完整性、电阻系数、连续性、可靠性、结深、ESD、射频性能、驱动电流、阈值电流、漏电流以及对于元件类型特定的操作的参数。半导体晶圆120的检查和电测试使得通过测试的半导体小片124被指派为用于在半导体封装中使用的确优小片(KGD)。
在图2d中，导电(electrically conductive)层或RDL150使用PVD、CVD、电解电镀、非电镀工艺或其他适合的金属沉积工艺形成在导电(conductive)层136和绝缘层138之上。导电层150能够为Al、Ti、TiW、Cu、Sn、Ni、Au、Ag或其他适合的导电材料的一层或多层。导电层150的一部分与导电层136电连接。导电层150的其他部分能够为电共用的或电隔离的，这取决于半导体小片124的设计和功能。RDL150将离开半导体小片124的中央区域128中接触焊盘136的信号发送到该半导体小片的外围区域130。在一个实施例中，半导体小片124是任何库存的或早先设计的半导体小片。半导体小片124在中央区域128具有信号和接触焊盘136。半导体小片124的中央区域128的一部分必须没有封装互连以容纳与较小半导体小片的堆叠。通过将离开中央区域128的信号发送到外围区域130，导电层150使得半导体小片124能够容纳与较小半导体小片的堆叠而不需半导体小片的定制或重新设计，这节约了大量时间和费用并且扩展了早先设计的半导体小片124的效用。
绝缘或钝化层152使用PVD、CVD、印刷、层叠(lamination)、旋涂、喷涂、烧结或热氧化形成在绝缘层138和导电层150上。绝缘层152包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或其他具有类似绝缘和结构属性的材料的一层或多层。绝缘层152的一部分通过LDA、刻蚀或其他适合的工艺移除以暴露导电层150。导电层150将离开半导体小片124的中央区域128中接触焊盘136的信号发送到该半导体小片的外围区域130。因而，暴露导电层150的、绝缘层152中的开口位于半导体小片124的外围区域130。在半导体小片124的中央区域128的一部分中的导电层150保持由绝缘层152覆盖。保持由绝缘层152覆盖的、半导体小片124的中央区域128的该部分对应于将在后来的处理步骤中布置于半导体小片124之上的较小半导体小片的占用空间。
图2e中，图案化或光刻胶层154使用印刷、旋涂或喷涂形成在导电层150和绝缘层152之上。在一个实施例中，光刻胶层154具有40-150微米(μm)的厚度。光刻胶层154的一部分使用激光156通过LDA移除以形成图案化的开口158并且暴露导电层150和绝缘层152。备选地，光刻胶层154的该部分通过图案化的光刻胶层由刻蚀工艺移除以形成图案化的开口158并且暴露导电层150和绝缘层152。导电层150将离开半导体小片124的中央区域128中接触焊盘136的信号发送到该半导体小片的外围区域130。因而，暴露导电层150和绝缘层152的、光刻胶层154中的图案化的开口158位于半导体小片124的外围区域130。半导体小片124的中央区域128的一部分保持由光刻胶层154覆盖。半导体小片124的中央区域128的一部分没有光刻胶层154中的图案化的开口158。保持由光刻胶层154覆盖的、半导体小片124的中央区域128的该部分对应于将在后来的处理步骤中布置于半导体小片124之上的、较小半导体小片的占用空间。在一个实施例中，图案化的开口158具有圆形的横截面，其配置为形成具有包括圆形横截面的圆柱形形状的导电柱。在另一实施例中，图案化的开口158具有矩形横截面，其配置为形成具有包括矩形横截面的立方体形状的导电柱。
在图2f中，在开口158内，导电层160使用图案化和金属沉积工艺(诸如印刷、PVD、CVD、溅射、电解电镀和非电镀)共形地(conformally)施加在导电层150和绝缘层152之上。光刻胶层154中图案化的开口158位于半导体小片124的外围区域130。因而，布置在图案化的开口158中的导电层160位于半导体小片124的外围区域130。半导体小片124的中央区域128的一部分保持由光刻胶层154覆盖。半导体小片124的中央区域128的一部分没有导电层160。保持由光刻胶层154覆盖并且没有导电层160的、半导体小片124的中央区域128的该部分对应于将在后来的处理步骤中布置于半导体小片124之上的、较小半导体小片的占用空间。导电层160能够为Al、Cu、Sn、Ti、Ni、Au、Ag或其他适合的导电材料的一层或多层。在一个实施例中，导电层160为包括种子层、阻挡层和粘附层的多层堆叠。种子层能够为钛铜(TiCu)、钛钨铜(TiWCu)或钽氮铜(TaNCu)。阻挡层能够为Ni、镍钒(NiV)、铂(Pt)、钯(Pd)、TiW、CrCu或其他适合的材料。粘附层能够为Ti、TiN、TiW、Al或铬(Cr)或其他适合的材料。导电层160跟随导电层150和绝缘层152的轮廓。导电层160电连接到导电层150。
在图2g中，导电材料162使用蒸发、溅射、电解电镀、非电镀或丝网印刷工艺沉积在图案化的开口158内和在导电层160之上。导电材料162能够为Cu、Al、钨(W)、Au、焊料或其他合适的导电材料。在一个实施例中，导电材料162通过电镀铜沉积在光刻胶层154的图案化的开口158中。光刻胶层154的图案化的开口158位于半导体小片124的外围区域130。因而，布置在图案化的开口158中的导电材料162位于半导体小片124的外围区域130中。半导体小片124的中央区域128的一部分保持由光刻胶层154覆盖。半导体小片124的中央区域128的一部分没有导电材料162。保持由光刻胶层154覆盖并且没有导电材料162的、半导体小片124的中央区域128的该部分对应于将在后来的处理步骤中布置于半导体小片124之上的、较小半导体小片的占用空间。导电材料162电连接到导电层160。
在图2h中，光刻胶层154通过刻蚀工艺来移除以留下个体导电柱164。导电柱164能够具有圆形或椭圆形横截面的圆柱形形状，或导电柱164能够具有矩形横截面的立方体形状。导电柱164具有H1的高度。在一个实施例中，导电柱164能够以堆叠的凸点或钉头凸点来实现。在另一实施例中，导电柱164的高度H1为40-150μm。导电材料162沉积在位于半导体小片124的外围区域130的图案化的开口158中。因而，导电柱164位于半导体小片124的外围区域130中。半导体小片124的中央区域128的一部分没有导电柱164。半导体小片124的中央区域128的一部分保持由绝缘层152覆盖。保持由绝缘层152覆盖并且没有导电柱164的、半导体小片124的中央区域128的该部分对应于将在后来的处理步骤中布置于半导体小片124之上的、较小半导体小片的占用空间。导电柱164电连接到导电层160。
在图2i中，导电凸点材料(bump material)使用蒸发、电解电镀、非电镀、落球(ball drop)或丝网印刷工艺沉积在导电柱164之上。凸点材料能够为带有可选的焊剂溶液的、Al、Sn、Ni、Au、Ag、Pb、铋(Bi)、Cu、焊料和它们的组合。例如，凸点材料能够为易熔的Sn/Pb、高铅焊料或无铅焊料。凸点材料能够回流以形成圆形的凸帽166。在一些应用中，凸帽166被再次回流以改善对柱体164的电接触。备选地，凸点材料在移除光刻胶层154之前沉积。导电柱164和凸帽166的组合组成了复合互连结构168，其具有非熔部分(导电柱164)和可熔部分(凸帽166)。凸帽166电连接到导电柱164。导电柱164位于半导体小片124的外围区域130中。因而，复合互连结构168位于半导体小片124的外围区域130中。半导体小片124的中央区域128的一部分没有复合互连结构168。半导体小片124的中央区域128的一部分保持由绝缘层152覆盖。保持由绝缘层152覆盖并且没有复合互连结构168的、半导体小片124的中央区域128的该部分对应于将在后来的处理步骤中布置于半导体小片124之上的、较小半导体小片的占用空间。复合互连结构168具有高度H2。在一个实施例中，复合互连结构168的高度H2为40-150μm。复合互连结构168表示能在半导体小片124之上形成的、互连结构的一种类型。该互连结构还能够使用凸点、导电胶、堆叠的钉头凸点或其他电互连。复合互连结构168电连接到导电层160。
在图2j中，保护层170跨半导体晶圆120的整个区域形成在绝缘层152和复合互连结构168之上。保护层170能够为通过丝网印刷、旋涂、喷涂或其他合适的沉积工艺施加的、可溶于水的聚合物材料的一层或多层。层叠带(lamination tape)172跨半导体晶圆120的整个区域施加在保护层170之上。在一个实施例中，层叠带172包括介电的基膜172a和粘附层172b，如图2j中半导体晶圆120的一部分的横截面视图中所示。保护层170覆盖半导体晶圆120的有源表面134，该半导体晶圆包括半导体小片124的中央区域128和外围区域130以及切割道126。
半导体晶圆120具有T1的初始厚度。在图2k中，半导体晶圆120的背面132经以研磨机174或其他合适的机械或刻蚀工艺进行的背部研磨操作，以移除基材122的一部分并且将基材减少到厚度T2，厚度T2小于厚度T1。基材122从背面132的移除作为机械工艺或物理刻蚀工艺来执行，这使得半导体晶圆120的新的背面176跨半导体晶圆的整个宽度而均匀。备选地，基材122的一部分通过LDA从背面132移除以暴露新的背面176。在一个实施例中，半导体晶圆120在背部研磨或晶圆减薄操作之后具有30-50μm的厚度T2。在另一实施例中，半导体晶圆120在背部研磨或晶圆减薄操作之后具有大约100μm的厚度T2。绝缘层152和复合互连结构168之上的保护层170在背部研磨或晶圆减薄操作、以及后来的制造工艺期间减少在有源表面134上的切口移位以及碎屑和污染物的积聚。因而，保护层170在图2k的背部研磨或晶圆减薄操作之前施加在绝缘层152和复合互连结构168之上。
在图2l中，绝缘层152和复合互连结构168之上的保护层170通过剥离或剥除操作来移除。使用锯条或激光切割工具180经由切割道126来将半导体晶圆120分隔成个体半导体小片182，该个体半导体小片182包括在外围区域130中的复合互连结构168。半导体小片182经由接触焊盘136电连接到导电层150。导电层150将离开半导体小片182的中央区域128中的接触焊盘136的信号发送到该半导体小片的外围区域130。半导体小片182的导电层150电连接到导电层160。导电层160位于半导体小片182的外围区域130。半导体小片182的导电层160电连接到导电柱164。导电柱164位于半导体小片182的外围区域130中。半导体小片182的导电柱164电连接到凸帽166。凸帽166位于半导体小片182的外围区域130中。导电柱164和凸帽166的组合组成了复合互连结构168，其具有非熔部分(导电柱164)和可熔部分(凸帽166)。复合互连结构168电连接到导电层160。半导体小片182的中央区域128的一部分没有复合互连结构168。没有导电互连结构168的、半导体小片182的中央区域128的该部分对应于将在后来的处理步骤中布置于半导体小片182之上的、较小半导体小片的占用空间。半导体小片182经由接触焊盘136、导电层150和导电层160电连接到复合互连结构168以供外部互连。能够对个体半导体小片182进行检查和电测试以用于KGD后分割的识别。
图3a-3c，相对于图1，示出图2a-2l中描述的半导体小片的平面图，其示出复合互连结构处于外围区域以及中央区域没有复合互连结构的实施例。图3a示出具有形成在外围区域130中的复合互连结构168的半导体小片182的平面图。图3a示出没有复合互连结构168的半导体小片182的中央区域128。图3b示出复合互连结构168的一列或多列，该一列或多列将半导体小片182的中央区域128划分成第一区域128a和第二区域128b。图3c示出复合互连结构168的一行或多行，该一行或多行将半导体小片128的第一区域128a划分成区域128c和区域128d并且将第二区域128b划分成区域128e和区域128f。半导体小片128的区域128a-128f的一部分没有复合互连结构168以容纳在后来的处理步骤中布置于该半导体小片之上的较小半导体小片。没有复合互连结构168的、半导体小片182的区域128a-128f的该部分对应于将在后来的处理步骤中布置于半导体小片182之上的较小半导体小片的占用空间。
图4a-4f，相对于图1，示出形成减薄的半导体小片的工艺，该减薄的半导体小片的占用空间比半导体小片182的中央区域128更小。图4a示出与半导体晶圆120相似的半导体晶圆190，其具有基础衬底材料192，诸如硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟、碳化硅或其他用于结构支撑的大块半导体材料。多个半导体小片或元件194形成在由以上描述的非有源、交互-小片晶圆区域或切割道196所分隔的晶圆190之上。切割道196提供切割区域以将半导体晶圆190分割成个体半导体小片194。在一个实施例中，半导体晶圆190具有100-450nm的宽度或直径。半导体小片194的占用空间比半导体小片182的中央区域128更小。半导体小片182的中央区域128比半导体小片182的占用空间更大。
图4b示出半导体晶圆190的一部分的横截面视图。半导体晶圆190具有T3的初始厚度。每一半导体小片194具有背面或非有源表面198以及包含模拟或数字电路的有源表面200，该些模拟或数字电路实现为形成在小片中并且根据小片的电设计和功能而电互连的有源装置、无源装置、导电层以及介电层。例如，电路可包括一个或多个晶体管、二极管和其他形成在有源表面200内的电路元件以实现模拟电路或数字电路，诸如DSP、ASIC、存储器或其他信号处理电路。半导体小片194还可包含诸如电感器、电容器和电阻器的IPD，以供射频信号处理。
导电层202使用PVD、CVD、电解电镀、非电镀工艺或其他适合的金属沉积工艺形成在有源表面200之上。导电层202能够为Al、Cu、Sn、Ni、Au、Ag或其他适合的导电材料的一层或多层。导电层202作为电连接到有源表面200上的电路的接触焊盘来进行操作。导电层202能够形成为在距离半导体小片194的边缘第一距离处并肩布置的接触焊盘，如图4b所示。备选地，导电层202能够形成为接触焊盘，该些接触焊盘成多行错位(offset)以使得接触焊盘的第一行在距离小片边缘第一距离处布置，而与该第一行交错(alternating)的、接触焊盘的第二行在距离小片边缘第二距离处布置。
绝缘或钝化层204使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化形成在有源表面200和导电层202之上。绝缘层204包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或其他具有类似绝缘和结构属性的材料的一层或多层。绝缘层204覆盖有源表面200并且提供对有源表面200的保护。绝缘层204的一部分通过刻蚀、LDA或其他适合的工艺来移除以暴露导电层202用于后来的电互连。
在图4c中，半导体晶圆190经历作为质量控制工艺部分的电测试及检查。人工视觉检查及自动光学系统用于对半导体晶圆190执行检查。能够在半导体晶圆190的自动化光学分析中使用软件。视觉检查方法可以使用诸如扫描电子显微镜、高亮度光或紫外线、或金相显微镜的设备。检查半导体晶圆190的结构特性，包括：翘曲、厚度变化、表面微粒、不规则性、裂缝、层离以及污染(discoloration)。
半导体小片194内的有源和无源元件在晶圆级经历测试以获得电性能和电路功能。使用探针或其他测试装置来测试每一半导体小片194以获得功能性和电参数。测试探头212包括多个探针210。探针210用于与每一半导体小片194上的接触焊盘202进行电接触并且提供对接触焊盘的电激励。半导体小片194响应该电激励，该电激励由计算机测试系统214测量并且与期望的响应进行比较以测试半导体小片的功能性。电测试可包括电路功能性、导线完整性、电阻系数、连续性、可靠性、结深、ESD、射频性能、驱动电流、阈值电流、漏电流以及对于元件类型特定的操作的参数。半导体晶圆190的检查和电测试使得通过测试的半导体小片194被指派为用于在半导体封装中使用的KGD。
在图4d中，导电凸点材料(bump material)使用蒸发、电解电镀、非电镀、落球(ball drop)或丝网印刷工艺沉积在接触焊盘202之上。凸点材料能够为带有可选的焊剂溶液的、Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料和它们的组合。例如，凸点材料能够为易熔的Sn/Pb、高铅焊料或无铅焊料。凸点材料使用合适的粘附或接合工艺接合到接触焊盘202。在一个实施例中，通过将凸点材料加热到其熔点之上来回流该凸点材料以形成球体或凸点216。在一些应用中，凸点216被再次回流以改善对接触焊盘202的电接触。凸点216也能够被压接或热压接到接触焊盘202。凸点216表示能够在接触焊盘202之上形成的互连结构的一种类型。互连结构也能够使用钉头凸点、微凸点或其他电互连。凸点216电连接到半导体小片194的接触焊盘202。
在图4e中，保护层220跨半导体晶圆190的整个区域形成在绝缘层204和凸点216之上。保护层220能够为通过丝网印刷、旋涂、喷涂或其他合适的沉积工艺施加的、可溶于水的聚合物材料的一层或多层。层叠带(lamination tape)222跨半导体晶圆190的整个区域施加在保护层220之上。在一个实施例中，层叠带222包括介电的基膜222a和粘附层222b，如图4e中半导体晶圆190的一部分的横截面视图中所示。
在图4e中，半导体晶圆190的背面198经以研磨机224或其他合适的机械或刻蚀工艺进行的背部研磨操作，以移除基材192的一部分并且将基材减少到厚度T4，厚度T4小于厚度T3。基材192从背面198的移除作为机械工艺或物理刻蚀工艺来执行，这使得半导体晶圆190的新的背面226跨半导体晶圆的整个宽度而均匀。备选地，基材192的一部分通过LDA从背面198移除以暴露新的背面226。在一个实施例中，半导体晶圆190在背部研磨或晶圆减薄操作之后具有30-50μm的厚度T4。在另一实施例中，半导体晶圆120在背部研磨或晶圆减薄操作之后具有大约100μm的厚度T4。在背部研磨或晶圆减薄操作之后的半导体晶圆190的厚度T4小于半导体小片182的复合互连结构168的高度H2。绝缘层204和凸点216之上的保护层220在背部研磨或晶圆减薄操作、以及后来的制造工艺期间减少在有源表面200上的切口移位以及碎屑和污染物的积聚。因而，保护层220在图4e的背部研磨或晶圆减薄操作之前施加在绝缘层204和凸点216之上。
在图4f中，绝缘层204和凸点216之上的保护层220通过剥离或剥除操作来移除。使用锯条或激光切割工具228经由切割道196来将半导体晶圆190分割成个体的凸起半导体小片230。半导体小片230经由接触焊盘202电连接到凸点216以供外部互连。半导体小片230具有厚度T4，其小于半导体小片182的复合互连结构168的高度H2。半导体小片182的复合互连结构168的高度H2大于半导体小片230的厚度T4。半导体小片230的占用空间小于半导体小片182的中央区域128。半导体小片230(其厚度T4小于半导体小片182的复合互连结构168的高度H2并且其占用空间小于半导体小片182的中央区域128)将适合在半导体小片182的中央区域128之下。半导体小片182在后续处理步骤中布置在半导体小片230之上。能够对半导体小片230进行检查以及电测试以用于KGD后分割的识别。
图5a-5i，相对于图1，示出以堆叠的减薄的半导体小片形成单侧FO-WLCSP的工艺。图5a示出衬底或载体240，其包含临时的或牺牲的基材，诸如硅、聚合物、氧化铍、玻璃或其他用于结构支撑的、适合的低成本的刚性材料。接口层或双面带(double-sided tape)242作为临时的粘附接合膜、刻蚀停止层或热释放层形成在载体240之上。
在图5b中，使用例如将有源表面200向载体定向的拾取和放置(pick and place)操作将来自图4f的半导体小片230装配到载体240和接口层242上。半导体小片230具有厚度T4，其小于半导体小片182的复合互连结构168的高度H2。半导体小片230的占用空间小于半导体小片182的中央区域128。
在放置来自图4f的半导体小片230之后，使用例如将有源表面134向载体定向的拾取和放置(pick and place)操作将来自图2l的半导体小片182装配到载体240和半导体小片230之上的接口层242，如图5c所示。半导体小片230具有厚度T4，其小于半导体小片182的复合互连结构168的高度H2。半导体小片230具有比半导体小片182的中央区域128更少的占用空间。因而，半导体小片230布置在半导体小片182的中央区域128之上。半导体小片182的中央区域128的一部分没有复合互连结构168以容纳布置在半导体小片182之上的较小半导体小片230。没有复合互连结构168的、半导体小片182的中央区域128的该部分对应于布置在半导体小片182之上的较小半导体小片230的占用空间。半导体小片230布置在半导体小片182的中央区域128和载体240之间。半导体小片182的有源表面134向半导体小片230的背面226定向。复合互连结构168定位在半导体小片182的外围区域130以提供半导体小片182到单侧FO-WLCSP的连通性，而没有使用TSV或THV。因而，单侧FO-WLCSP能够通过消除TSV和THV而达到较低的成本、较高的UPH产量以及增强的装置可靠性。半导体小片182的复合互连结构168环绕或包围半导体小片230。半导体小片230布置在半导体小片182的复合互连结构168之间。复合互连结构168具有高度H2，其大于减薄的半导体小片230的厚度T4。图5d示出装配到载体240的接口层242的半导体小片182和230，作为重组的或重新装配的晶圆244。
在图5e中，密封体或模塑料250使用膏印刷(paste printing)、压缩成型、传递模塑、液体密封成型、真空层叠(vacuum lamination)或其他适合的敷料器(applicator)沉积在半导体小片182、半导体小片230和载体240之上。密封体250能够为聚合物复合材料，诸如具有填充物的环氧树脂、具有填充物的环氧丙烯酸脂或具有适当填充物的聚合物。密封体250不导电并且在环境上保护半导体装置免受外部元件和污染物的影响。在一个实施例中，密封体250使用薄膜辅助成型工艺来沉积。密封体250的表面246可能经历可选的研磨操作来平坦化表面并且减少密封体的厚度。对密封体250的表面246进行研磨以减少密封体的厚度减少了最终半导体装置的总体厚度，从而使得最终的半导体装置能够在需要减少的厚度的应用中得到利用。减少最终半导体装置的厚度增加了对该最终半导体装置的市场需求。
在图5f中，载体240和接口层242通过化学刻蚀、机械剥离、CMP、机械研磨、热烘焙、UV光、激光扫描或湿法剥除来移除。将载体240和接口层242移除暴露出密封体250、半导体小片230的有源表面200和凸点216、以及半导体小片182的复合互连结构168。半导体小片182的复合互连结构168环绕或包围半导体小片230的有源表面200和凸点216。半导体小片230的有源表面200和凸点216由半导体小片182的复合互连结构168所限制。半导体小片182的复合互连结构168形成在半导体小片182的外围区域130而半导体小片230布置在半导体小片182的中央区域128之上。
在图5g中，形成的互连结构252形成在重组的晶圆244之上。形成的互连结构252包括使用诸如溅射、电解电镀和非电镀的图案化和金属沉积工艺而形成的导电层或RDL254。导电层254能够为Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一层或多层。导电层254的一部分电连接到半导体小片230的接触焊盘202。导电层254的另一部分电连接到半导体小片182的复合互连结构168。导电层254的其他部分能够为电共用的或电隔离的，这取决于最终半导体装置的设计和功能。形成的互连结构252还包括绝缘或钝化层256，其形成在导电层254之间用于电隔离。绝缘层256包含Sio2、Si3N4、SiON、Ta2o5、Al2o3或其他具有类似绝缘和结构属性的材料的一层或多层。绝缘层256使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化形成。绝缘层256的一部分通过刻蚀工艺移除以暴露导电层254用于凸点形成或额外的封装互连。
在图5h中，凸点形成在导电层254之上。导电凸点材料使用蒸发、电解电镀、非电镀、落球或丝网印刷工艺沉积在导电层254之上。凸点材料能够为带有可选的焊剂溶液的、Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料和它们的组合。例如，凸点材料能够为易熔的Sn/Pb、高铅焊料或无铅焊料。凸点材料使用合适的粘附或接合工艺接合到导电层254。在一个实施例中，通过将材料加热到熔点之上来回流凸点材料以形成球体或凸点260。在一些应用中，凸点260被再次回流以改善对导电层254的电接触。在一个实施例中，凸点260形成在具有润湿层、阻挡层和粘附层的凸点下金属化(UBM)之上。凸点也能够被压接或热压接到导电层254。凸点260电连接到导电层254。凸点260表示能够在导电层254之上形成的互连结构的一种类型。互连结构也能够使用接合引线、导电膏(paste)、钉头凸点、微凸点或其他电互连。以锯条或激光切割工具262经由密封体250将重组的晶圆244分割成独立的单侧FO-WLCSP264。
图5i示出具有堆叠的减薄半导体小片182和230的单侧FO-WLCSP264。半导体小片182的导电层150将来自中央区域128的信号发送到外围区域130，这允许中央区域128的一部分免于设置复合互连结构168以容纳与较小半导体小片230的堆叠。保持免于设置复合互连结构168的、半导体小片182的中央区域128的该部分对应于布置在半导体小片182上方的较小半导体小片230的占用空间。半导体小片182经由接触焊盘136电连接到导电层150。导电层150将离开半导体小片182的中央区域128中接触焊盘136的信号发送到该半导体小片的外围区域130。半导体小片182的导电层150电连接到导电层160。导电层160位于半导体小片182的外围区域130。半导体小片182的中央区域128的一部分没有导电层160。没有导电层160的、半导体小片182的中央区域128的该部分对应于布置在半导体小片182之上的较小半导体小片230的占用空间。半导体小片182的导电层160电连接到导电柱164。导电柱164位于半导体小片182的外围区域130。半导体小片182的中央区域128的一部分没有导电柱164。没有导电柱164的、半导体小片182的中央区域128的该部分对应于布置在半导体小片182上方的较小半导体小片230的占用空间。半导体小片182的导电柱164电连接到凸帽166。凸帽166位于半导体小片182的外围区域130中。半导体小片182的中央区域128的一部分没有凸帽166。没有凸帽166的、半导体小片182的中央区域128的该部分对应于布置在半导体小片182上方的较小半导体小片230的占用空间。导电柱164和凸帽166的组合组成了复合互连结构168，其具有非熔部分(导电柱164)和可熔部分(凸帽166)。复合互连结构168电连接到导电层160。半导体小片182经由接触焊盘136、导电层150、导电层160和复合互连结构168电连接到导电层254的一部分以供外部互连。半导体小片230经由接触焊盘202和凸点216电连接到导电层254的一部分以供外部互连。导电层254的一部分电连接到半导体小片230的凸点216。导电层254的另一部分电连接到半导体小片182的复合互连结构168。导电层254的其他部分能够为电共用的或电隔离的，这取决于单侧FO-WLCSP264的设计和功能。凸点260电连接到导电层254。单侧FO-WLCSP264提供从半导体小片182和半导体小片230经由导电层254到外部互连的单侧连通性，而没有使用TSV和THV，这节约大量时间和费用。避免TSV和THV的使用提高了UPH产量并减少了成本。而且，避免TSV和THV的使用消除了会减少装置可靠性的空洞的形成，并且消除了与通孔(via)形成关联的、半导体小片放置精度和翘曲控制的问题。对密封体250以及半导体小片182和230的减薄允许单侧FO-WLCSP264厚度的减少。半导体小片182和230的堆叠允许单侧FO-WLCSP264的占用空间的明显减少。单侧FO-WLCSP264的封装厚度和占用空间的减少增加了对单侧FO-WLCSP264适合的应用的数量，从而增加了对该半导体装置的市场需求。
在从图5b连续的另一实施例中，图6a-6g，相对于图1，示出形成具有半导体封装和减薄半导体小片的单侧FO-WLCSP的备选工艺。在放置来自图4f的半导体小片230之后，使用例如将凸点272向载体定向的拾取和放置(pick and place)操作将半导体封装或装置270装配到载体240和半导体小片230之上的接口层242，如图6a所示。半导体装置270可包括滤波器、存储器或其他IC芯片、处理器、微控制器、确优的(known-good)封装或任何其他包含半导体小片或其他电子装置或电路的封装的装置。凸点272具有高度H3，其大于减薄半导体小片230的厚度T4。凸点272表示能够在半导体装置270之上形成的互连结构的一种类型。互连结构也能够使用导电柱、导电膏、堆叠钉头凸点或其他电互连。半导体装置270的中央区域274的一部分没有凸点272以容纳布置在半导体装置270之上的较小半导体小片230。没有凸点272的、半导体装置270的中央区域274的该部分对应于布置在半导体装置270之上的较小半导体小片230的占用空间。半导体小片230布置在半导体装置270的中央区域274和载体240之间。凸点272位于半导体装置270的外围区域276中以提供半导体装置270的电路和单侧FO-WLCSP之间的连通性，而没有使用TSV和THV。避免TSV和THV的使用提高了UPH产量并减少了成本。而且，避免TSV和THV的使用消除了会减少装置可靠性的空洞的形成，并且消除了与通孔(via)形成关联的、半导体小片放置精度和翘曲控制的问题。半导体装置270的凸点272环绕或包围半导体小片230。半导体小片230布置在半导体装置270的凸点272之间。图6b示出装配到载体240的接口层242的半导体装置270和半导体小片230，作为重组的或重新装配的晶圆280。
在图6c中，密封体或模塑料282使用膏印刷、压缩成型、传递模塑、液体密封成型、真空层叠(vacuum lamination)或其他适合的敷料器(applicator)沉积在半导体装置270、半导体小片230和载体240之上。密封体282能够为聚合物复合材料，诸如具有填充物的环氧树脂、具有填充物的环氧丙烯酸脂或具有适当填充物的聚合物。密封体282不导电并且在环境上保护半导体装置免受外部元件和污染物的影响。在一个实施例中，密封体282使用薄膜辅助成型工艺来沉积。密封体282的表面284可能经历可选的研磨操作来平坦化表面并且减少密封体的厚度。对密封体282的表面284进行研磨以减少密封体的厚度减少了最终半导体装置的总体厚度，从而使得最终的半导体装置能够在需要减少的厚度的应用中得到利用。减少最终半导体装置的厚度提高了对最终半导体装置的市场需求。
在图6d中，载体240和接口层242通过化学刻蚀、机械剥离、CMP、机械研磨、热烘焙、UV光、激光扫描或湿法剥除来移除。将载体240和接口层242移除暴露出半导体小片230的有源表面200和凸点216、以及半导体装置270的凸点272。半导体装置270的凸点272环绕或包围半导体小片230的有源表面200和凸点216。半导体小片230的有源表面200和凸点216由半导体装置270的凸点272所限制。半导体装置270的凸点272形成在半导体装置270的外围区域276中而半导体小片230布置在半导体装置270的中央区域274之上。
在图6e中，形成的互连结构290形成在重组的晶圆280之上。形成的互连结构290包括使用诸如溅射、电解电镀和非电镀的图案化和金属沉积工艺而形成的导电层或RDL292。导电层292能够为Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一层或多层。导电层292的一部分电连接到半导体小片230的接触焊盘202。导电层292的另一部分电连接到半导体装置270的凸点272。导电层292的其他部分能够为电共用的或电隔离的，这取决于最终半导体装置的设计和功能。形成的互连结构290还包括绝缘或钝化层294，其形成在导电层292之间用于电隔离。绝缘层294包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或其他具有类似绝缘和结构属性的材料的一层或多层。绝缘层294使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化工艺形成。绝缘层294的一部分通过刻蚀工艺移除以暴露导电层292用于凸点形成或额外的封装互连。
在图6f中，凸点形成在导电层292之上。导电凸点材料使用蒸发、电解电镀、非电镀、落球或丝网印刷工艺沉积在导电层292之上。凸点材料能够为带有可选的焊剂溶液的、Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料和它们的组合。例如，凸点材料能够为易熔的Sn/Pb、高铅焊料或无铅焊料。凸点材料使用合适的粘附或接合工艺接合到导电层292。在一个实施例中，通过将材料加热到其熔点之上来回流凸点材料以形成球体或凸点296。在一些应用中，凸点296被再次回流以改善对导电层292的电接触。在一个实施例中，凸点296形成在具有润湿层、阻挡层和粘附层的UBM之上。凸点也能够被压接或热压接到导电层292。凸点296电连接到导电层292。凸点296表示能够在导电层292之上形成的互连结构的一种类型。互连结构也能够使用接合引线、导电膏(paste)、钉头凸点、微凸点或其他电互连。以锯条或激光切割工具298经由密封体282将重组的晶圆280分割成独立的单侧FO-WLCSP300。
图6g示出具有堆叠的减薄半导体小片230和半导体装置270的单侧FO-WLCSP300。半导体装置270的中央区域274的一部分没有凸点272以容纳与较小半导体小片230的堆叠。凸点272提供从半导体装置270到单侧FO-WLCSP300的连通性，而没有使用TSV和THV，这节省了大量时间和费用。半导体装置270可包括滤波器、存储器或其他IC芯片、处理器、微控制器、确优的封装或任何其他包含半导体小片或其他电子装置或电路的封装的装置。半导体装置270电连接到凸点272以用于外部互连。半导体小片230经由接触焊盘202电连接到凸点216以用于外部互连。导电层292的一部分电连接到半导体小片230的接触焊盘202。导电层292的另一部分电连接到半导体装置270的凸点272。凸点296电连接到导电层292。单侧FO-WLCSP300提供从半导体小片230和半导体装置270经由导电层292到外部互连的单侧连通性，而没有使用TSV和THV，这节约大量时间和费用。避免TSV和THV的使用提高了UPH产量并减少了成本。而且，避免TSV和THV的使用消除了会减少装置可靠性的空洞的形成，并且消除了与通孔(via)形成关联的、半导体小片放置精度和翘曲控制的问题。对密封体282以及半导体小片230的减薄允许单侧FO-WLCSP300厚度的减少。半导体小片230和半导体装置270的堆叠允许单侧FO-WLCSP300的占用空间的明显减少。单侧FO-WLCSP300的封装厚度和占用空间的减少增加了对单侧FO-WLCSP300适合的应用的数量，从而增加了对半导体装置的市场需求。
尽管详细地例示了本发明的一个或多个实施例，本领域技术人员将理解可对这些实施例作出修正和适配，而没有偏离在下列权利要求中阐述的本发明的范围。

Claims (15)

1.一种制作半导体装置的方法，包括：
提供第一半导体小片；
在所述第一半导体小片的外围区域中形成多个互连结构；以及
在所述互连结构之间的所述第一半导体小片之上沉积第二半导体小片。
2.根据权利要求1所述的方法，还包括在所述第一半导体小片的中央区域和所述第一半导体小片的所述外围区域之间形成导电层。
3.根据权利要求1所述的方法，还包括在所述第一半导体小片和第二半导体小片之上形成重新分配层。
4.根据权利要求1所述的方法，还包括：
提供包括所述第一半导体小片的半导体晶圆；以及
移除所述半导体晶圆的一部分，以使其厚度为30到100微米。
5.根据权利要求4所述的方法，还包括在移除所述半导体晶圆的所述一部分之前形成所述互连结构。
6.一种制作半导体装置的方法，包括：
提供第一半导体小片；
形成第一互连结构和第二互连结构；以及
在所述第一互连结构和所述第二互连结构之间的所述第一半导体小片之上布置第二半导体小片。
7.根据权利要求6所述的方法，还包括在形成所述第一互连结构之后移除所述第一半导体小片的一部分。
8.根据权利要求6所述的方法，其中形成所述第一互连结构还包括：
在所述第一半导体小片的外围区域中形成第一导电柱；以及
在所述导电柱之上形成凸点。
9.根据权利要求6所述的方法，还包括在所述第一半导体小片的中央区域和所述第一半导体小片的外围区域之间形成导电层。
10.根据权利要求6所述的方法，还包括在所述第一半导体小片的中央区域之上布置所述第二半导体小片。
11.一种半导体装置，包括：
第一半导体小片；
第一互连结构和第二互连结构，其形成在所述第一半导体小片的外围区域中；以及
第二半导体小片，其布置在所述第一互连结构和所述第二互连结构之间的所述第一半导体小片之上。
12.根据权利要求11所述的半导体装置，还包括所述第二半导体小片的高度低于所述第一互连结构的高度。
13.根据权利要求11所述的半导体装置，还包括所述第二半导体小片的占用空间小于所述第一半导体小片的中央区域。
14.根据权利要求11所述的半导体装置，其中所述第一互连结构还包括：
导电柱，其形成在所述第一半导体小片的所述外围区域中；以及
凸点，其形成在所述导电柱之上。
15.根据权利要求14所述的半导体装置，还包括重新分配层，其形成在所述第一半导体小片和所述第二半导体小片之上。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449420A (zh) * 2015-08-05 2017-02-22 恒劲科技股份有限公司 嵌埋式封装结构及其制造方法
CN109599390A (zh) * 2018-12-29 2019-04-09 华进半导体封装先导技术研发中心有限公司 一种扇出型封装结构和封装方法
CN110114874A (zh) * 2016-12-30 2019-08-09 英特尔Ip公司 微电子设备中堆叠管芯的互连结构
CN110571158A (zh) * 2016-05-11 2019-12-13 日月光半导体制造股份有限公司 半导体装置封装及其制造方法
CN111755344A (zh) * 2019-03-28 2020-10-09 台湾积体电路制造股份有限公司 封装结构及其形成方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI555166B (zh) * 2013-06-18 2016-10-21 矽品精密工業股份有限公司 層疊式封裝件及其製法
US20160013076A1 (en) * 2014-07-14 2016-01-14 Michael B. Vincent Three dimensional package assemblies and methods for the production thereof
US9633974B2 (en) * 2015-03-04 2017-04-25 Apple Inc. System in package fan out stacking architecture and process flow
US11056373B2 (en) 2015-07-21 2021-07-06 Apple Inc. 3D fanout stacking
TWI582933B (zh) * 2015-08-05 2017-05-11 恆勁科技股份有限公司 嵌埋式封裝結構的製造方法
US10049953B2 (en) * 2015-09-21 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US10854590B2 (en) 2015-12-23 2020-12-01 Intel IP Corporation Semiconductor die package with more than one hanging die
US10461000B2 (en) * 2016-08-08 2019-10-29 Semiconductor Components Industries, Llc Semiconductor wafer and method of probe testing
US11075129B2 (en) 2016-08-08 2021-07-27 Semiconductor Components Industries, Llc Substrate processing carrier
US9793186B1 (en) * 2016-08-08 2017-10-17 Semiconductor Components Industries, Llc Semiconductor wafer and method of backside probe testing through opening in film frame
US11257724B2 (en) 2016-08-08 2022-02-22 Semiconductor Components Industries, Llc Semiconductor wafer and method of probe testing
WO2020036631A2 (en) 2018-03-06 2020-02-20 The Regents Of The University Of California Network on interconnect fabric
KR20220109753A (ko) * 2021-01-29 2022-08-05 삼성전자주식회사 포스트를 포함하는 반도체 패키지
US11694876B2 (en) 2021-12-08 2023-07-04 Applied Materials, Inc. Apparatus and method for delivering a plurality of waveform signals during plasma processing

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010038151A1 (en) * 2000-03-09 2001-11-08 Yoshikazu Takahashi Semiconductor device and the method for manufacturing the same
US20040070064A1 (en) * 2002-10-15 2004-04-15 Tae Yamane Semiconductor device and fabrication method of the same
US20070158857A1 (en) * 2006-01-10 2007-07-12 Casio Computer Co., Ltd. Semiconductor device having a plurality of semiconductor constructs
US20120038064A1 (en) * 2010-08-16 2012-02-16 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Wafer-Level Multi-Row Etched Leadframe With Base Leads and Embedded Semiconductor Die
CN102386113A (zh) * 2010-09-03 2012-03-21 新科金朋有限公司 一种半导体器件及其制造方法
CN103123920A (zh) * 2011-09-16 2013-05-29 阿尔特拉公司 电子组件装置和关联方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6847105B2 (en) * 2001-09-21 2005-01-25 Micron Technology, Inc. Bumping technology in stacked die configurations
US6987031B2 (en) * 2002-08-27 2006-01-17 Micron Technology, Inc. Multiple chip semiconductor package and method of fabricating same
US8076232B2 (en) * 2008-04-03 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
US8124471B2 (en) * 2008-03-11 2012-02-28 Intel Corporation Method of post-mold grinding a semiconductor package
US8642381B2 (en) * 2010-07-16 2014-02-04 Stats Chippac, Ltd. Semiconductor device and method of forming protective layer over exposed surfaces of semiconductor die
US8288201B2 (en) 2010-08-25 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of forming FO-WLCSP with discrete semiconductor components mounted under and over semiconductor die
US8354297B2 (en) 2010-09-03 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die
GB2485830A (en) * 2010-11-26 2012-05-30 Cambridge Silicon Radio Ltd Stacked multi-chip package using encapsulated electroplated pillar conductors; also able to include MEMS elements
TWI590399B (zh) * 2012-04-02 2017-07-01 矽品精密工業股份有限公司 半導體封裝件及其製法與其封裝基板
US9385006B2 (en) 2012-06-21 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SOP fan-out package

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010038151A1 (en) * 2000-03-09 2001-11-08 Yoshikazu Takahashi Semiconductor device and the method for manufacturing the same
US20040070064A1 (en) * 2002-10-15 2004-04-15 Tae Yamane Semiconductor device and fabrication method of the same
US20070158857A1 (en) * 2006-01-10 2007-07-12 Casio Computer Co., Ltd. Semiconductor device having a plurality of semiconductor constructs
US20120038064A1 (en) * 2010-08-16 2012-02-16 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Wafer-Level Multi-Row Etched Leadframe With Base Leads and Embedded Semiconductor Die
CN102386113A (zh) * 2010-09-03 2012-03-21 新科金朋有限公司 一种半导体器件及其制造方法
CN103123920A (zh) * 2011-09-16 2013-05-29 阿尔特拉公司 电子组件装置和关联方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449420A (zh) * 2015-08-05 2017-02-22 恒劲科技股份有限公司 嵌埋式封装结构及其制造方法
CN106449420B (zh) * 2015-08-05 2019-06-21 凤凰先驱股份有限公司 嵌埋式封装结构及其制造方法
CN110571158A (zh) * 2016-05-11 2019-12-13 日月光半导体制造股份有限公司 半导体装置封装及其制造方法
CN110571158B (zh) * 2016-05-11 2021-12-21 日月光半导体制造股份有限公司 半导体装置封装及其制造方法
CN110114874A (zh) * 2016-12-30 2019-08-09 英特尔Ip公司 微电子设备中堆叠管芯的互连结构
CN109599390A (zh) * 2018-12-29 2019-04-09 华进半导体封装先导技术研发中心有限公司 一种扇出型封装结构和封装方法
CN111755344A (zh) * 2019-03-28 2020-10-09 台湾积体电路制造股份有限公司 封装结构及其形成方法
CN111755344B (zh) * 2019-03-28 2023-10-24 台湾积体电路制造股份有限公司 封装结构及其形成方法

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