TW201501227A - 在扇出晶圓級晶片尺寸封裝上堆疊半導體晶粒之半導體裝置和方法 - Google Patents

在扇出晶圓級晶片尺寸封裝上堆疊半導體晶粒之半導體裝置和方法 Download PDF

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TW201501227A
TW201501227A TW103119637A TW103119637A TW201501227A TW 201501227 A TW201501227 A TW 201501227A TW 103119637 A TW103119637 A TW 103119637A TW 103119637 A TW103119637 A TW 103119637A TW 201501227 A TW201501227 A TW 201501227A
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semiconductor die
semiconductor
interconnect structure
conductive layer
die
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TW103119637A
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TWI662631B (zh
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Xusheng Bao
Kwokkeung Szeto
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Stats Chippac Ltd
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Abstract

一種半導體裝置係具有一第一半導體晶粒。一例如是一導電柱的第一互連結構以及第二互連結構係被形成在該第一半導體晶粒的一週邊區域中，該導電柱係包含一形成在該導電柱之上的凸塊。一第二半導體晶粒係被設置在該第一互連結構以及該第二互連結構之間的該第一半導體晶粒之上。該第二半導體晶粒的一高度係小於該第一互連結構的一高度。該第二半導體晶粒的一覆蓋區係小於該第一半導體晶粒的一中央區域。一種囊封體係沉積在該第一半導體晶粒以及第二半導體晶粒之上。或者是，該第二半導體晶粒係被設置在一包含複數個互連結構的半導體封裝之上。來自該單側扇出晶圓級晶片尺寸封裝之外部的連接性係在不使用導電的穿孔下加以執行，以提供高的處理量及裝置可靠度。

Description

在扇出晶圓級晶片尺寸封裝上堆疊半導體晶粒之半導體裝置和方法
本發明係大致有關於半導體裝置，並且更具體而言係有關於一種利用單側扇出晶圓級晶片尺寸封裝(FO-WLCSP)來堆疊半導體晶粒或半導體封裝之半導體裝置和方法。
國內優先權之主張
本申請案係主張2013年6月28日申請的美國臨時申請案號61/841,059的益處，該申請案係被納入在此作為參考。
半導體裝置係常見於現代的電子產品中。半導體裝置係在電氣構件的數目及密度上變化。離散的半導體裝置一般包含一類型的電氣構件，例如，發光二極體、小信號電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(MOSFET)。集積的半導體裝置通常包含數百到數百萬個電氣構件。集積的半導體裝置的例子係包含微控制器、微處理器、電荷耦合裝置(CCD)、太陽能電池、以及數位微鏡裝置(DMD)。
半導體裝置係執行廣範圍的功能，例如，信號處理、高速的計算、傳送及接收電磁信號、控制電子裝置、轉換太陽光成為電力、以及產生用於電視顯示器的視覺投影。半導體裝置係見於娛樂、通訊、電力轉 換、網路、電腦以及消費者產品的領域中。半導體裝置亦見於軍事的應用、航空、汽車、工業用的控制器、以及辦公室設備。
半導體裝置係利用半導體材料的電氣特性。半導體材料的結構係容許該半導體材料的導電度能夠藉由一電場或基極電流的施加或是透過摻雜的製程來加以操縱。摻雜係將雜質帶入半導體材料中，以操縱及控制半導體裝置的導電度。
一半導體裝置係包含主動及被動的電性結構。包含雙載子及場效電晶體的主動結構係控制電流的流動。藉由改變摻雜的程度以及一電場或基極電流的施加，該電晶體不是提升、就是限制電流的流動。包含電阻器、電容器及電感器的被動結構係在電壓及電流之間產生執行各種電氣功能所必要的一種關係。該被動及主動結構係電連接以形成電路，此係使得該半導體裝置能夠執行高速的運算及其它有用的功能。
半導體裝置一般是利用兩個複雜的製程，亦即，前端製造及後端製造來加以製造，每個製造潛在涉及數百道步驟。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。每個半導體晶粒通常是相同的，並且包含藉由電連接主動及被動構件所形成的電路。後端製造係牽涉到從完成的晶圓單粒化(singulating)個別的半導體晶粒並且封裝該晶粒以提供結構的支撐以及環境的隔離。如同在此所用的術語“半導體晶粒”係指該字的單數與複數形兩者，並且於是可以指稱單一半導體裝置及多個半導體裝置兩者。
半導體製造的一目標是產出較小的半導體裝置。較小的裝置通常消耗較低的功率，具有較高的效能，並且可以更有效率地加以生產。 此外，較小的半導體裝置具有一較小的覆蓋區，此係較小的終端產品所期望的。較小的晶粒尺寸可藉由在產生具有較小且較高密度的主動及被動構件之半導體晶粒的前端製程中的改良來達成。後端製程可以藉由在電氣互連及囊封體上的改良來產生具有較小覆蓋區的半導體裝置封裝。
較小的半導體裝置的製造係依賴對於在多個層級上(3D裝置的集積)，於多個半導體裝置之間的水平及垂直的電互連實施改良。水平的電互連係包含被形成為FO-WLCSP或是嵌入式晶圓級球格陣列(eWLB)的部分之重新分佈層(RDL)，其係提供在一半導體晶粒以及該封裝的外部的點之間的電連接。垂直的互連可以利用導電的直通矽晶穿孔(TSV)或是直通孔洞穿孔(THV)來加以達成。然而，TSV及THV的使用通常牽涉到相當大量的時間及設備，此係降低每小時的產能(UPH)製造並且增加成本。再者，穿孔的形成可能會包含空孔(void)的形成，此係降低裝置可靠度，並且可能對於半導體晶粒的設置正確性及翹曲控制產生問題。
對於以一種達成較低的成本、較高的UPH製造以及增高的裝置可靠度方式來增加半導體晶粒封裝的密度係存在著需求。於是，在一實施例中，本發明是一種製造一半導體裝置之方法，其係包括以下步驟：提供一第一半導體晶粒，在該第一半導體晶粒的一週邊區域中形成複數個互連結構，以及在該些互連結構之間的該第一半導體晶粒之上設置一第二半導體晶粒。
在另一實施例中，本發明是一種製造一半導體裝置之方法，其係包括以下步驟：提供一第一半導體晶粒，形成一第一互連結構以及一 第二互連結構，以及將一第二半導體晶粒設置在該第一互連結構以及該第二互連結構之間的該第一半導體晶粒之上。
在另一實施例中，本發明是一種半導體裝置，其係包括一第一半導體晶粒。一第一互連結構以及一第二互連結構係被形成在該第一半導體晶粒的一週邊區域中。一第二半導體晶粒係被設置在該第一互連結構以及該第二互連結構之間的該第一半導體晶粒之上。
在另一實施例中，本發明是一種半導體裝置，其係包括一第一半導體晶粒。一第一互連結構以及一第二互連結構係被形成在該第一半導體晶粒之上。一第二半導體晶粒係被設置在該第一互連結構以及該第二互連結構之間的該第一半導體晶粒之上。
50‧‧‧電子裝置
52‧‧‧晶片載體基板/印刷電路板(PCB)
54‧‧‧信號線路
56‧‧‧接合線封裝
58‧‧‧覆晶
60‧‧‧球格陣列(BGA)
62‧‧‧凸塊晶片載體(BCC)
66‧‧‧平台柵格陣列(LGA)
68‧‧‧多晶片模組(MCM)
70‧‧‧四邊扁平無引腳封裝(QFN)
72‧‧‧四邊扁平封裝
74‧‧‧eWLB
76‧‧‧晶圓級晶片尺寸封裝(WLCSP)
120‧‧‧半導體晶圓
122‧‧‧主體基板材料
124‧‧‧半導體晶粒/構件
126‧‧‧切割道
128‧‧‧中央區域
128a‧‧‧第一區域
128b‧‧‧第二區域
128c‧‧‧區域
128d‧‧‧區域
128e‧‧‧區域
128f‧‧‧區域
130‧‧‧週邊區域
132‧‧‧背面/非主動表面
134‧‧‧主動表面
136‧‧‧導電層/節點/接觸墊
138‧‧‧絕緣層/保護層
140‧‧‧探針/測試引線
142‧‧‧測試探針頭
144‧‧‧電腦測試系統
150‧‧‧導電層/RDL
152‧‧‧絕緣層/保護層
154‧‧‧圖案化層/光阻層
156‧‧‧雷射
158‧‧‧圖案化的開口
160‧‧‧導電層
162‧‧‧導電材料
164‧‧‧導電柱
166‧‧‧凸塊蓋
168‧‧‧複合的互連結構
170‧‧‧保護塗層
172‧‧‧疊層帶
172a‧‧‧介電基底膜
172b‧‧‧黏著層
174‧‧‧研磨機
176‧‧‧背表面
180‧‧‧鋸刀/雷射切割工具
182‧‧‧半導體晶粒
190‧‧‧半導體晶圓
192‧‧‧主體基板材料
194‧‧‧半導體晶粒/構件
196‧‧‧切割道
198‧‧‧背面/非主動表面
200‧‧‧主動表面
202‧‧‧導電層/接觸墊
204‧‧‧絕緣層/保護層
210‧‧‧探針
212‧‧‧測試探針頭
214‧‧‧電腦測試系統
216‧‧‧球/凸塊
220‧‧‧保護塗層
222‧‧‧疊層帶
222a‧‧‧介電基底膜
222b‧‧‧黏著層
224‧‧‧研磨機
226‧‧‧背表面
228‧‧‧鋸刀/雷射切割工具
230‧‧‧半導體晶粒
240‧‧‧基板/載體
242‧‧‧介面層/雙面帶
244‧‧‧重組晶圓/重新配置的晶圓
246‧‧‧表面
250‧‧‧囊封體/模製化合物
252‧‧‧堆積的互連結構
254‧‧‧導電層/RDL
256‧‧‧絕緣層/保護層
260‧‧‧球/凸塊
262‧‧‧鋸刀/雷射切割工具
264‧‧‧單側FO-WLCSP
270‧‧‧半導體封裝/半導體裝置
272‧‧‧凸塊
274‧‧‧中央區域
276‧‧‧週邊區域
280‧‧‧重組晶圓/重新配置的晶圓
282‧‧‧囊封體/模製化合物
284‧‧‧表面
290‧‧‧堆積的互連結構
292‧‧‧導電層/RDL
294‧‧‧絕緣層/保護層
296‧‧‧球/凸塊
298‧‧‧鋸刀/雷射切割工具
300‧‧‧單側fo-WLCSP
H1‧‧‧高度
H2‧‧‧高度
T1‧‧‧厚度
T2‧‧‧厚度
T3‧‧‧厚度
T4‧‧‧厚度
圖1係描繪一印刷電路板(PCB)，其中不同類型的封裝係安裝到該PCB的一表面；圖2a-2l係描繪一具有複數個藉由切割道分開的半導體晶粒之半導體晶圓；圖3a-3c係以平面圖來描繪圖2a-2l的半導體晶粒；圖4a-4f係描繪一具有複數個藉由切割道分開的半導體晶粒之半導體晶圓；圖5a-5i係描繪一利用單側FO-WLCSP來堆疊圖2a-2l及4a-4f的半導體晶粒的製程；以及圖6a-6g係描繪一利用單側FO-WLCSP來堆疊一半導體封裝以及圖 4a-4f的半導體晶粒的製程。
本發明係在以下參考該些圖式的說明中，以一或多個實施例來加以描述，其中相同的元件符號係代表相同或類似的元件。儘管本發明係以用於達成本發明之目的之最佳模式來加以描述，但熟習此項技術者將會體認到的是，其係欲涵蓋可內含在藉由所附的申請專利範圍及其由以下的揭露內容及圖式所支持的等同項所界定的本發明的精神與範疇內的替換物、修改以及等同物。
半導體裝置一般是利用兩個複雜的製程：前端製造及後端製造來加以製造。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。在該晶圓上的每個晶粒係包含電連接以形成功能電路的主動及被動電氣構件。例如是電晶體及二極體的主動電氣構件係具有控制電流的流動之能力。例如是電容器、電感器及電阻器的被動電氣構件係產生執行電路功能所必要的電壓及電流之間的一種關係。
被動及主動構件係藉由一系列的製程步驟而形成在半導體晶圓的表面之上，該些製程步驟包含摻雜、沉積、微影、蝕刻及平坦化。摻雜係藉由例如是離子植入或熱擴散的技術以將雜質帶入半導體材料中。該摻雜製程係藉由響應於一電場或基極電流來動態地改變該半導體材料的導電度以修改主動元件中的半導體材料的導電度。電晶體係包含具有不同類型及程度的摻雜的區域，該些區域係以使得該電晶體在電場或基極電流的施加時提升或限制電流的流動所必要的來加以配置。
主動及被動構件係藉由具有不同電氣特性的材料層來加以 形成。該些層可藉由各種沉積技術來形成，該些技術部分是由被沉積的材料類型所決定的。例如，薄膜沉積可能牽涉到化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解的電鍍以及無電的電鍍製程。每個層一般是被圖案化，以形成主動構件、被動構件或是構件間的電連接的部分。
後端製造係指切割或單粒化完成的晶圓成為個別的半導體晶粒並且接著為了結構的支撐及環境的隔離來封裝該半導體晶粒。為了單粒化該半導體晶粒，晶圓係沿著該晶圓的非功能區域(稱為切割道或劃線)來被劃線且截斷。該晶圓係利用一雷射切割工具或鋸刀而被單粒化。在單粒化之後，該個別的半導體晶粒係被安裝到一封裝基板，該封裝基板係包含用於和其它系統構件互連的接腳或接觸墊。形成在半導體晶粒之上的接觸墊係接著連接至該封裝內的接觸墊。該些電連接可以利用焊料凸塊、柱形凸塊、導電膏、或是引線接合來做成。一囊封體(encapsulant)或是其它模製材料係沉積在該封裝之上，以提供實體支撐及電氣隔離。該完成的封裝係接著被插入一電氣系統中，並且使得該半導體裝置的功能為可供其它系統構件利用的。
圖1係描繪具有一晶片載體基板或PCB 52之電子裝置50，其中複數個半導體封裝係安裝在PCB 52的一表面之上。視應用而定，電子裝置50可具有一種類型之半導體封裝或是多種類型之半導體封裝。
電子裝置50可以是一使用該些半導體封裝以執行一或多種電功能之獨立的系統。或者，電子裝置50可以是一較大系統之子構件。舉例而言，電子裝置50可以是行動電話、個人數位助理(PDA)、數位視訊攝影機(DVC)、或是其它電子通訊裝置的一部份。或者是，電子裝置50可以 是一可插入電腦中之顯示卡、網路介面卡或其它信號處理卡。該半導體封裝可包括微處理器、記憶體、特殊應用積體電路(ASIC)、邏輯電路、類比電路、射頻(RF)電路、離散裝置或其它半導體晶粒或電氣構件。小型化及重量減輕是這些產品能夠被市場接受所不可少的。在半導體裝置間的距離可被縮短以達到更高的密度。
在圖1中，PCB 52係提供一般的基板以供安裝在該PCB上之半導體封裝的結構支撐及電氣互連。導電的信號線路54係利用蒸鍍、電解的電鍍、無電的電鍍、網版印刷、或其它適合的金屬沉積製程而被形成在PCB 52的一表面之上或是在層內。信號線路54係提供在半導體封裝、安裝的構件、以及其它外部的系統構件的每一個之間的電通訊。線路54亦提供電源及接地連接給每個半導體封裝。
在某些實施例中，一半導體裝置係具有兩個封裝層級。第一層級的封裝是一種用於將半導體晶粒機械及電氣地附接至一中間載體的技術。第二層級的封裝係牽涉到將該中間載體機械及電氣地附接至PCB。在其它實施例中，一半導體裝置可以只有該第一層級的封裝，其中晶粒是直接機械及電性地安裝到PCB上。
為了說明之目的，包含接合線封裝56及覆晶58之數種類型的第一層級的封裝係被展示在PCB 52上。此外，包含球格陣列(BGA)60、凸塊晶片載體(BCC)62、平台柵格陣列(LGA)66、多晶片模組(MCM)68、四邊扁平無引腳封裝(QFN)70、四邊扁平封裝72、eWLB 74以及晶圓級晶片尺寸封裝(WLCSP)76之數種類型的第二層級的封裝係被展示安裝在PCB 52上。eWLB 74是一扇出晶圓級封裝，而WLCSP 76是一扇入晶圓級封裝 (FI-WLP)。視系統需求而定，以第一及第二層級的封裝類型的任意組合來組態的半導體封裝及其它電子構件的任意組合都可連接至PCB 52。在某些實施例中，電子裝置50係包含單一附接的半導體封裝，而其它實施例係需要多個互連的封裝。藉由在單一基板之上組合一或多個半導體封裝，製造商可將預製的構件納入電子裝置及系統中。由於半導體封裝包括複雜的功能，因此可使用較便宜構件及流線化製程來製造電子裝置。所產生的裝置不太可能發生失效且製造費用較便宜，從而對於消費者產生降低的成本。
圖2a-2i係相關於圖1來描繪一利用在該半導體晶粒的一週邊區域中之複合的互連結構來形成一薄化的半導體晶粒的製程。一RDL係將來自在該半導體晶粒的一中央區域中的電路之信號繞線至該半導體晶粒的該週邊區域。在一實施例中，該半導體晶粒的該中央區域的一部分係維持沒有複合的互連結構，以在一後續的處理步驟中容納一設置在該半導體晶粒之上的較小的半導體晶粒。在另一實施例中，複合的互連結構的列可以將該中央區域區分成較小的區域，以容納堆疊在該半導體晶粒之上的超過一個的較小的半導體晶粒。
圖2a係展示一半導體晶圓120，其係具有一種主體基板材料122，例如矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、或是矽碳化物、或是其它用於結構的支撐之基體半導體材料。在一實施例中，半導體晶圓120係具有一100-450mm的寬度或直徑。複數個半導體晶粒或構件124係被形成在晶圓120上，其係藉由一如上所述的非主動的晶粒間的晶圓區域或切割道126加以分開。切割道126係提供切割區域，以單粒化半導體晶圓120成為個別的半導體晶粒124。每個半導體晶粒124係具有一中央 區域128以及一週邊區域130。在一實施例中，中央區域128係具有一方形或矩形的形狀。
圖2b係展示半導體晶圓120的一部分的橫截面圖。每個半導體晶粒124係具有一背面或非主動表面132以及一包含類比或數位電路的主動表面134，該些類比或數位電路係被實施為形成在晶粒內之主動元件、被動元件、導電層及介電層並且根據該晶粒的電性設計及功能而電互連。例如，該電路可包含形成在主動表面134內之一或多個電晶體、二極體以及其它電路元件，以實施類比電路或數位電路，例如數位信號處理器(DSP)、ASIC、記憶體、或是其它信號處理電路。半導體晶粒124亦可包含整合的被動裝置(IPD)，例如電感器、電容器及電阻器，以用於RF信號處理。
一導電層136係利用PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它適合的金屬沉積製程以形成在主動表面134之上。導電層136可以是一或多層的鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或是其它適當的導電材料。導電層136係運作為電連接至主動表面134上的電路之接觸墊。導電層136可被形成為接觸墊，該些接觸墊係與半導體晶粒124的邊緣相隔一第一距離並排地加以設置，即如同在圖2b中所示者。或者是，導電層136可被形成為接觸墊，該些接觸墊係以多個列加以偏置，使得一第一列的接觸墊係與該晶粒的邊緣相隔一第一距離加以設置，並且一和該第一列交錯的第二列的接觸墊係與該晶粒的邊緣相隔一第二距離加以設置。
一絕緣或保護層138係利用PVD、CVD、網版印刷、旋轉塗覆、噴霧塗覆、燒結、或是熱氧化以形成在主動表面134及導電層136之上。 該絕緣層138係包含一或多層的二氧化矽(SiO2)、矽氮化物(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、鋁氧化物(Al2O3)、或是其它具有類似絕緣及結構的性質之材料。該絕緣層138係覆蓋並且提供保護給主動表面134。絕緣層138的一部分係藉由蝕刻、雷射直接剝蝕(LDA)、或是其它適當的製程來加以移除以露出導電層136，以用於後續的電互連。
在圖2c中，半導體晶圓120係進行電性測試及檢查，以作為一品質管制製程的部分。人工視覺的檢查以及自動化的光學系統係被用來對於半導體晶圓120執行檢查。軟體可被利用在半導體晶圓120的自動化光學分析中。視覺的檢查方法可以利用例如是一掃描式電子顯微鏡、高強度或紫外線的光、或是金相顯微鏡的設備。半導體晶圓120係針對於包含翹曲、厚度變化、表面微粒、不規則性、裂縫、脫層、以及變色之結構的特徵來加以檢查。
在半導體晶粒124內的主動及被動構件係在晶圓層級下對於電性效能及電路功能進行測試。如同在圖2c中所示，每個半導體晶粒124係針對於功能及電性參數而被測試，其係利用一包含複數個探針或測試引線140的測試探針頭142或是其它的測試裝置。探針140係被用來與在每個半導體晶粒124上的節點或接觸墊136做成電性接觸，並且提供電性刺激至該些接觸墊。半導體晶粒124係響應該些電性刺激，此係藉由電腦測試系統144來加以量測並且相較於一預期的響應，以測試該半導體晶粒的功能。該電性測試可包含電路功能、引線完整性、電阻率、連續性、可靠度、接面深度、ESD、RF效能、驅動電流、臨界電流、漏電流、以及該構件類型特有的操作參數。半導體晶圓120的該檢查及電性測試係使得通過而被標 明為已知良好的晶粒(KGD)的半導體晶粒124能夠用於一半導體封裝。
在圖2d中，一導電層或RDL 150係利用PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它適合的金屬沉積製程以形成在導電層136及絕緣層138之上。導電層150可以是一或多層的Al、Ti、TiW、Cu、Sn、Ni、Au、Ag、或是其它適當的導電材料。導電層150的一部分係電連接至導電層136。根據半導體晶粒124的設計及功能，導電層150的其它部分可以是電性共通或是電性隔離的。RDL 150係將在半導體晶粒124的中央區域128中的接觸墊136的信號繞線離開至該半導體晶粒的週邊區域130。在一實施例中，半導體晶粒124是任何現有或是先前設計出的半導體晶粒。半導體晶粒124係具有在中央區域128中的信號及接觸墊136。半導體晶粒124的中央區域128的一部分必須沒有封裝互連，以便容納與較小的半導體晶粒之堆疊。藉由將中央區域128的信號繞線離開至週邊區域130，導電層150係使得半導體晶粒124能夠容納與較小的半導體晶粒之堆疊，而不須客製化或重新設計該半導體晶粒，此係節省相當大量的時間及費用並且延伸先前設計出的半導體晶粒124的效用。
一絕緣或保護層152係利用PVD、CVD、印刷、疊層、旋轉塗覆、噴霧塗覆、燒結、或是熱氧化以形成在絕緣層138及導電層150之上。絕緣層152係包含一或多層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是其它具有類似絕緣及結構的性質之材料。絕緣層152的一部分係藉由LDA、蝕刻、或是其它適當的製程來加以移除，以露出導電層150。導電層150係將在半導體晶粒124的中央區域128中接觸墊136的信號繞線離開至該半導體晶粒的週邊區域130。於是，在絕緣層152中露出導電層150的開口係位在 半導體晶粒124的週邊區域130中。在半導體晶粒124的中央區域128的一部分中的導電層150係維持被絕緣層152所覆蓋。半導體晶粒124的中央區域128之維持被絕緣層152所覆蓋的部分係對應於在一後續的處理步驟中，將被設置在半導體晶粒124之上的較小的半導體晶粒的覆蓋區。
在圖2e中，一圖案化或光阻層154係利用印刷、旋轉塗覆、或是噴霧塗覆以形成在導電層150及絕緣層152之上。在一實施例中，光阻層154係具有一40-150微米(μm)的厚度。光阻層154的一部分係藉由利用雷射156的LDA來加以移除，以形成圖案化的開口158並且露出導電層150及絕緣層152。或者是，光阻層154的部分係藉由一蝕刻製程透過一圖案化的光阻層來加以移除，以形成圖案化的開口158並且露出導電層150及絕緣層152。導電層150係將在半導體晶粒124的中央區域128中的接觸墊136的信號繞線離開至該半導體晶粒的週邊區域130。於是，在光阻層154中露出導電層150及絕緣層152之圖案化的開口158係位在半導體晶粒124的週邊區域130中。半導體晶粒124的中央區域128的一部分係維持被光阻層154所覆蓋。半導體晶粒124的中央區域128的一部分係沒有在光阻層154中之圖案化的開口158。半導體晶粒124的中央區域128維持被光阻層154所覆蓋的部分係對應於在一後續的處理步驟中將被設置在半導體晶粒124之上的較小的半導體晶粒的覆蓋區。在一實施例中，圖案化的開口158係具有一圓形的橫截面區域，其係被配置以形成具有一包含圓形橫截面的圓柱形的形狀之導電柱。在另一實施例中，圖案化的開口158係具有一矩形的橫截面區域，其係被配置以形成具有一包含矩形橫截面的立方體形狀之導電柱。
在圖2f中，一導電層160係利用一圖案化及金屬沉積製程，例如印刷、PVD、CVD、濺鍍、電解的電鍍、以及無電的電鍍而被保形地施加在開口158內的導電層150及絕緣層152之上。在光阻層154中之圖案化的開口158係位在半導體晶粒124的週邊區域130中。於是，設置在圖案化的開口158中的導電層160係位在半導體晶粒124的週邊區域130中。半導體晶粒124的中央區域128的一部分係維持被光阻層154所覆蓋。半導體晶粒124的中央區域128的一部分係沒有導電層160。半導體晶粒124的中央區域128維持被光阻層154所覆蓋而且沒有導電層160的部分係對應於在一後續的處理步驟中將被設置在半導體晶粒124之上的較小的半導體晶粒的覆蓋區。導電層160可以是一或多層的Al、Cu、Sn、Ti、Ni、Au、Ag、或是其它適當的導電材料。在一實施例中，導電層160是一多層的堆疊，其係包含一晶種層、阻障層以及黏著層。該晶種層可以是鈦銅(TiCu)、鈦鎢銅(TiWCu)、或是鉭氮銅(TaNCu)。該阻障層可以是Ni、鎳釩(NiV)、鉑(Pt)、鈀(Pd)、TiW、CrCu、或是其它適當的材料。該黏著層可以是Ti、TiN、TiW、Al或鉻(Cr)、或是其它適當的材料。導電層160係依循導電層150及絕緣層152的輪廓。導電層160係電連接至導電層150。
在圖2g中，一導電材料162係利用一蒸鍍、濺鍍、電解的電鍍、無電的電鍍、或是網版印刷製程以沉積在圖案化的開口158之內以及在導電層160之上。導電材料162可以是Cu、Al、鎢(W)、Au、焊料、或是其它適當的導電材料。在一實施例中，導電材料162係藉由在光阻層154之圖案化的開口158中電鍍Cu來加以沉積的。光阻層154之圖案化的開口158係位在半導體晶粒124的週邊區域130中。於是，設置在圖案化的開口 158中的導電材料162係位在半導體晶粒124的週邊區域130中。半導體晶粒124的中央區域128的一部分係維持被光阻層154所覆蓋。半導體晶粒124的中央區域128的一部分係沒有導電材料162。半導體晶粒124的中央區域128維持被光阻層154所覆蓋而且沒有導電材料162的部分係對應於在一後續的處理步驟中將被設置在半導體晶粒124之上的較小的半導體晶粒的覆蓋區。導電材料162係電連接至導電層160。
在圖2h中，光阻層154係藉由一蝕刻製程來加以移除，以留下個別的導電柱164。導電柱164可具有一帶有圓形或橢圓形的橫截面之圓柱形的形狀、或是導電柱164可具有一帶有矩形橫截面之立方體形狀。導電柱164係具有一高度H1。在一實施例中，導電柱164可以利用堆疊的凸塊或柱形凸塊來加以實施。在另一實施例中，導電柱164的高度H1是40-150μm。導電材料162係被設置在位於半導體晶粒124的週邊區域130中之圖案化的開口158中。於是，導電柱164係位在半導體晶粒124的週邊區域130中。半導體晶粒124的中央區域128的一部分係沒有導電柱164。半導體晶粒124的中央區域128的一部分係維持被絕緣層152所覆蓋。半導體晶粒124的中央區域128維持被絕緣層152所覆蓋而且沒有導電柱164的部分係對應於在一後續的處理步驟中將被設置在半導體晶粒124之上的較小的半導體晶粒的覆蓋區。導電柱164係電連接至導電層160。
在圖2i中，一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落、或是網版印刷製程以沉積在導電柱164之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、鉍(Bi)、Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的 焊料、或是無鉛的焊料。該凸塊材料可加以回焊以形成一圓形的凸塊蓋166。在某些應用中，凸塊蓋166係被回焊第二次，以改善至柱164的電性接觸。或者是，該凸塊材料係在移除光阻層154之前加以沉積的。導電柱164及凸塊蓋166的組合構成一具有一非可熔的部分(導電柱164)以及一可熔的部分(凸塊蓋166)之複合的互連結構168。凸塊蓋166係電連接至導電柱164。導電柱164係位在半導體晶粒124的週邊區域130中。於是，複合的互連結構168係位在半導體晶粒124的週邊區域130中。半導體晶粒124的中央區域128的一部分係沒有複合的互連結構168。半導體晶粒124的中央區域128的一部分係維持被絕緣層152所覆蓋。半導體晶粒124的中央區域128維持被絕緣層152所覆蓋而且沒有複合的互連結構168的部分係對應於在一後續的處理步驟中將被設置在半導體晶粒124之上的較小的半導體晶粒的覆蓋區。複合的互連結構168係具有一高度H2。在一實施例中，複合的互連結構168的高度H2是40-150μm。複合的互連結構168係代表一種可被形成在半導體晶粒124之上的互連結構類型。該互連結構亦可以使用凸塊、導電膏、堆疊的柱形凸塊或是其它電互連。複合的互連結構168係電連接至導電層160。
在圖2j中，一保護塗層170係橫跨半導體晶圓120的整個區域以形成在絕緣層152及複合的互連結構168之上。保護塗層170可以是一或多層藉由網版印刷、旋轉塗覆、噴霧塗覆、或是其它適當的沉積製程所施加的一種水溶性的聚合物材料。一疊層帶172係橫跨半導體晶圓120的整個區域而被施加在保護塗層170之上。在一實施例中，如同在圖2j中的半導體晶圓120的一部分的橫截面圖中所示，疊層帶172係包含一介電基 底膜172a以及黏著層172b。保護塗層170係覆蓋包含半導體晶粒124的中央區域128及週邊區域130之半導體晶圓120的主動表面134以及切割道126。
半導體晶圓120係具有一最初的厚度T1。在圖2k中，半導體晶圓120的背表面132係受到一利用研磨機174的背面研磨操作或是其它適當的機械式或蝕刻製程，以移除基底材料122的一部分並且降低該基底材料至一小於厚度T1的厚度T2。基底材料122從背表面132的移除係被執行為一機械式製程或是物理蝕刻製程，其係留下橫跨該半導體晶圓的整個寬度都為均勻的半導體晶圓120的新的背表面176。或者是，基底材料122的一部分係從背表面132藉由LDA來加以移除，以露出新的背表面176。在一實施例中，在該背面研磨或晶圓薄化操作之後，半導體晶圓120係具有一30-50μm的厚度T2。在另一實施例中，在該背面研磨或晶圓薄化操作之後，半導體晶圓120係具有一約100μm的厚度T2。在絕緣層152以及複合的互連結構168之上的保護塗層170係在該背面研磨或晶圓薄化操作以及後續的製程期間，降低切損(kerf shift)以及碎片及污染物在主動表面134上的累積。於是，保護塗層170係在圖2k的背面研磨或晶圓薄化操作之前被施加在絕緣層152以及複合的互連結構168之上。
在圖2l中，在絕緣層152及複合的互連結構168之上的保護塗層170係藉由一剝離或剝除操作來加以移除。半導體晶圓120係透過切割道126利用鋸刀或雷射切割工具180而被單粒化成為在週邊區域130中包含複合的互連結構168之個別的半導體晶粒182。半導體晶粒182係透過接觸墊136而電連接至導電層150。導電層150係將在半導體晶粒182的中央 區域128中的接觸墊136的信號繞線離開至該半導體晶粒的週邊區域130。半導體晶粒182的導電層150係電連接至導電層160。導電層160係位在半導體晶粒182的週邊區域130中。半導體晶粒182的導電層160係電連接至導電柱164。導電柱164係位在半導體晶粒182的週邊區域130中。半導體晶粒182的導電柱164係電連接至凸塊蓋166。凸塊蓋166係位在半導體晶粒182的週邊區域130中。導電柱164及凸塊蓋166的組合係構成具有一非可熔的部分(導電柱164)以及一可熔的部分(凸塊蓋166)之一複合的互連結構168。複合的互連結構168係電連接至導電層160。半導體晶粒182的中央區域128的一部分係沒有複合的互連結構168。半導體晶粒182的中央區域128的沒有導電的互連結構168的部分係對應於在一後續的處理步驟中將被設置在半導體晶粒182之上的較小的半導體晶粒的覆蓋區。半導體晶粒182係透過接觸墊136、導電層150以及導電層160來電連接至複合的互連結構168以用於外部的互連。個別的半導體晶粒182可以對於單粒化後的KGD的識別來加以檢查並且電性地測試。
圖3a-3c係相關於圖1來描繪一在圖2a-2l中敘述的半導體晶粒的平面圖，其係展示在一週邊區域中的複合的互連結構以及一沒有複合的互連結構之中央區域的實施例。圖3a係展示具有形成在週邊區域130中的複合的互連結構168之半導體晶粒182的平面圖。圖3a係展示半導體晶粒182的中央區域128沒有複合的互連結構168。圖3b係展示一或多行的複合的互連結構168將半導體晶粒182的中央區域128區分成為第一區域128a以及第二區域128b。圖3c係展示一或多列的複合的互連結構168將半導體晶粒182的第一區域128a區分成為區域128c及區域128d並且將第二 區域128b區分成為區域128e及區域128f。半導體晶粒182的區域128a-128f的一部分係沒有複合的互連結構168，以便於在一後續的處理步驟中容納被設置在該半導體晶粒之上的較小的半導體晶粒。半導體晶粒182的區域128a-128f的沒有複合的互連結構168的部分係對應於在一後續的處理步驟中將被設置在半導體晶粒182之上的較小的半導體晶粒的覆蓋區。
圖4a-4f係相關於圖1來描繪一形成一薄化的半導體晶粒的製程，該薄化的半導體晶粒係具有一小於半導體晶粒182的中央區域128的覆蓋區。圖4a係展示一類似於半導體晶圓120的半導體晶圓190，其具有一主體基板材料192，例如矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、矽碳化物、或是其它用於結構的支撐之基體半導體材料。複數個半導體晶粒或構件194係形成在晶圓190上，其係藉由一如上所述的非主動晶粒間的晶圓區域或切割道196來加以分開。切割道196係提供切割區域以單粒化半導體晶圓190成為個別的半導體晶粒194。在一實施例中，半導體晶圓190係具有一100-450mm的寬度或直徑。半導體晶粒194的覆蓋區係小於半導體晶粒182的中央區域128。半導體晶粒182的中央區域128係大於半導體晶粒182的覆蓋區。
圖4b係展示半導體晶圓190的一部分的橫截面圖。半導體晶圓190係具有一最初的厚度T3。每個半導體晶粒194係具有一背面或非主動表面198以及包含類比或數位電路的主動表面200，該些類比或數位電路係被實施為形成在晶粒內之主動元件、被動元件、導電層及介電層並且根據該晶粒的電性設計及功能而電互連。例如，該電路可包含形成在主動表面200內之一或多個電晶體、二極體以及其它電路元件，以實施類比電路 或數位電路，例如DSP、ASIC、記憶體、或是其它信號處理電路。半導體晶粒194亦可包含IPD，例如電感器、電容器及電阻器，以用於RF信號處理。
一導電層202係利用PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它適合的金屬沉積製程以形成在主動表面200之上。導電層202可以是一或多層的Al、Cu、Sn、Ni、Au、Ag、或是其它適當的導電材料。導電層202係運作為電連接至在主動表面200上的電路之接觸墊。導電層202可被形成為接觸墊，該些接觸墊係與半導體晶粒194的邊緣相隔一第一距離並排地加以設置，即如同在圖4b中所示者。或者是，導電層202可被形成為接觸墊，該些接觸墊係以多個列加以偏置，使得一第一列的接觸墊係與該晶粒的邊緣相隔一第一距離來加以設置，並且一和該第一列交錯的第二列的接觸墊係與該晶粒的邊緣相隔一第二距離加以設置。
一絕緣或保護層204係利用PVD、CVD、網版印刷、旋轉塗覆、噴霧塗覆、燒結、或是熱氧化以形成在主動表面200及導電層202之上。該絕緣層204係包含一或多層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是其它具有類似絕緣及結構的性質之材料。該絕緣層204係覆蓋並且提供保護給主動表面200。絕緣層204的一部分係藉由蝕刻、LDA、或是其它適當的製程來加以移除以露出導電層202，以用於後續的電互連。
在圖4c中，半導體晶圓190係進行電性測試及檢查，以作為一品質管制製程的部分。人工視覺的檢查以及自動化的光學系統係被用來對於半導體晶圓190執行檢查。軟體可被利用在半導體晶圓190的自動化光學分析中。視覺的檢查方法可以利用例如是一掃描式電子顯微鏡、高強 度或紫外線的光、或是金相顯微鏡的設備。半導體晶圓190係針對於包含翹曲、厚度變化、表面微粒、不規則性、裂縫、脫層、以及變色之結構的特徵來加以檢查。
在半導體晶粒194內的主動及被動構件係在晶圓層級下對於電性效能及電路功能進行測試。每個半導體晶粒194係針對於功能及電性參數，利用一探針或是其它測試裝置而被測試。測試探針頭212係包含複數個探針210。探針210係被用來與在每個半導體晶粒194上的接觸墊202做成電性接觸，並且提供電性刺激至該些接觸墊。半導體晶粒194係響應該些電性刺激，此係藉由電腦測試系統214來加以量測並且相較於一預期的響應，以測試該半導體晶粒的功能。該電性測試可包含電路功能、引線完整性、電阻率、連續性、可靠度、接面深度、ESD、RF效能、驅動電流、臨界電流、漏電流、以及該構件類型特有的操作參數。半導體晶圓190的該檢查及電性測試係使得通過而被標明為已知良好的晶粒(KGD)的半導體晶粒194能夠用於一半導體封裝。
在圖4d中，一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落、或是網版印刷製程以沉積在接觸墊202之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料、或是無鉛的焊料。該凸塊材料係利用一適當的安裝或接合製程而被接合到接觸墊202。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊216。在某些應用中，凸塊216係被回焊第二次，以改善至接觸墊202的電性接觸。凸塊216亦可以被壓縮接合或是熱壓接合 到接觸墊202。凸塊216係代表一種可被形成在接觸墊202之上的互連結構類型。該互連結構亦可以使用柱形凸塊、微凸塊、或是其它電互連。凸塊216係電連接至半導體晶粒194的接觸墊202。
在圖4e中，一保護塗層220係形成在橫跨半導體晶圓190的整個區域的絕緣層204及凸塊216之上。保護塗層220可以是一或多層藉由網版印刷、旋轉塗覆、噴霧塗覆、或是其它適當的沉積製程所施加的一種水溶性的聚合物材料。一疊層帶222係被施加在橫跨半導體晶圓190的整個區域的保護塗層220之上。在一實施例中，疊層帶222係包含一介電基底膜222a以及黏著層222b，即如同在圖4e中的半導體晶圓190的一部分的橫截面圖中所示。
在圖4e中，半導體晶圓190的背表面198係受到一利用研磨機224的背面研磨操作或是其它適當的機械式或蝕刻製程，以移除基底材料192的一部分並且降低該基底材料至一小於厚度T3的厚度T4。基底材料192從背表面198的移除係被執行為一機械式製程或是物理蝕刻製程，此係留下橫跨該半導體晶圓的整個寬度都為均勻的半導體晶圓190的新的背表面226。或者是，基底材料192的一部分係藉由LDA以從背表面198來加以移除，以露出新的背表面226。在一實施例中，在該背面研磨或晶圓薄化操作之後，半導體晶圓190係具有一30-50μm的厚度T4。在另一實施例中，在該背面研磨或晶圓薄化操作之後，半導體晶圓120係具有一約100μm的厚度T4。在該背面研磨或晶圓薄化操作之後，半導體晶圓190的厚度T4係小於半導體晶粒182之複合的互連結構168的高度H2。在絕緣層204及凸塊216之上的保護塗層220係降低在該背面研磨或晶圓薄化操作以及後續的 製程期間的切損以及碎片及污染物在主動表面200上的累積。於是，保護塗層220係在圖4e的背面研磨或晶圓薄化操作之前被施加在絕緣層204及凸塊216之上。
在圖4f中，在絕緣層204及凸塊216之上的保護塗層220係藉由一剝離或剝除操作來加以移除。半導體晶圓190係透過切割道196利用鋸刀或雷射切割工具228而被單粒化成為個別的凸塊化(bumped)半導體晶粒230。半導體晶粒230係透過接觸墊202而電連接至凸塊216，以用於外部的互連。半導體晶粒230係具有小於半導體晶粒182之複合的互連結構168的高度H2的厚度T4。半導體晶粒182之複合的互連結構168的高度H2係大於半導體晶粒230的厚度T4。半導體晶粒230的覆蓋區係小於半導體晶粒182的中央區域128。具有小於半導體晶粒182之複合的互連結構168的高度H2的厚度T4以及小於半導體晶粒182的中央區域128的覆蓋區之半導體晶粒230將可裝設在半導體晶粒182的中央區域128之下。半導體晶粒182係在一後續的處理步驟中被設置在半導體晶粒230之上。半導體晶粒230可以對於單粒化後的KGD的識別來加以檢查並且電性地測試。
圖5a-5i係相關於圖1來描繪一形成具有堆疊的薄化的半導體晶粒之單側FO-WLCSP的製程。圖5a係展示一基板或載體240，其係包含臨時或犧牲的基底材料，例如矽、聚合物、鈹氧化物、玻璃、或是其它用於結構的支撐之適當的低成本剛性材料。一介面層或雙面帶242係形成在載體240之上，以作為一臨時的黏著接合膜、蝕刻停止層或是熱釋放層。
在圖5b中，來自圖4f的半導體晶粒230係在主動表面200被定向朝向該載體下，利用例如一拾放操作而被安裝到載體240及介面層 242。半導體晶粒230係具有小於半導體晶粒182之複合的互連結構168的高度H2的厚度T4。半導體晶粒230的覆蓋區係小於半導體晶粒182的中央區域128。
在設置來自圖4f的半導體晶粒230之後，如同在圖5c中所示，來自圖2l的半導體晶粒182係在主動表面134被定向朝向該載體下，利用例如一拾放操作而被安裝到載體240及介面層242並且在半導體晶粒230之上。半導體晶粒230係具有小於半導體晶粒182之複合的互連結構168的高度H2的厚度T4。半導體晶粒230係具有一小於半導體晶粒182的中央區域128的覆蓋區。於是，半導體晶粒230係被設置在半導體晶粒182的中央區域128之上。半導體晶粒182的中央區域128的一部分係沒有複合的互連結構168，以便於容納被設置在半導體晶粒182之上的較小的半導體晶粒230。半導體晶粒182的中央區域128的沒有複合的互連結構168的部分係對應於設置在半導體晶粒182之上的較小的半導體晶粒230的覆蓋區。半導體晶粒230係被設置在半導體晶粒182的中央區域128以及載體240之間。半導體晶粒182的主動表面134係被定向朝向半導體晶粒230的背表面226。複合的互連結構168係位在半導體晶粒182的週邊區域130中，以在不使用TSV或THV之下提供半導體晶粒182至該單側FO-WLCSP的連接性。於是，該單側FO-WLCSP係能夠藉由消除TSV及THV以達成較低的成本、較高的UPH製造以及增高的裝置可靠度。半導體晶粒182之複合的互連結構168係包圍或圍繞半導體晶粒230。半導體晶粒230係被設置在半導體晶粒182之複合的互連結構168之間。複合的互連結構168係具有一高度H2大於薄化的半導體晶粒230的一厚度T4。圖5d係展示半導體晶粒182及 230安裝到載體240的介面層242，以作為重組或是重新配置的晶圓244。
在圖5e中，一種囊封體或模製化合物250係利用一膏印刷、壓縮模製、轉移模製、液體囊封體模製、真空疊層或是其它適當的施用器以沉積在半導體晶粒182、半導體晶粒230以及載體240之上。囊封體250可以是聚合物複合材料，例如具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適當的填充物的聚合物。囊封體250是不導電的，並且在環境上保護該半導體裝置免於外部的元素及污染物。在一實施例中，囊封體250係利用膜輔助的模製製程來加以沉積。囊封體250的表面246可以進行一選配的研磨操作以平坦化該囊封體的表面並且降低該囊封體的厚度。研磨囊封體250的表面246以降低該囊封體的厚度係降低最終的半導體裝置的整體厚度，因此使得該最終的半導體裝置能夠被利用在需要一降低的厚度的應用中。減少該最終的半導體裝置的厚度係增加市場對於該最終的半導體裝置之需求。
在圖5f中，載體240及介面層242係藉由化學蝕刻、機械式剝離、CMP、機械式研磨、熱烘烤、UV光、雷射掃描、或是濕式剝除來加以移除。移除載體240及介面層242係露出囊封體250、半導體晶粒230的主動表面200及凸塊216、以及半導體晶粒182之複合的互連結構168。半導體晶粒182之複合的互連結構168係包圍或圍繞半導體晶粒230的主動表面200及凸塊216。半導體晶粒230的主動表面200及凸塊216係藉由半導體晶粒182之複合的互連結構168加以劃定界線。半導體晶粒182之複合的互連結構168係形成在半導體晶粒182的週邊區域130中，而半導體晶粒230係被設置在半導體晶粒182的中央區域128之上。
在圖5g中，一堆積的互連結構252係形成在重組晶圓244之上。堆積的互連結構252係包含一利用一圖案化及金屬沉積製程，例如是濺鍍、電解的電鍍、以及無電的電鍍所形成的導電層或RDL 254。導電層254可以是一或多層的Al、Cu、Sn、Ni、Au、Ag、或是其它適當的導電材料。導電層254的一部分係電連接至半導體晶粒230的接觸墊202。導電層254的另一部分係電連接至半導體晶粒182之複合的互連結構168。根據該最終的半導體裝置的設計及功能，導電層254的其它部分可以是電性共通或是電性隔離的。堆積的互連結構252進一步包含一形成在導電層254之間以用於電性隔離的絕緣或保護層256。絕緣層256係包含一或多層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是其它具有類似絕緣及結構的性質之材料。絕緣層256係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、燒結或是熱氧化來加以形成。絕緣層256的一部分係藉由一蝕刻製程來加以移除以露出導電層254，以用於凸塊的形成或是額外的封裝互連。
在圖5h中，凸塊係形成在導電層254之上。一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落、或是網版印刷製程以沉積在導電層254之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料、或是無鉛的焊料。該凸塊材料係利用一適當的安裝或接合製程而被接合到導電層254。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球狀的球或凸塊260。在某些應用中，凸塊260係被回焊第二次，以改善至導電層254的電性接觸。在一實施例中，凸塊260係形成在一具有一潤濕層、阻障層以及黏著層的 凸塊底部金屬化(UBM)之上。該些凸塊亦可以被壓縮接合或是熱壓接合到導電層254。凸塊260係電連接至導電層254。凸塊260係代表一種可被形成在導電層254之上的互連結構類型。該互連結構亦可以使用接合線、導電膏、柱形凸塊、微凸塊、或是其它電互連。重組晶圓244係透過囊封體250利用鋸刀或雷射切割工具262而被單粒化成為個別的單側FO-WLCSP 264。
圖5i係展示具有堆疊的薄化的半導體晶粒182及230之單側FO-WLCSP 264。半導體晶粒182的導電層150係將信號從中央區域128繞線至週邊區域130，此係容許中央區域128的一部分能夠沒有複合的互連結構168，以便容納與較小的半導體晶粒230的堆疊。半導體晶粒182的中央區域128維持沒有複合的互連結構168的部分係對應於設置在半導體晶粒182之上的較小的半導體晶粒230的覆蓋區。半導體晶粒182係透過接觸墊136而電連接至導電層150。導電層150係將在半導體晶粒182的中央區域128中的接觸墊136的信號繞線離開至該半導體晶粒的週邊區域130。半導體晶粒182的導電層150係電連接至導電層160。導電層160係位在半導體晶粒182的週邊區域130中。半導體晶粒182的中央區域128的一部分係沒有導電層160。半導體晶粒182的中央區域128的沒有導電層160的部分係對應於設置在半導體晶粒182之上的較小的半導體晶粒230的覆蓋區。半導體晶粒182的導電層160係電連接至導電柱164。導電柱164係位在半導體晶粒182的週邊區域130中。半導體晶粒182的中央區域128的一部分係沒有導電柱164。半導體晶粒182的中央區域128的沒有導電柱164的部分係對應於設置在半導體晶粒182之上的較小的半導體晶粒230的覆蓋區。半導體晶粒182的導電柱164係電連接至凸塊蓋166。凸塊蓋166係位在半導體 晶粒182的週邊區域130中。半導體晶粒182的中央區域128的一部分係沒有凸塊蓋166。半導體晶粒182的中央區域128的沒有凸塊蓋166的部分係對應於設置在半導體晶粒182之上的較小的半導體晶粒230的覆蓋區。導電柱164及凸塊蓋166的組合係構成一具有一非可熔的部分(導電柱164)以及一可熔的部分(凸塊蓋166)之複合的互連結構168。複合的互連結構168係電連接至導電層160。半導體晶粒182係透過接觸墊136、導電層150、導電層160以及複合的互連結構168而電連接至導電層254的一部分，以用於外部的互連。半導體晶粒230係透過接觸墊202及凸塊216而電連接至導電層254的一部分，以用於外部的互連。導電層254的一部分係電連接至半導體晶粒230的凸塊216。導電層254的另一部分係電連接至半導體晶粒182之複合的互連結構168。根據單側FO-WLCSP 264的設計及功能，導電層254的其它部分可以是電性共通或是電性隔離的。凸塊260係電連接至導電層254。單側FO-WLCSP 264係在不使用TSV及THV下，提供從半導體晶粒182及半導體晶粒230透過導電層254而至外部的互連之單側連接性，此係節省相當大量的時間及費用。避免TSV及THV的使用係增加該UPH製造並且降低成本。再者，避免TSV及THV的使用係消除會降低裝置可靠度的空孔(void)的形成，並且消除有關半導體晶粒設置正確性以及和穿孔的形成相關的翹曲控制之問題。囊封體250以及半導體晶粒182及230的薄化係容許在單側FO-WLCSP 264的厚度上的縮減。半導體晶粒182及230的堆疊係容許單側FO-WLCSP 264的覆蓋區之顯著的縮減。在單側FO-WLCSP 264的封裝厚度及覆蓋區上的縮減係增加適合單側FO-WLCSP 264的應用的數目，因此增加市場對於該半導體裝置的需求。
在另一實施例中，從圖5b繼續，圖6a-6g係相關於圖1來描繪一形成具有半導體封裝及薄化的半導體晶粒之單側fo-WLCSP之替代的製程。在設置來自圖4f的半導體晶粒230之後，如同在圖6a中所示，一半導體封裝或裝置270係在凸塊272被定向朝向該載體下，利用例如一拾放操作而被安裝到載體240及介面層242並且在半導體晶粒230之上。半導體裝置270可包含濾波器、記憶體、或是其它IC晶片、處理器、微控制器、已知良好的封裝、或是任何其它包含半導體晶粒或其它電子裝置或電路之封裝的裝置。凸塊272係具有大於薄化的半導體晶粒230的厚度T4之高度H3。凸塊272係代表一種可被形成在半導體裝置270之上的互連結構類型。該互連結構亦可以使用導電柱、導電膏、堆疊的柱形凸塊、或是其它電互連。半導體裝置270的中央區域274的一部分係沒有凸塊272，以便於容納設置在半導體裝置270之上的較小的半導體晶粒230。半導體裝置270的中央區域274的沒有凸塊272的部分係對應於設置在半導體裝置270之上的較小的半導體晶粒230的覆蓋區。半導體晶粒230係被設置在半導體裝置270的中央區域274以及載體240之間。凸塊272係位在半導體裝置270的週邊區域276中，以在不利用TSV及THV下提供在半導體裝置270的電路以及該單側fo-WLCSP之間的連接性。避免TSV及THV的使用係增加該UPH製造並且降低成本。再者，避免TSV及THV的使用係消除會降低裝置可靠度的空孔的形成，並且消除有關半導體晶粒設置正確性以及和穿孔的形成相關的翹曲控制之問題。半導體裝置270的凸塊272係包圍或圍繞半導體晶粒230。半導體晶粒230係被設置在半導體裝置270的凸塊272之間。圖6b係展示半導體裝置270及半導體晶粒230被安裝到載體240的介面層242，以 作為重組或重新配置的晶圓280。
在圖6c中，一種囊封體或模製化合物282係利用一膏印刷、壓縮模製、轉移模製、液體囊封體模製、真空疊層或是其它適當的施用器以沉積在半導體裝置270、半導體晶粒230以及載體240之上。囊封體282可以是聚合物複合材料，例如具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適當的填充物的聚合物。囊封體282是不導電的，並且在環境上保護該半導體裝置免於外部的元素及污染物。在一實施例中，囊封體282係利用膜輔助的模製製程來加以沉積的。囊封體282的表面284可以進行一選配的研磨操作，以平坦化該囊封體的表面並且降低該囊封體的厚度。研磨囊封體282的表面284以降低該囊封體的厚度係降低該最終的半導體裝置的整體厚度，因此使得該最終的半導體裝置能夠被利用在需要一降低厚度的應用中。減少該最終的半導體裝置的厚度係增加市場對於該最終的半導體裝置之需求。
在圖6d中，載體240及介面層242係藉由化學蝕刻、機械式剝離、CMP、機械式研磨、熱烘烤、UV光、雷射掃描、或是濕式剝除來加以移除。移除載體240及介面層242係露出半導體晶粒230的主動表面200及凸塊216以及半導體裝置270的凸塊272。半導體裝置270的凸塊272係包圍或圍繞半導體晶粒230的主動表面200及凸塊216。半導體晶粒230的主動表面200及凸塊216係藉由半導體裝置270的凸塊272所劃定界線。半導體裝置270的凸塊272係形成在半導體裝置270的週邊區域276中，而半導體晶粒230係被設置在半導體裝置270的中央區域274之上。
在圖6e中，一堆積的互連結構290係形成在重組晶圓280 之上。堆積的互連結構290係包含一利用一圖案化及金屬沉積製程，例如是濺鍍、電解的電鍍、以及無電的電鍍所形成的導電層或RDL 292。導電層292可以是一或多層的Al、Cu、Sn、Ni、Au、Ag、或是其它適當的導電材料。導電層292的一部分係電連接至半導體晶粒230的接觸墊202。導電層292的另一部分係電連接至半導體裝置270的凸塊272。根據該最終的半導體裝置的設計及功能，導電層292的其它部分可以是電性共通或是電性隔離的。堆積的互連結構290進一步包含一形成在導電層292之間以用於電性隔離的絕緣或保護層294。絕緣層294係包含一或多層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是其它具有類似絕緣及結構的性質之材料。絕緣層294係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、燒結或是熱氧化來加以形成。絕緣層294的一部分係藉由一蝕刻製程來加以移除以露出導電層292，以用於凸塊的形成或是額外的封裝互連。
在圖6f中，凸塊係形成在導電層292之上。一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落、或是網版印刷製程以沉積在導電層292之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料、或是無鉛的焊料。該凸塊材料係利用一適當的安裝或接合製程而被接合到導電層292。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球狀的球或凸塊296。在某些應用中，凸塊296係被回焊第二次，以改善至導電層292的電性接觸。在一實施例中，凸塊296係形成在一具有一潤濕層、阻障層及黏著層的UBM之上。該些凸塊亦可以被壓縮接合或是熱壓接合到導電層292。凸塊296係 電連接至導電層292。凸塊296係代表一種可被形成在導電層292之上的互連結構類型。該互連結構亦可以使用接合線、導電膏、柱形凸塊、微凸塊、或是其它電互連。重組晶圓280係透過囊封體282利用鋸刀或雷射切割工具298而被單粒化成為個別的單側fo-WLCSP 300。
圖6g係展示具有堆疊的薄化的半導體晶粒230及半導體裝置270之單側fo-WLCSP 300。半導體裝置270的中央區域274的一部分係沒有凸塊272，以便於容納與較小的半導體晶粒230的堆疊。凸塊272係在不使用TSV及THV下，提供從半導體裝置270至單側fo-WLCSP 300的連接性，此係節省相當大量的時間及費用。半導體裝置270可包含濾波器、記憶體、或是其它IC晶片、處理器、微控制器、已知良好的封裝、或是任何其它包含半導體晶粒或其它電子裝置或電路之封裝的裝置。半導體裝置270係電連接至凸塊272以用於外部的互連。半導體晶粒230係透過接觸墊202而電連接至凸塊216，以用於外部的互連。導電層292的一部分係電連接至半導體晶粒230的接觸墊202。導電層292的另一部分係電連接至半導體裝置270的凸塊272。凸塊296係電連接至導電層292。單側fo-WLCSP 300係在不使用TSV及THV下，提供從半導體晶粒230及半導體裝置270透過導電層292至外部的互連之單側連接性，此係節省相當大量的時間及費用。避免TSV及THV的使用係增加該UPH製造並且降低成本。再者，避免TSV及THV的使用係消除會降低裝置可靠度的空孔的形成，並且消除有關半導體晶粒設置正確性以及和穿孔的形成相關的翹曲控制之問題。囊封體282及半導體晶粒230的薄化係容許在單側fo-WLCSP 300的厚度上的縮減。半導體晶粒230及半導體裝置270的堆疊係容許單側fo-WLCSP 300的覆蓋區 之顯著的縮減。在單側fo-WLCSP 300的封裝厚度及覆蓋區上的縮減係增加適合單側fo-WLCSP 300的應用的數目，因此增加市場對於該半導體裝置之需求。
儘管本發明的一或多個實施例已經詳細地描述，但是本領域技術人員將會體認到對於該些實施例的修改及調適可以在不脫離如同在以下的申請專利範圍中所闡述之本發明的範疇下來加以完成。
122‧‧‧主體基板材料
128‧‧‧中央區域
130‧‧‧週邊區域
134‧‧‧主動表面
136‧‧‧導電層/節點/接觸墊
138‧‧‧絕緣層/保護層
150‧‧‧導電層/RDL
152‧‧‧絕緣層/保護層
160‧‧‧導電層
164‧‧‧導電柱
166‧‧‧凸塊蓋
168‧‧‧複合的互連結構
176‧‧‧背表面
182‧‧‧半導體晶粒
192‧‧‧主體基板材料
200‧‧‧主動表面
202‧‧‧導電層/接觸墊
204‧‧‧絕緣層/保護層
216‧‧‧球/凸塊
226‧‧‧背表面
230‧‧‧半導體晶粒
250‧‧‧囊封體/模製化合物
252‧‧‧堆積的互連結構
254‧‧‧導電層/RDL
256‧‧‧絕緣層/保護層
260‧‧‧球/凸塊
264‧‧‧單側FO-WLCSP
H2‧‧‧高度
T4‧‧‧厚度

Claims (15)

  1. 一種製造一半導體裝置之方法，其係包括：提供一第一半導體晶粒；在該第一半導體晶粒的一週邊區域中形成複數個互連結構；以及在該些互連結構之間的該第一半導體晶粒之上設置一第二半導體晶粒。
  2. 如申請專利範圍第1項之方法，其進一步包含在該第一半導體晶粒的一中央區域以及該第一半導體晶粒的該週邊區域之間形成一導電層。
  3. 如申請專利範圍第1項之方法，其進一步包含在該第一半導體晶粒以及第二半導體晶粒之上形成一重新分佈層。
  4. 如申請專利範圍第1項之方法，其進一步包含：提供一包含該第一半導體晶粒的半導體晶圓；以及移除該半導體晶圓的一部分至一30至100微米的厚度。
  5. 如申請專利範圍第4項之方法，其進一步包含在移除該半導體晶圓的該部分之前形成該些互連結構。
  6. 一種製造一半導體裝置之方法，其係包括：提供一第一半導體晶粒；形成一第一互連結構以及一第二互連結構；以及將一第二半導體晶粒設置在該第一互連結構以及該第二互連結構之間的該第一半導體晶粒之上。
  7. 如申請專利範圍第6項之方法，其進一步包含在形成該第一互連結構之後移除該第一半導體晶粒的一部分。
  8. 如申請專利範圍第6項之方法，其中形成該第一互連結構進一步包含：在該第一半導體晶粒的一週邊區域中形成一第一導電柱；以及在該導電柱之上形成一凸塊。
  9. 如申請專利範圍第6項之方法，其進一步包含在該第一半導體晶粒的一中央區域以及該第一半導體晶粒的一週邊區域之間形成一導電層。
  10. 如申請專利範圍第6項之方法，其進一步包含在該第一半導體晶粒的一中央區域之上設置該第二半導體晶粒。
  11. 一種半導體裝置，其係包括：一第一半導體晶粒；一第一互連結構以及一第二互連結構，其形成在該第一半導體晶粒的一週邊區域中；以及一第二半導體晶粒，其設置在該第一互連結構以及該第二互連結構之間的該第一半導體晶粒之上。
  12. 如申請專利範圍第11項之半導體裝置，其進一步包含該第二半導體晶粒的一高度是小於該第一互連結構的一高度。
  13. 如申請專利範圍第11項之半導體裝置，其進一步包含該第二半導體晶粒的一覆蓋區是小於該第一半導體晶粒的一中央區域。
  14. 如申請專利範圍第11項之半導體裝置，其中該第一互連結構進一步包含：一形成在該第一半導體晶粒的該週邊區域中的導電柱；以及一形成在該導電柱之上的凸塊。
  15. 如申請專利範圍第14項之半導體裝置，其進一步包含一形成在該第一半導體晶粒以及第二半導體晶粒之上的重新分佈層。
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