TWI588956B - 形成在扇出晶圓級晶片尺寸封裝中的雙側互連結構的半導體裝置和方法 - Google Patents

形成在扇出晶圓級晶片尺寸封裝中的雙側互連結構的半導體裝置和方法 Download PDF

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TWI588956B
TWI588956B TW102122923A TW102122923A TWI588956B TW I588956 B TWI588956 B TW I588956B TW 102122923 A TW102122923 A TW 102122923A TW 102122923 A TW102122923 A TW 102122923A TW I588956 B TWI588956 B TW I588956B
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interconnect structure
substrate
conductive layer
layer
semiconductor die
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TW102122923A
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TW201411791A (zh
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林耀劍
陳康
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史達晶片有限公司
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Description

形成在扇出晶圓級晶片尺寸封裝中的雙側互連結構的半導體裝置和方法
本發明係大致有關於半導體裝置，並且更具體而言係有關於一種在扇出晶圓級晶片尺寸封裝中形成雙側的互連結構之半導體裝置和方法。
優先權主張
本申請案係主張2012年9月14日申請的美國臨時申請案號61/701,366的利益，該申請案係被納入在此作為參考。
相關申請案交互參照
本申請案係相關於美國專利申請案序號13/832,118、代理人文件號2515.0424之名稱為“在載體上形成用於過渡階段測試的積層的互連結構之半導體裝置和方法”。本申請案係進一步相關於美國專利申請案序號13/832,205、代理人文件號2515.0408之名稱為“形成在扇出晶圓級晶片尺寸封裝中的雙側互連結構的半導體裝置和方法”。
半導體裝置係常見於現代的電子產品中。半導體裝置係在電氣構件的數目及密度上變化。離散的半導體裝置一般包含一類型的電氣構件，例如，發光二極體(LED)、小信號電晶體、電阻器、電容器、電感器、 以及功率金屬氧化物半導體場效電晶體(MOSFET)。集積的半導體裝置通常包含數百到數百萬個電氣構件。集積的半導體裝置的例子係包含微控制器、微處理器、電荷耦合裝置(CCD)、太陽能電池、以及數位微鏡裝置(DMD)。
半導體裝置係執行廣範圍的功能，例如，信號處理、高速的計算、傳送及接收電磁信號、控制電子裝置、轉換太陽光成為電力、以及產生用於電視顯示器的視覺投影。半導體裝置係見於娛樂、通訊、電力轉換、網路、電腦以及消費者產品的領域中。半導體裝置亦見於軍事的應用、航空、汽車、工業用的控制器、以及辦公室設備。
半導體裝置係利用半導體材料的電氣特性。半導體材料的結構係容許其導電度能夠藉由一電場或基極電流的施加或是透過摻雜的製程來加以操縱。摻雜係將雜質帶入半導體材料中，以操縱及控制半導體裝置的導電度。
一半導體裝置係包含主動及被動的電性結構。包含雙載子及場效電晶體的主動結構係控制電流的流動。藉由改變摻雜的程度以及一電場或基極電流的施加，該電晶體不是提升、就是限制電流的流動。包含電阻器、電容器及電感器的被動結構係在電壓及電流之間產生執行各種電氣功能所必要的一種關係。該被動及主動結構係電連接以形成電路，此係使得該半導體裝置能夠執行高速的計算及其它有用的功能。
半導體裝置一般是利用兩個複雜的製程，亦即，前端製造及後端製造來加以製造，每個製造潛在涉及數百道步驟。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。每個半導體晶粒通常是相同的，並且包含藉由電連接主動及被動構件所形成的電路。後端製造係牽涉 到從完成的晶圓單粒化(singulating)個別的半導體晶粒並且封裝該晶粒以提供結構的支撐以及環境的隔離。如同在此所用的術語“半導體晶粒”係指該字的單數與複數形兩者，並且於是可以指稱單一半導體裝置及多個半導體裝置兩者。
半導體製造的一目標是產出較小的半導體裝置。較小的裝置通常消耗較低的功率，具有較高的效能，並且可以更有效率地加以生產。此外，較小的半導體裝置具有一較小的覆蓋區，此係較小的終端產品所期望的。較小的半導體晶粒尺寸可藉由在產生具有較小且較高密度的主動及被動構件之半導體晶粒的前端製程中的改良來達成。後端製程可以藉由在電互連及囊封體上的改良來產生具有較小覆蓋區的半導體裝置封裝。
在扇出晶圓級晶片尺寸封裝(Fo-WLCSP)中，半導體晶粒經常需要一頂端及底部積層的互連結構以用於電連接至外部的裝置。該些積層的互連結構通常是逐層的形成在該Fo-WLCSP的兩側上。由於工業標準的暫時接合製程的關係，該些積層的互連結構之逐層的形成會需要長的週期時間以及高的製造成本。該暫時的接合可能會降低製造良率且增加缺陷。
對於一種在一扇出晶圓級晶片尺寸封裝(Fo-WLCSP)中之簡單且符合成本效益的雙側的互連結構存在著需求。於是，在一實施例中，本發明是一種製造一半導體裝置之方法，其係包括下列步驟：提供一基板，該基板係包含形成在該基板的第一及第二相對的表面之上的第一及第二導電層，在該基板之上形成複數個導線柱，在該些導線柱之間安裝一半導體晶粒至該基板，在該半導體晶粒之上形成一第一互連結構，在該基板、半 導體晶粒及第一互連結構之上沉積一第一囊封體，以及在該第一囊封體以及第一互連結構之上形成一第二互連結構，並且該第二互連結構係電耦接至該導線柱。
在另一實施例中，本發明是一種製造一半導體裝置之方法，其係包括下列步驟：提供一基板，在該基板之上形成一垂直的互連結構，安裝一半導體晶粒至該基板，在該半導體晶粒之上形成一第一互連結構，在該基板以及半導體晶粒之上沉積一第一囊封體，以及在該第一囊封體以及第一互連結構之上形成一第二互連結構。
在另一實施例中，本發明是一種製造一半導體裝置之方法，其係包括下列步驟：提供一第一互連結構，提供一半導體晶粒，在該半導體晶粒之上形成一保護層，安裝該半導體晶粒至該第一互連結構，在該第一互連結構之上形成複數個柱形凸塊，在該第一互連結構以及半導體晶粒之上沉積一種囊封體，移除該保護層以露出該半導體晶粒，以及在該囊封體以及半導體晶粒之上形成一第二互連結構。
在另一實施例中，本發明是一種半導體裝置，其係包括一基板以及形成在該基板之上的垂直的互連結構。一半導體晶粒係被安裝至該基板。一第一互連結構係形成在該半導體晶粒之上。一第一囊封體係沉積在該基板以及半導體晶粒之上。一第二互連結構係形成在該第一囊封體以及第一互連結構之上。
50‧‧‧電子裝置
52‧‧‧印刷電路板(PCB)
54‧‧‧信號線路
56‧‧‧接合線封裝
58‧‧‧覆晶
60‧‧‧球格陣列(BGA)
62‧‧‧凸塊晶片載體(BCC)
64‧‧‧雙排型封裝(DIP)
66‧‧‧平台柵格陣列(LGA)
68‧‧‧多晶片模組(MCM)
70‧‧‧四邊扁平無引腳封裝(QFN)
72‧‧‧四邊扁平封裝
74‧‧‧半導體晶粒
76‧‧‧接觸墊
78‧‧‧中間載體
80‧‧‧導線
82‧‧‧接合線
84‧‧‧囊封體
88‧‧‧半導體晶粒
90‧‧‧載體
92‧‧‧底膠填充(環氧樹脂黏著材料)
94‧‧‧接合線
96、98‧‧‧接觸墊
100‧‧‧模製化合物(囊封體)
102‧‧‧接觸墊
104‧‧‧凸塊
106‧‧‧中間載體
108‧‧‧主動區
110、112‧‧‧凸塊
114‧‧‧信號線
116‧‧‧模製化合物(囊封體)
120‧‧‧晶圓
122‧‧‧主體基板材料
124‧‧‧半導體晶粒(構件)
126‧‧‧切割道
128‧‧‧背表面
130‧‧‧主動表面
132‧‧‧導電層
134‧‧‧絕緣(鈍化)層
136‧‧‧雷射
137‧‧‧研磨機
138‧‧‧晶粒附接黏著膜(帶)
139‧‧‧鋸刀(雷射切割工具)
140‧‧‧核心基板
144‧‧‧導電的貫孔
146‧‧‧導電層(重新分配層(RDL))
148‧‧‧絕緣(鈍化)層
150‧‧‧導電層(RDL)
152‧‧‧絕緣(鈍化)層
154‧‧‧雷射
155‧‧‧中介體基板
156‧‧‧導線柱
156a‧‧‧基底部分
156b‧‧‧柄
158‧‧‧重組晶圓
160‧‧‧保護層
162‧‧‧囊封體
164‧‧‧積層的互連結構
166‧‧‧絕緣層
168‧‧‧導電層
170‧‧‧絕緣層
172‧‧‧導電層
174‧‧‧絕緣層
176‧‧‧鋸刀(雷射切割工具)
180‧‧‧載體(臨時的基板)
182‧‧‧介面層(雙面帶)
184‧‧‧可壓縮的黏著剝離膜
188‧‧‧囊封體(模製化合物)
190‧‧‧雷射
192‧‧‧研磨機
194‧‧‧支撐帶
196‧‧‧絕緣(鈍化)層
198‧‧‧導電層(RDL)
200‧‧‧絕緣(鈍化)層
202‧‧‧球(凸塊)
204‧‧‧積層的互連結構
208‧‧‧鋸刀(雷射切割工具)
210‧‧‧扇出晶圓級晶片尺寸封裝(Fo-WLCSP)
220‧‧‧載體
222‧‧‧可剝離的接合帶(永久的介電質接合層)
226‧‧‧囊封體(模製化合物)
228‧‧‧雷射
230‧‧‧絕緣(鈍化)層
232‧‧‧導電層(RDL)
234‧‧‧絕緣(鈍化)層
236‧‧‧球(凸塊)
238‧‧‧積層的互連結構
239‧‧‧鋸刀(雷射切割工具)
240‧‧‧扇出晶圓級晶片尺寸封裝(Fo-WLCSP)
242‧‧‧囊封體(模製化合物)
243‧‧‧雷射
244‧‧‧絕緣(鈍化)層
246‧‧‧導電層(RDL)
248‧‧‧絕緣(鈍化)層
250‧‧‧球(凸塊)
252‧‧‧積層的互連結構
254‧‧‧雷射
255‧‧‧鋸刀(雷射切割工具)
256‧‧‧扇出晶圓級晶片尺寸封裝(Fo-WLCSP)
262‧‧‧柱形凸塊
270‧‧‧扇出晶圓級晶片尺寸封裝(Fo-WLCSP)
272‧‧‧柱形凸塊
280‧‧‧扇出晶圓級晶片尺寸封裝(Fo-WLCSP)
282‧‧‧柱形凸塊
290‧‧‧扇出晶圓級晶片尺寸封裝(Fo-WLCSP)
292‧‧‧柱形凸塊
294‧‧‧遮罩層
300‧‧‧扇出晶圓級晶片尺寸封裝(Fo-WLCSP)
302‧‧‧引線架
304‧‧‧囊封體
306‧‧‧柱形凸塊
310‧‧‧載體(臨時的基板)
312‧‧‧絕緣(鈍化)層
314‧‧‧導電層(RDL)
316‧‧‧絕緣(鈍化)層
318‧‧‧雷射
320‧‧‧半導體晶粒
322‧‧‧背表面
324‧‧‧主動表面
326‧‧‧導電層
328‧‧‧絕緣(鈍化)層
330‧‧‧絕緣(鈍化)層
332‧‧‧保護層
334‧‧‧晶粒附接黏著劑
336‧‧‧柱形凸塊
338‧‧‧離散的半導體裝置
340‧‧‧導電膏
342‧‧‧囊封體(模製化合物)
350‧‧‧絕緣(鈍化)層
352‧‧‧導電層(RDL)
354‧‧‧絕緣(鈍化)層
356‧‧‧導電層(RDL)
358‧‧‧絕緣(鈍化)層
360‧‧‧球(凸塊)
362‧‧‧積層的互連結構
366‧‧‧雷射
370‧‧‧扇出晶圓級晶片尺寸封裝(Fo-WLCSP)
圖1係描繪一具有不同類型的封裝安裝到其表面的印刷電路板(PCB)； 圖2a-2c係描繪安裝到該PCB之代表性的半導體封裝的進一步細節；圖3a-3e係描繪一具有複數個藉由切割道分開的半導體晶粒之半導體晶圓；圖4a-4g係描繪一形成一中介體基板的製程，其中一半導體晶粒係安裝到該基板；圖5a-5h係描繪一在一Fo-WLCSP中形成一積層的互連結構以及該中介體基板以作為雙側的互連結構的製程；圖6係描繪根據圖5a-5h之具有雙側的互連結構的Fo-WLCSP；圖7a-7d係描繪另一在一Fo-WLCSP中形成一積層的互連結構以及該中介體基板以作為雙側的互連結構的製程；圖8係描繪根據圖7a-7d之雙側的互連結構的Fo-WLCSP；圖9a-9d係描繪另一在一Fo-WLCSP中形成一積層的互連結構以及該中介體基板以作為雙側的互連結構的製程；圖10係描繪根據圖9a-9d之雙側的互連結構的Fo-WLCSP；圖11係描繪在該些雙側的互連結構之間具有柱形凸塊的Fo-WLCSP；圖12係描繪具有沿著該中介體基板的側邊延伸的囊封體的Fo-WLCSP；圖13係描繪具有設置在半導體晶粒的主動表面的一部分上的囊封體的Fo-WLCSP；圖14係描繪在該互連結構之上具有一遮罩層的Fo-WLCSP；圖15係描繪具有一引線架以作為一互連結構的Fo-WLCSP；以及圖16a-16f係描繪一在一Fo-WLCSP中形成頂端及底部積層的互連結構的製程。
本發明係在以下參考該些圖式的說明中，以一或多個實施例來加以描述，其中相同的元件符號係代表相同或類似的元件。儘管本發明係以用於達成本發明之目的之最佳模式來加以描述，但熟習此項技術者將會體認到的是，其係欲涵蓋可內含在藉由所附的申請專利範圍及其由以下的揭露內容及圖式所支持的等同項所界定的本發明的精神與範疇內的替換物、修改以及等同物。
半導體裝置一般是利用兩個複雜的製程：前端製造及後端製造來加以製造。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。在該晶圓上的每個晶粒係包含電連接以形成功能電路的主動及被動電氣構件。例如是電晶體及二極體的主動電氣構件係具有控制電流的流動之能力。例如是電容器、電感器及電阻器的被動電氣構件係產生執行電路功能所必要的電壓及電流之間的一種關係。
被動及主動構件係藉由一系列的製程步驟而形成在半導體晶圓的表面之上，該些製程步驟包含摻雜、沉積、微影、蝕刻及平坦化。摻雜係藉由例如是離子植入或熱擴散的技術以將雜質帶入半導體材料中。該摻雜製程係修改主動元件中的半導體材料的導電度，其係藉由響應於一電場或基極電流來動態地改變該半導體材料的導電度。電晶體係包含具有不同類型及程度的摻雜的區域，該些區域係以使得該電晶體在電場或基極電流的施加時提升或限制電流的流動所必要的來加以配置。
主動及被動構件係藉由具有不同電氣特性的材料層來加以形成。該些層可藉由各種沉積技術來形成，該技術部分是由被沉積的材料 類型來決定的。例如，薄膜沉積可能牽涉到化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解的電鍍以及無電的電鍍製程。每個層一般是被圖案化，以形成主動構件、被動構件或是構件間的電連接的部分。
後端製造係指切割或單粒化完成的晶圓成為個別的半導體晶粒並且接著為了結構的支撐及環境的隔離來封裝該半導體晶粒。為了單粒化該半導體晶粒，晶圓係沿著該晶圓的非功能區域(稱為切割道或劃線)來加以劃線且截斷。該晶圓係利用一雷射切割工具或鋸刀而被單粒化。在單粒化之後，該個別的半導體晶粒係被安裝到一封裝基板，該封裝基板係包含用於和其它系統構件互連的接腳或接觸墊。形成在半導體晶粒之上的接觸墊係接著連接至該封裝內的接觸墊。該些電連接可以利用焊料凸塊、柱形凸塊、導電膏、或是接合線來做成。一囊封體或是其它模製材料係沉積在該封裝之上，以提供實體支撐及電氣隔離。該完成的封裝係接著被插入一電氣系統中，並且使得該半導體裝置的功能為可供其它系統構件利用的。
圖1係描繪具有複數個安裝於其表面上之半導體封裝的晶片載體基板或印刷電路板(PCB)52之電子裝置50。視應用而定，電子裝置50可具有一種類型之半導體封裝或多種類型之半導體封裝。不同類型之半導體封裝係為了說明之目的而展示於圖1中。
電子裝置50可以是一使用該些半導體封裝以執行一或多種電功能之獨立的系統。或者，電子裝置50可以是一較大系統之子構件。舉例而言，電子裝置50可以是行動電話、個人數位助理(PDA)、數位視訊攝影機(DVC)、或是其它電子通訊裝置的一部份。或者是，電子裝置50可以 是一可插入電腦中之顯示卡、網路介面卡或其它信號處理卡。該半導體封裝可包括微處理器、記憶體、特殊應用積體電路(ASIC)、邏輯電路、類比電路、RF電路、離散裝置或其它半導體晶粒或電氣構件。小型化及重量減輕是這些產品能夠被市場接受所不可少的。在半導體裝置間的距離必須縮短以達到更高的密度。
在圖1中，PCB 52係提供一般的基板以供安裝在該PCB上之半導體封裝的結構支撐及電性互連。導電的信號線路54係利用蒸鍍、電解的電鍍、無電的電鍍、網版印刷、或其它適合的金屬沉積製程而被形成在PCB 52的一表面之上或是在層內。信號線路54係提供在半導體封裝、安裝的構件、以及其它外部的系統構件的每一個之間的電通訊。線路54亦提供電源及接地連接給該些半導體封裝的每一個。
在某些實施例中，一半導體裝置係具有兩個封裝層級。第一層級的封裝是一種用於將半導體晶粒機械及電氣地附接至一中間載體的技術。第二層級的封裝係牽涉到將該中間載體機械及電性地附接至PCB。在其它實施例中，一半導體裝置可以只有該第一層級的封裝，其中晶粒是直接機械及電性地安裝到PCB上。
為了說明之目的，包含接合線封裝56及覆晶58之數種類型的第一層級的封裝係被展示在PCB 52上。此外，包含球格陣列(BGA)60、凸塊晶片載體(BCC)62、雙排型封裝(DIP)64、平台柵格陣列(LGA)66、多晶片模組(MCM)68、四邊扁平無引腳封裝(QFN)70及四邊扁平封裝72之數種類型的第二層級的封裝係被展示安裝在PCB 52上。視系統需求而定，以第一及第二層級的封裝類型的任意組合來配置的半導體封裝的任何組合及其 它電子構件都可連接至PCB 52。在某些實施例中，電子裝置50係包含單一附接的半導體封裝，而其它實施例需要多個互連的封裝。藉由在單一基板之上組合一或多個半導體封裝，製造商可將預製的構件納入電子裝置及系統中。由於半導體封裝包括複雜的功能，因此可使用較便宜構件及流線化製程來製造電子裝置。所產生的裝置不太可能發生故障且製造費用較低，從而降低消費者成本。
圖2a-2c係展示範例的半導體封裝。圖2a係描繪安裝在PCB 52上的DIP 64之進一步的細節。半導體晶粒74係包括一含有類比或數位電路的主動區，該些類比或數位電路係被實施為形成在晶粒內並且根據該晶粒的電設計而電互連之主動元件、被動元件、導電層及介電層。例如，該電路可包含形成在半導體晶粒74的主動區內之一或多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。接觸墊76是一或多層的導電材料，例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)，並且電連接至形成在半導體晶粒74內之電路元件。在DIP 64的組裝期間，半導體晶粒74係利用一金矽共晶層或例如是熱環氧樹脂的黏著材料而被安裝到一中間載體78。該封裝主體係包含一種例如是聚合物或陶瓷的絕緣囊封體。導線80及接合線82係在半導體晶粒74及PCB 52之間提供電互連。囊封體84係為了環境保護而沉積在該封裝之上，以防止濕氣及微粒進入該封裝且污染半導體晶粒74或接合線82。
圖2b係描繪安裝在PCB 52上之BCC 62的進一步細節。半導體晶粒88係利用一種底膠填充(underfill)或是環氧樹脂黏著材料92而被安裝在載體90之上。接合線94係在接觸墊96及98之間提供第一層級的封裝 互連。模製化合物或囊封體100係沉積在半導體晶粒88及接合線94之上，以提供實體支撐及電氣隔離給該裝置。接觸墊102係利用一例如是電解的電鍍或無電的電鍍之合適的金屬沉積製程而被形成在PCB 52的一表面之上以避免氧化。接觸墊102係電連接至PCB 52中的一或多個導電信號線路54。凸塊104係形成在BCC 62的接觸墊98以及PCB 52的接觸墊102之間。
在圖2c中，半導體晶粒58係以覆晶型第一層級的封裝面向下而安裝到中間載體106。半導體晶粒58的主動區108係包含類比或數位電路，該些類比或數位電路係被實施為根據該晶粒的電設計所形成的主動元件、被動元件、導電層及介電層。例如，該電路可包含一或多個電晶體、二極體、電感器、電容器、電阻器以及主動區108內之其它電路元件。半導體晶粒58係透過凸塊110電性及機械地連接至載體106。
BGA 60係以BGA型第二層級的封裝而利用凸塊112以電性及機械地連接至PCB 52。半導體晶粒58係透過凸塊110、信號線114及凸塊112而電連接至PCB 52中的導電信號線路54。一種模製化合物或囊封體116係沉積在半導體晶粒58及載體106之上，以提供實體支撐及電氣隔離給該裝置。該覆晶半導體裝置係提供從半導體晶粒58上的主動元件到PCB 52上的導電跡線之短的導電路徑，以便縮短信號傳遞距離、降低電容以及改善整體電路效能。在另一實施例中，半導體晶粒58可在無中間載體106的情況下，利用覆晶型第一層級的封裝直接機械及電連接至PCB 52。
圖3a係展示一具有一種例如是矽、鍺、砷化鎵、磷化銦或矽碳化物的主體基板材料122以供結構支撐的半導體晶圓120。如上所述，複數個半導體晶粒或構件124係形成在晶圓120上，且藉由非主動的晶粒間 的晶圓區域或切割道126加以分開。切割道126係提供切割區域以單粒化半導體晶圓120成為個別的半導體晶粒124。
圖3b係展示半導體晶圓120的一部份的橫截面圖。每個半導體晶粒124係具有一背表面128以及包含類比或數位電路的主動表面130，該些類比或數位電路被實施為形成在該晶粒內且根據該晶粒的電設計及功能來電互連的主動元件、被動元件、導電層以及介電層。例如，該電路可包含一或多個電晶體、二極體以及其它形成在主動表面130內之電路元件以實施類比電路或數位電路，例如數位信號處理器(DSP)、ASIC、記憶體或是其它信號處理電路。半導體晶粒124亦可包含整合被動裝置(IPD)，例如電感器、電容器及電阻器，以供RF信號處理使用。
一導電層132係利用PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它合適的金屬沉積製程而形成在主動表面130之上。導電層132可以是一或多層的Al、Cu、Sn、Ni、Au、Ag、或是其它合適的導電材料。導電層132係運作為接觸墊，該些接觸墊係電連接至主動表面130上的電路。如同圖3b中所示，導電層132可形成為接觸墊，該些接觸墊係和半導體晶粒124的邊緣相隔一第一距離而並排地加以設置。或者是，導電層132可形成為接觸墊，該些接觸墊是以多個列加以偏置，使得一第一列的接觸墊係和該晶粒的邊緣相隔一第一距離地加以設置，並且一和該第一列交錯的第二列的接觸墊係和該晶粒的邊緣相隔一第二距離地加以設置。
一絕緣或鈍化層134係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、燒結或是熱氧化而形成在主動表面130及導電層132之上。該絕緣層134係包含一或多層的二氧化矽(SiO2)、矽氮化物(Si3N4)、氮氧化矽 (SiON)、五氧化二鉭(Ta2O5)、鋁氧化物(Al2O3)或是其它具有類似絕緣及結構的性質之材料。絕緣層134的一部分係藉由利用雷射136的雷射直接剝蝕(LDA)來加以移除，以露出導電層132。或者是，絕緣層134的一部分係藉由一蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層132。
在圖3c中，半導體晶圓120的背表面128係進行一利用研磨機137的背面研磨操作，接著是一拋光步驟，以降低該晶圓的厚度。在圖3d中，一晶粒附接黏著膜或帶138係在單粒化之前疊層至該拋光後的背表面128。
在圖3e中，半導體晶圓120係利用一鋸刀或是雷射切割工具139，透過切割道126而被單粒化成為個別的半導體晶粒124。
圖4a-4g係描繪一中介體基板的形成，其中一半導體晶粒係安裝到該基板。圖4a係展示一核心基板140，其係包含一或多個疊層的聚四氟乙烯預浸材(prepreg)、FR-4、FR-1、CEM-1或是CEM-3的層以及酚醛棉紙、環氧樹脂、樹脂、玻璃布、磨砂玻璃、聚酯及其它增強纖維或織物的組合。或者是，核心基板140係包含一或多個絕緣或介電層。
複數個穿透貫孔係利用雷射鑽孔、機械式鑽孔或是深反應性離子蝕刻(DRIE)以穿過核心基板140來加以形成。該些貫孔係利用電解的電鍍、無電的電鍍製程或是其它適當的沉積製程而被填入Al、Cu、Sn、Ni、Au、Ag、鈦(Ti)、鎢(W)或是其它適當的導電材料，以形成z方向垂直的互連導電的貫孔144。在一實施例中，Cu係藉由無電的電鍍以及電鍍而沉積在該些穿透貫孔的側壁之上。該些穿透貫孔係被填入導電膏或是具有填充物的插塞樹脂。
一導電層或是重新分配層(RDL)146係利用一例如是印刷、PVD、CVD、濺鍍、電解的電鍍以及無電的電鍍之圖案化及金屬沉積製程，以形成在核心基板140的一第一表面以及導電的貫孔144之上。導電層146係包含一或多層的Al、Cu、Sn、Ni、Au、Ag或是其它適當的導電材料。導電層146係電連接至導電的貫孔144。
一絕緣或鈍化層148係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結或是熱氧化以形成在核心基板140的第一表面以及導電層146之上。該絕緣層148係包含一或多層的具有或是不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、鉿氧化物(HfO2)、苯環丁烯(BCB)、聚醯亞胺(PI)、聚苯並噁唑(PBO)、聚合物介電質阻劑、或是其它具有類似結構及介電性質之材料。在另一實施例中，絕緣層148是一遮罩層。
一導電層或是RDL 150係利用一例如是印刷、PVD、CVD、濺鍍、電解的電鍍以及無電的電鍍之圖案化及金屬沉積製程以形成在核心基板140相對該第一表面的一第二表面以及導電的貫孔144之上。導電層150係包含一或多層的Al、Cu、Sn、Ni、Au、Ag或是其它適當的導電材料。導電層150係電連接至導電的貫孔144以及導電層146。在另一實施例中，導電的貫孔144係在形成導電層146及/或導電層150之後穿過核心基板140來加以形成。
一絕緣或鈍化層152係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結或是熱氧化以形成在核心基板140的第二表面以及導電層150之上。該絕緣層152係包含一或多層的具 有或是不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PI、PBO、聚合物介電質阻劑、或是其它具有類似結構及介電性質之材料。在一實施例中，為了強化的彎曲強度，絕緣層148及152係包含一例如是二氧化矽、Al2O3或是玻璃纖維的填充物或纖維。絕緣層152的一部分係藉由利用雷射154的LDA來加以移除，以露出導電層150。在另一實施例中，絕緣層152是一遮罩層。
該所產生的中介體基板155係根據半導體晶粒124的電性功能以透過導電層146及150以及導電的貫孔144來提供垂直及橫向地橫跨該基板的電互連。基板155係在過渡階段，亦即在安裝半導體晶粒124之前，藉由開路/短路探針或是自動示波器的檢查來加以檢查及測試是否已知為良好的。根據半導體晶粒124的設計及功能，導電層146及150的部分以及導電的貫孔144是電性共通或是電性隔離的。
基板155亦可以是一多層的撓性積層、陶瓷、銅箔、玻璃或是包含一主動表面的半導體晶圓，該主動表面係包含一或多個電晶體、二極體以及其它電路元件以實施類比電路或是數位電路。
在圖4b中，導線柱156係藉由壓縮接合、線尾接合、球形接合或是楔形接合而附接至基板155的導電層146。導線柱156係在和導電層146接觸之際，於被展示為基底部分156a之處壓縮。柄156b可以裁切至適當的長度，例如250-500μm。在一實施例中，導線柱156係包含Cu、Al或是金屬合金。導線柱156係提供一個3D垂直的互連結構。
圖4c係展示基板155的一實施例，其中導電層150係被絕緣層152所覆蓋，亦即，導電層150並未藉由LDA或是蝕刻製程而被露出。
在圖4d中，來自圖3c的半導體晶粒124係在背表面128被定向朝向該基板之下，利用例如一拾放的操作而被安裝到中介體基板155。半導體晶粒124係利用晶粒附接黏著劑或膜138而被固定到基板155的絕緣層148。圖4e係展示半導體晶粒124被安裝到基板155以作為重組晶圓158。半導體晶粒124是一在安裝到基板155之前已經被測試之已知為良好的晶粒(KGD)。基板155係具有充分的尺寸以容納多個半導體晶粒。
在另一實施例中，如同圖4f中所示，一例如是可剝離乾膜、介電質阻劑或是光阻的保護層160係形成在絕緣層134及導電層132之上。
在另一實施例中，一囊封體162係沉積在半導體晶粒124周圍。如同在圖4g中所示，一積層的互連結構164係形成在絕緣層134、導電層132及囊封體162之上。積層的互連結構164係包含絕緣層166、導電層168、絕緣層170、導電層172以及絕緣層174。積層的互連結構164係在過渡階段，亦即在單粒化之前，藉由開路/短路探針或是自動示波器的檢查來加以檢查及測試是否已知為良好的。該重組晶圓158係利用鋸刀或雷射切割工具176，穿過基板155而被單粒化成為個別的半導體晶粒124。
圖5a-5h係相關於圖1及2a-2c來描繪一在一Fo-WLCSP中形成一積層的互連結構以及中介體基板以作為該雙側的互連結構的製程。圖5a係展示一包含例如是矽、聚合物、鈹氧化物、玻璃、鐵合金或是其它適當的低成本剛性材料之可重複使用或犧牲的基底材料之載體或臨時的基板180，以用於結構的支撐。載體180可以是圓形或是矩形。一包含可壓縮的黏著剝離膜184之介面層或是雙面帶182係形成在載體180之上以作為一暫時的黏著接合膜、蝕刻停止層或是熱剝離層。當安裝半導體晶粒124到 基板140時，其係在積層的互連結構164被定向朝向該載體下，被接合到載體180上之可壓縮的黏著剝離膜184。圖5b係展示半導體晶粒124及基板140被安裝到載體180，其中導電層172及絕緣層174係內嵌在載體180上之可壓縮的剝離膜184之內。載體180係具有充分的尺寸以容納多個半導體晶粒124。
在圖5c中，一囊封體或是模製化合物188係利用一膏印刷、壓縮模製、轉移模製、液體囊封體模製、真空疊層、旋轉塗覆或是其它適當的施用器而沉積在載體180、基板155、半導體晶粒124以及導線柱156之上及周圍。囊封體188可以是聚合物複合材料，例如具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適當的填充物的聚合物。囊封體188是非導電的，並且在環境上保護該半導體裝置免於外部的元素及污染物。
在圖5d中，載體180、介面層182以及可壓縮的剝離膜184係藉由化學蝕刻、機械式剝離，化學品機械的平坦化(CMP)、機械式研磨、熱烘烤、UV光、雷射掃描或是濕式剝除而被移除。額外的背面研磨可被施加，以控制翹曲。囊封體188的一部分係藉由利用雷射190的LDA來加以移除，以露出導線柱156以及積層的互連結構164之導電層172及絕緣層174。
在圖5e中，一絕緣或鈍化層196係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結或是熱氧化以形成在囊封體188、積層的互連結構164以及露出的導線柱156之上。該絕緣層196係包含一或多層的具有或是不具有填充物或纖維之SiO2、Si3N4、 SiON、Ta2O5、Al2O3、聚合物介電質阻劑、或是其它具有類似結構及絕緣性質的材料。
一導電層或是RDL 198係利用一例如是印刷、PVD、CVD、濺鍍、電解的電鍍以及無電的電鍍之圖案化及金屬沉積製程以形成在絕緣層196、積層的互連結構164以及露出的導線柱156之上。導電層198係包含一或多層的Al、Cu、Ti、TiW、Sn、Ni、Au、Ag或是其它適當的導電材料。導電層198的一部分係電連接至積層的互連結構164的導電層172。導電層198的另一部分係電連接至導線柱156。根據半導體晶粒124的設計及功能，導電層198的其它部分可以是電性共通或是電性隔離的。
一絕緣或鈍化層200係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結或是熱氧化以形成在絕緣層196及導電層198之上。該絕緣層200係包含一或多層的具有或是不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物介電質阻劑、或是其它具有類似結構及絕緣性質的材料。絕緣層200的一部分係藉由LDA或是蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層198。
一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程而沉積在導電層198之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。該凸塊材料係利用一適當的安裝或是接合製程而被接合到導電層198。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊202。在某些應用中，凸塊202係被回焊第二次，以改善至導 電層198的電性接觸。在一實施例中，凸塊202係形成在一具有一潤濕層、阻障層及黏著層的UBM之上。該凸塊亦可以壓縮接合或是熱壓接合到導電層198。凸塊202係代表一種可被形成在導電層198之上的互連結構類型。該互連結構亦可以使用接合線、導電膏、柱形凸塊、微凸塊或是其它電互連。
絕緣層196及200以及導電層198及凸塊202的組合係構成一積層的互連結構204。該積層的互連結構204係在額外的裝置集積之前被檢查及測試是否已知為良好的。
在圖5f中，一背面研磨或是支撐帶194係被施加在積層的互連結構204之上。囊封體188的一部分係在一利用研磨機192的研磨操作中加以移除，以平坦化該表面並且露出基板155的絕緣層152。一化學蝕刻或是CMP製程亦可被利用以消除產生自該研磨操作及平坦化囊封體188的機械式損壞。圖5g係展示在該研磨操作之後的基板155，其中任何剩餘的囊封體係藉由雷射193及/或剝除及清洗製程而從導電層150及絕緣層152加以移除。
在圖5h中，背面研磨或是支撐帶194係被移除，並且半導體晶粒124係利用鋸刀或是雷射切割工具208而穿過囊封體188以及積層的互連結構204被單粒化成為個別的雙側的扇出晶圓級晶片尺寸封裝(Fo-WLCSP)210。圖6係展示在單粒化之後的Fo-WLCSP 210。半導體晶粒124係透過積層的互連結構164、積層的互連結構204以及導線柱156而電連接至基板155，以用於連接至外部的裝置。基板155以及積層的互連結構164及204係在Fo-WLCSP 210的相對側(雙側)上提供垂直及橫向的互連給半 導體晶粒124。基板155係在和積層的互連結構164及204不同的時間且分開地加以形成。在晶粒安裝之前形成及測試基板155係簡化製程並且降低成本。在基板155以及該些積層的互連結構之間提供垂直的互連之積層的互連結構164及204以及導線柱156之稍後的形成係完成用於半導體晶粒124在Fo-WLCSP 210的相對側上之垂直及橫向的互連。
在另一實施例中，從圖4g繼續，如同在圖7a中所示，在基板140的絕緣層152被定向朝向該載體下，半導體晶粒124係被安裝到載體220。導電層150可以完全被絕緣層152覆蓋。一高溫(大於200℃)可剝離的接合帶222係被施加在載體220之上。或者是，一具有選配的填充物或纖維之永久的介電質接合層222係被施加在載體220之上。基板140的導電層146及絕緣層148係被壓縮到載體220上之可剝離的接合帶222中。一類似於圖4f中的保護層160之保護層可以形成在積層的互連結構164的絕緣層174之上。或者是，絕緣層174可以是具有填充物的介電材料，並且具有大於25μm的厚度。
一囊封體或是模製化合物226係利用一膏印刷、壓縮模製、轉移模製、液體囊封體模製、真空疊層、旋轉塗覆或是其它適當的施用器而沉積在載體220、基板155、半導體晶粒124及導線柱156之上。囊封體226可以是聚合物複合材料，例如具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適當的填充物的聚合物。囊封體226是非導電的，並且在環境上保護該半導體裝置免於外部的元素及污染物。
在圖7b中，囊封體226的一部分係藉由利用雷射228的LDA來加以移除，以露出積層的互連結構164的導線柱156以及導電層172及絕 緣層174。
在圖7c中，一絕緣或鈍化層230係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結或是熱氧化以形成在囊封體226、積層的互連結構164以及露出的導線柱形156之上。該絕緣層230係包含一或多層的具有或是不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物介電質阻劑、或是其它具有類似結構及絕緣性質的材料。
一導電層或是RDL 232係利用一例如是印刷、PVD、CVD、濺鍍、電解的電鍍以及無電的電鍍之圖案化及金屬沉積製程以形成在絕緣層230、積層的互連結構164以及露出的導線柱156之上。導電層232係包含一或多層的Al、Cu、Ti、TiW、Sn、Ni、Au、Ag或是其它適當的導電材料。導電層232的一部分係電連接至積層的互連結構164的導電層172。導電層232的另一部分係電連接至導線柱156。根據半導體晶粒124的設計及功能，導電層232的其它部分可以是電性共通或是電性隔離的。
一絕緣或鈍化層234係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結或是熱氧化以形成在絕緣層230及導電層232之上。該絕緣層234係包含一或多層的具有或是不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物介電質阻劑、或是其它具有類似結構及絕緣性質的材料。絕緣層234的一部分係藉由LDA或是蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層232。
一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程而沉積在導電層232之上。該凸塊材料可 以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。該凸塊材料係利用一適當的安裝或是接合製程而被接合到導電層232。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊236。在某些應用中，凸塊236係被回焊第二次，以改善至導電層232的電性接觸。在一實施例中，凸塊236係形成在一具有一潤濕層、阻障層及黏著層的UBM之上。該些凸塊亦可以壓縮接合或是熱壓接合到導電層232。凸塊236係代表一種可被形成在導電層232之上的互連結構類型。該互連結構亦可以使用接合線、導電膏、柱形凸塊、微凸塊或是其它電互連。
絕緣層230及234以及導電層232及凸塊236的組合係構成一積層的互連結構238。該積層的互連結構238係在額外的裝置集積之前被檢查及測試是否已知為良好的。
在圖7d中，載體220以及可剝離接合帶222係藉由化學蝕刻、機械的剝離、CMP、機械式研磨、熱烘烤、UV光、雷射掃描或是濕式剝除來加以移除。在永久的接合材料222的情形中，載體220可以部分地被移除。半導體晶粒124係利用鋸刀或是雷射切割工具239，透過囊封體226及積層的互連結構238而被單粒化成為個別的雙側的Fo-WLCSP 240。圖8係展示在單粒化之後的Fo-WLCSP 240。半導體晶粒124係透過積層的互連結構164、積層的互連結構238以及導線柱156而電連接至基板155，以用於連接至外部的裝置。基板155以及積層的互連結構164及238係提供給半導體晶粒124在Fo-WLCSP 240的相對側(雙側)上之垂直及橫向的互連。基 板155係在和積層的互連結構164及238不同的時間而且是分開地加以形成。基板155在晶粒安裝之前的形成及測試係簡化製程並且降低成本。在基板155以及該些積層的互連結構之間提供垂直的互連之積層的互連結構164及238以及導線柱156之稍後的形成係完成用於半導體晶粒124在Fo-WLCSP 240的相對側上之垂直及橫向的互連。
在另一實施例中，從圖4g繼續，如同在圖9a中所示，基板155係維持為未單粒化的(參見圖4c)，其中半導體晶粒124係安裝到該基板。一囊封體或是模製化合物242係沉積在基板155、半導體晶粒124及導線柱156之上。
在圖9b中，囊封體242的一部分係藉由利用雷射243的LDA來加以移除，以露出導線柱156以及積層的互連結構164的導電層172及絕緣層174。
在圖9c中，一絕緣或鈍化層244係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結或是熱氧化以形成在囊封體242、積層的互連結構164以及露出的導線柱156之上。該絕緣層244係包含一或多層的具有或是不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物介電質阻劑、或是其它具有類似結構及絕緣性質的材料。
一導電層或是RDL 246係利用一例如是印刷、PVD、CVD、濺鍍、電解的電鍍以及無電的電鍍之圖案化及金屬沉積製程以形成在絕緣層244、積層的互連結構164以及露出的導線柱156之上。導電層246係包含一或多層的Al、Cu、Sn、Ni、Au、Ag或是其它適當的導電材料。導電層 246的一部分係電連接至積層的互連結構164的導電層172。導電層246的另一部分係電連接至導線柱156。根據半導體晶粒124的設計及功能，導電層246的其它部分可以是電性共通或是電性隔離的。
一絕緣或鈍化層248係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結或是熱氧化以形成在絕緣層244及導電層246之上。該絕緣層248係包含一或多層的具有或是不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物介電質阻劑、或是其它具有類似結構及絕緣性質的材料。絕緣層248的一部分係藉由LDA或是蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層246。
一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程而沉積在導電層246之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。該凸塊材料係利用一適當的安裝或是接合製程而被接合到導電層246。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊250。在某些應用中，凸塊250係被回焊第二次，以改善至導電層246的電性接觸。在一實施例中，凸塊250係形成在一具有一潤濕層、阻障層及黏著層的UBM之上。該凸塊亦可以壓縮接合或是熱壓接合到導電層246。凸塊250係代表一種可被形成在導電層246之上的互連結構類型。該互連結構亦可以使用接合線、導電膏、柱形凸塊、微凸塊或是其它電互連。
絕緣層244及248以及導電層246及凸塊250的組合係構成 一積層的互連結構252。該積層的互連結構252係在額外的裝置集積之前被檢查及測試是否已知為良好的。
在圖9d中，絕緣層152的一部分係藉由利用雷射254的LDA來加以移除，以露出導電層150。半導體晶粒124係利用鋸刀或是雷射切割工具255，穿過基板155、囊封體242以及積層的互連結構252而被單粒化成為個別的雙側的Fo-WLCSP 256。圖10係展示在單粒化之後的Fo-WLCSP 256。半導體晶粒124係透過積層的互連結構164、積層的互連結構252以及導線柱156而電連接至基板155，以用於連接至外部的裝置。基板155以及積層的互連結構164及252係提供給半導體晶粒124在Fo-WLCSP 256的相對側(雙側)上之垂直及橫向的互連。基板155係在和積層的互連結構164及252不同的時間且分開的形成。基板155在晶粒安裝之前的形成及測試係簡化製程並且降低成本。在基板155以及該些積層的互連結構之間提供垂直的互連之積層的互連結構164及252以及導線柱156之稍後的形成係完成用於半導體晶粒124在Fo-WLCSP 256的相對側上之垂直及橫向的互連。
類似於圖10，圖11係描繪Fo-WLCSP 260的一實施例，其中柱形凸塊262係設置在基板155以及積層的互連結構252之間。柱形凸塊262係將基板155的導電層146電連接至積層的互連結構252的導電層246。積層的互連結構164係包含至少一RDL層，例如，導電層168。
類似於圖5a-5h，圖12係描繪Fo-WLCSP 270的一實施例，其中柱形凸塊272係設置在基板155以及積層的互連結構204之間。柱形凸塊272係將基板155的導電層146電連接至積層的互連結構204的導電層198。囊封體188係沿著基板155的側表面延伸到絕緣層152的一上表面。 積層的互連結構164係包含至少一RDL層，例如，導電層168。
類似於圖5a-5h，圖13係描繪Fo-WLCSP 280的一實施例，其中柱形凸塊282係設置在基板155以及積層的互連結構204之間。柱形凸塊282係將基板155的導電層146電連接至積層的互連結構204的導電層198。囊封體188係沿著基板155的側表面延伸到絕緣層152的一上表面。囊封體188係覆蓋半導體晶粒124的側表面以及該半導體晶粒的主動表面130的一部分。
類似於圖5a-5h，圖14係描繪Fo-WLCSP 290的一實施例，其中柱形凸塊292係設置在基板155以及積層的互連結構204之間。柱形凸塊292係將基板155的導電層146電連接至積層的互連結構204的導電層198。囊封體188係覆蓋半導體晶粒124的側表面以及該半導體晶粒的主動表面130的一部分。基板155係被移除，並且被所遮罩層294取代。遮罩層294的一部分係藉由LDA或是蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層146。
類似於圖5a-5h，圖15係描繪Fo-WLCSP 300的一實施例，其中引線架302係內嵌在囊封體304之內。柱形凸塊306係被設置在引線架302以及積層的互連結構204之間。囊封體188係覆蓋半導體晶粒124的側表面以及該半導體晶粒的主動表面130的一部分。囊封體304的一部分係藉由LDA或是蝕刻製程透過一圖案化的光阻層來加以移除，以露出引線架302。
圖16a-16f係相關於圖1及2a-2c來描繪一在一Fo-WLCSP中形成頂端及底部積層的互連結構的製程。圖16a係展示一包含例如是矽、聚 合物、鈹氧化物、玻璃或是其它適當的低成本剛性材料的犧牲基底材料之載體或是臨時的基板310，以用於結構的支撐。
一絕緣或鈍化層312係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結或是熱氧化以形成在載體310之上。該絕緣層312係包含一或多層的具有或是不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物介電質阻劑、或是其它具有類似結構及絕緣性質的材料。在一實施例中，為了強化的彎曲強度，絕緣層312係包含一玻璃布、玻璃纖維布、填充物、或是纖維，例如二氧化矽、Al2O3或玻璃纖維。
一導電層或是RDL 314係利用一例如是Cu箔疊層、印刷、PVD、CVD、濺鍍、電解的電鍍以及無電的電鍍之圖案化及金屬沉積製程以形成在絕緣層312之上。導電層314係包含一或多層的Al、Cu、Sn、Ni、Au、Ag或是其它適當的導電材料。在一實施例中，導電層314係利用光阻或是墨水印刷圖案化的Cu箔。或者是，導電層314係包含Ti(TiW)/Cu晶種層，接著是微影及選擇性的電鍍。根據該半導體晶粒的設計及功能，導電層314的部分可以是電性共通或是電性隔離的。
在圖16b中，一絕緣或鈍化層316係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結或是熱氧化以形成在絕緣層312及導電層314之上。該絕緣層316係包含一或多層的具有或是不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物介電質阻劑、或是其它具有類似結構及絕緣性質的材料。在一實施例中，為了強化的彎曲強度，絕緣層316係包含一玻璃布、玻璃纖維布、填充物、或 是纖維，例如二氧化矽、Al2O3或玻璃纖維。絕緣層316的一部分係藉由利用雷射318的LDA來加以移除，以露出導電層314。或者是，絕緣層316的一部分係藉由蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層314。導電層314以及絕緣層316係在過渡階段，亦即在安裝半導體晶粒320之前，藉由開路/短路探針或是自動示波器的檢查來加以檢查及測試是否已知為良好的。
圖16c係展示來自一類似於圖3a的半導體晶圓之具有一背表面322及主動表面324的半導體晶粒320，該主動表面324係包含類比或數位電路，該些類比或數位電路係被實施為形成在該晶粒內並且根據該晶粒的電性設計及功能電互連的主動元件、被動元件、導電層及介電層。例如，該電路可包含一或多個形成在主動表面324內的電晶體、二極體以及其它電路元件，以實施例如是DSP、ASIC、記憶體或是其它信號處理電路的類比電路或數位電路，。半導體晶粒320亦可包含例如是電感器、電容器及電阻器的IPD，以用於RF信號處理。
一導電層326係利用PVD、CVD、電解的電鍍、無電的電鍍製程或是其它適當的金屬沉積製程以形成在主動表面324之上。導電層326可以是一或多層的Al、Cu、Sn、Ni、Au、Ag或是其它適當的導電材料。導電層326係運作為電連接至主動表面324上的電路之接觸墊。
一絕緣或鈍化層328係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結或是熱氧化以形成在主動表面324及導電層326之上。該絕緣層328係包含一或多層的具有或是不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物介電質阻劑、 或是其它具有類似結構及絕緣性質的材料。絕緣層328的一部分係藉由LDA或是蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層326。
一絕緣或鈍化層330係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結或是熱氧化以形成在絕緣層328及導電層326之上。該絕緣層330係包含一或多層的具有或是不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物材料、或是其它具有類似結構及絕緣性質的材料。絕緣層330的一部分係藉由LDA或是蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層326。
一保護層332係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結或是熱氧化以形成在絕緣層330及導電層326之上。保護層332係包含一或多層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是其它具有類似結構及絕緣性質的材料。
半導體晶粒320係利用例如是環氧樹脂的晶粒附接黏著劑334而被安裝到絕緣層316。柱形凸塊336係形成在導電層314之上。離散的半導體裝置338係利用導電膏340而冶金且電耦接至導電層314。離散的半導體裝置338可以是一電感器、電容器、電阻器、電晶體或是二極體。
在圖16d中，一囊封體或是模製化合物342係利用一膏印刷、壓縮模製、轉移模製、液體囊封體模製、真空疊層、旋轉塗覆或是其它適當的施用器而沉積在絕緣層316、半導體晶粒320、柱形凸塊336以及離散的半導體裝置338之上及周圍。囊封體342可以是聚合物複合材料，例如具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適當的填充物的聚合物。囊封體342是非導電的，並且在環境上保護該半導體裝 置免於外部的元素及污染物。
在圖16e中，保護層332係被移除以露出在囊封體342內的一淺凹處中之絕緣層330及導電層326。一絕緣或保護層350係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結或是熱氧化以形成在半導體晶粒320、囊封體342及柱形凸塊336之上。該絕緣層350係包含一或多層的具有或是不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物介電質阻劑、或是其它具有類似結構及絕緣性質的材料。絕緣層350的一部分係藉由LDA或是蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層326及柱形凸塊336。
一導電層或是RDL 352係利用一例如是印刷、PVD、CVD、濺鍍、電解的電鍍以及無電的電鍍之圖案化及金屬沉積製程以形成在絕緣層350及柱形凸塊336之上。導電層352係包含一或多層的Al、Cu、Sn、Ni、Au、Ag或是其它適當的導電材料。導電層352的一部分係電連接至半導體晶粒320的導電層326。導電層352的另一部分係電連接至柱形凸塊336。根據半導體晶粒320的設計及功能，導電層352的其它部分可以是電性共通或是電性隔離的。
一絕緣或鈍化層354係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結或是熱氧化以形成在絕緣層350及導電層352之上。該絕緣層354係包含一或多層的具有或是不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物介電質阻劑、或是其它具有類似結構及絕緣性質的材料。絕緣層354的一部分係藉由LDA或是蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層326及柱 形凸塊352。
一導電層或是RDL 356係利用一例如是印刷、PVD、CVD、濺鍍、電解的電鍍以及無電的電鍍之圖案化及金屬沉積製程以形成在絕緣層354及導電層352之上。導電層356係包含一或多層的Al、Cu、Sn、Ni、Au、Ag或是其它適當的導電材料。導電層356的一部分係電連接至導電層352。根據半導體晶粒320的設計及功能，導電層356的其它部分可以是電性共通或是電性隔離的。
一絕緣或鈍化層358係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結或是熱氧化以形成在絕緣層354及導電層356之上。該絕緣層358係包含一或多層的具有或是不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物介電質阻劑、或是其它具有類似結構及絕緣性質的材料。絕緣層358的一部分係藉由LDA或是蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層356。
一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程而沉積在導電層356之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。該凸塊材料係利用一適當的安裝或是接合製程而被接合到導電層356。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊360。在某些應用中，凸塊360係被回焊第二次，以改善至導電層356的電性接觸。在一實施例中，凸塊360係形成在一具有一潤濕層、阻障層及黏著層的UBM之上。該些凸塊亦可以壓縮接合或是熱壓接合到導 電層356。凸塊360係代表一種可被形成在導電層356之上的互連結構類型。該互連結構亦可以使用接合線、導電膏、柱形凸塊、微凸塊或是其它電互連。
絕緣層350、354及358以及導電層352以及356以及凸塊360的組合係構成一積層的互連結構362。該積層的互連結構362係在額外的裝置集積之前被檢查及測試是否已知為良好的。
在圖16f中，載體310係藉由化學蝕刻、機械的剝離、CMP、機械式研磨、熱烘烤、UV光、雷射掃描或是濕式剝除來加以移除，以露出導電層314及絕緣層316。額外的背面研磨可以施加，以控制翹曲。絕緣層312的一部分係藉由利用雷射366的LDA來加以移除，以露出導電層314。或者是，絕緣層312的一部分係藉由蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層314。
在Fo-WLCSP 370中，半導體晶粒320係透過積層的互連結構362以及柱形凸塊336而電連接至導電層314。積層的互連結構362以及導電層314係提供在Fo-WLCSP 370的相對側(雙側)上之垂直及橫向的互連給半導體晶粒320。導電層314係在和積層的互連結構362不同的時間且分開地加以形成。導電層314在晶粒安裝前的形成及測試係簡化製程並且降低成本。在導電層314以及該些積層的互連結構之間提供垂直的互連之積層的互連結構362以及柱形凸塊336之稍後的形成係在Fo-WLCSP 370的相對側上完成用於半導體晶粒320之垂直及橫向的互連。
儘管本發明的一或多個實施例已經詳細地描述，但是本領域技術人員將會體認到對於該些實施例的修改及調適可以在不脫離如以下的 申請專利範圍中所闡述之本發明的範疇下加以完成。
124‧‧‧半導體晶粒(構件)
128‧‧‧背表面
130‧‧‧主動表面
132‧‧‧導電層
134‧‧‧絕緣(鈍化)層
138‧‧‧晶粒附接黏著膜(帶)
140‧‧‧核心基板
144‧‧‧導電的貫孔
146‧‧‧導電層(重新分配層)
148‧‧‧絕緣(鈍化)層
150‧‧‧導電層(RDL)
152‧‧‧絕緣(鈍化)層
155‧‧‧中介體基板
156‧‧‧導線柱
156a‧‧‧基底部分
156b‧‧‧柄
162‧‧‧囊封體
164‧‧‧積層的互連結構
166‧‧‧絕緣層
168‧‧‧導電層
170‧‧‧絕緣層
172‧‧‧導電層
174‧‧‧絕緣層
226‧‧‧囊封體(模製化合物)
228‧‧‧雷射
230‧‧‧絕緣(鈍化)層
232‧‧‧導電層
234‧‧‧絕緣(鈍化)層
236‧‧‧球(凸塊)
238‧‧‧積層的互連結構
240‧‧‧扇出晶圓級晶片尺寸封裝

Claims (15)

  1. 一種製造一半導體裝置之方法，其係包括：提供一基板，其包含被形成在該基板的一表面之上的一第一導電層；在該基板的該表面之上形成複數個導線柱；設置一半導體晶粒至該基板的該表面之上及該些導線柱之間；在相對於該基板的該半導體晶粒的一表面之上形成一第一互連結構；在該基板、該第一互連結構以及該半導體晶粒之上沉積一第一囊封體，而該些導線柱的一部分是從該第一囊封體露出；以及在相對於該基板的該第一囊封體的一表面之上形成一第二互連結構並且電性連接至該第一互連結構和該些導線柱。
  2. 如申請專利範圍第1項之方法，其進一步包含：在該半導體晶粒周圍形成一第二囊封體；以及在該半導體晶粒以及第二囊封體之上形成該第一互連結構。
  3. 如申請專利範圍第1項之方法，其進一步包含從該第一互連結構之上移除該第一囊封體的一部分。
  4. 如申請專利範圍第1項之方法，其進一步包含從該基板之上移除該第一囊封體的一部分。
  5. 一種製造一半導體裝置之方法，其係包括：形成一第一互連結構；提供一半導體晶粒；在該半導體晶粒之上形成一保護層；在形成該第一互連結構之後，設置該半導體晶粒至該第一互連結構的 一第一表面之上；在該第一互連結構的該第一表面之上形成複數個柱形凸塊；在該第一互連結構、該些柱形凸塊以及該半導體晶粒之上沉積一囊封體；從該半導體晶粒之上移除該保護層；以及在該囊封體、該些柱形凸塊以及該半導體晶粒之上形成一第二互連結構。
  6. 如申請專利範圍第5項之方法，其中形成該第一互連結構係包含：形成一第一絕緣層；在該第一絕緣層之上形成一導電層；以及在該第一絕緣層以及該導電層之上形成一第二絕緣層。
  7. 如申請專利範圍第6項之方法，其中形成該第一互連結構進一步包含藉由雷射直接剝蝕來移除該第二絕緣層的一部分。
  8. 如申請專利範圍第6項之方法，其進一步包含在該第二絕緣層以及該導電層之上形成一第三絕緣層。
  9. 如申請專利範圍第5項之方法，其中形成該第二互連結構係包含：在該囊封體以及該半導體晶粒之上形成一第一絕緣層；在該第一絕緣層之上形成一第一導電層；在該第一絕緣層以及該第一導電層之上形成一第二絕緣層；在該第二絕緣層以及該第一導電層之上形成一第二導電層上；以及在該第二絕緣層以及第二導電層之上形成一第三絕緣層。
  10. 一種半導體裝置，其係包括： 一基板；一垂直的互連結構，其形成在該基板的一第一表面之上；一半導體晶粒，其配置在該基板的該第一表面之上；一第一囊封體，其沉積在該基板、該半導體晶粒以及該垂直的互連結構之上；以及一第一互連結構，其形成在該第一囊封體、該半導體晶粒以及該垂直的互連結構的一露出部份之上。
  11. 如申請專利範圍第10項之半導體裝置，其中該基板係包含形成在該基板的第一及第二相對的表面之上的第一及第二導電層。
  12. 如申請專利範圍第10項之半導體裝置，其進一步包含一沉積在該半導體晶粒的周圍的第二囊封體，其中該第一互連結構係形成在該半導體晶粒以及該第二囊封體之上。
  13. 如申請專利範圍第10項之半導體裝置，其中該第一囊封體係形成在該半導體晶粒的一部分之上。
  14. 如申請專利範圍第10項之半導體裝置，其中該第一囊封體係形成在該基板的一側表面之上。
  15. 如申請專利範圍第10項之半導體裝置，其中該垂直的互連結構係包含導線柱或是柱形凸塊。
TW102122923A 2012-09-14 2013-06-27 形成在扇出晶圓級晶片尺寸封裝中的雙側互連結構的半導體裝置和方法 TWI588956B (zh)

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