CN103681362B - 半导体器件以及在fo-wlcsp中形成双侧互连结构的方法 - Google Patents

半导体器件以及在fo-wlcsp中形成双侧互连结构的方法 Download PDF

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CN103681362B
CN103681362B CN201310170374.3A CN201310170374A CN103681362B CN 103681362 B CN103681362 B CN 103681362B CN 201310170374 A CN201310170374 A CN 201310170374A CN 103681362 B CN103681362 B CN 103681362B
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interconnection structure
substrate
semiconductor chip
conductive layer
sealant
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CN103681362A (zh
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林耀剑
陈康
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明的名称为半导体器件以及在FO‑WLCSP中形成双侧互连结构的方法。一种半导体器件具有衬底，所述衬底包括形成在所述衬底的第一和第二相反表面上的第一和第二导电层。多个引线柱或柱形凸起被形成在所述衬底上。半导体小片被安装到所述引线柱之间的所述衬底上。第一密封剂被沉积在所述半导体小片周围。第一互连结构被形成在所述半导体小片和第一密封剂上。第二密封剂被沉积在所述衬底、半导体小片和第一互连结构上。所述第二密封剂能够被形成在所述半导体小片的一部分和所述衬底的侧表面上。所述第二密封剂的一部分被去除以暴露所述衬底和第一互连结构。第二互连结构被形成在所述第二密封剂和第一互连结构上并且与所述引线柱电耦合。分立半导体器件能够被形成在所述互连结构上。

Description

半导体器件以及在FO-WLCSP中形成双侧互连结构的方法
国内优先权的声明
本申请要求2012年9月14日提交的、申请号为61/701,366的美国临时申请的权益，该申请通过引用并入本文。
相关申请的交叉引用
本申请与序号13/832,118、代理人案号2515.0424、题为“Semiconductor Deviceand Method of Forming Build-up Interconnect Structure over Carrier forTesting at Interim stages (半导体器件以及在载体上形成积层互连结构用于在中间阶段进行测试的方法)”的美国专利申请相关。本申请还与序号13/832,205、代理人案号2515.0408、题为“Semiconductor Device and Method of Forming Dual-SidedInterconnect Structures in Fo-WLCSP (半导体器件以及在Fo-WLCSP中形成双侧互连结构的方法)”的美国专利申请相关。
技术领域
本申请一般地涉及半导体器件，并且更具体地，涉及一种半导体器件以及在Fo-WLCSP中形成双侧互连结构的方法。
背景技术
半导体器件通常在现代电子产品中被发现。半导体器件在电部件的数量和密度方面各不相同。分立半导体器件通常包含一种类型的电部件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器以及功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件典型地包含数百到数百万个电部件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池以及数字微镜器件(DMD)。
半导体器件执行范围广泛的功能，诸如信号处理、高速计算、发射及接收电磁信号、控制电子器件、将日光转换为电力以及创建用于电视显示的视觉投影。半导体器件在娱乐、通信、功率变换、网络、计算机以及消费品领域中被发现。半导体器件还在军事应用、航空、汽车、工业控制器以及办公设备中被发现。
半导体器件利用了半导体材料的电特性。半导体材料的结构允许它的电导率通过电场或基电流的施加或经由掺杂工艺来操纵。掺杂将杂质引入半导体材料中以操纵并且控制半导体器件的电导率。
半导体器件包含有源和无源的电结构。包括双极型和场效应晶体管的有源结构控制电流的流动。通过改变掺杂的程度和电场或基电流的施加，晶体管或者促进或者限制电流的流动。包括电阻器、电容器和电感器的无源结构在电压与电流之间建立对于执行各种电功能所必需的关系。无源和有源结构被电连接以形成电路，这使半导体器件能够执行高速操作及其他有用的功能。
半导体器件通常使用两种复杂的制造工艺，即前端制造和后端制造来制造，所述每种工艺都潜在地涉及数百个步骤。前端制造涉及多个小片在半导体晶片的表面上的形成。每个半导体小片通常是一致的并且包含通过电连接有源和无源部件所形成的电路。后端制造涉及从完成的晶片分割(singulate)出单独的半导体小片并且对所述小片进行封装以提供结构支撑和环境隔离。在本文中所使用的术语“半导体小片”指词的单数形式和复数形式两者，并且相应地，能够指单个半导体器件和多个半导体器件两者。
半导体制造的一个目标是产生更小的半导体器件。更小的器件典型地消耗更少的功率、具有更高的性能并且能够被更高效地生产。此外，更小的半导体器件具有更小的占用面积，这对于更小的终端产品来说是所期望的。更小的半导体小片尺寸能够由前端工艺方面的改进来达到，从而产生具有更小的、更高密度的有源和无源部件的半导体小片。后端工艺可以通过电互连和封装材料方面的改进来产生具有更小占用面积的半导体器件封装。
半导体小片常常为与外部器件的电连接而在扇出型晶片级芯片规模封装(Fo-WLCSP)中需要顶部和底部积层互连结构。积层互连结构典型地逐层形成在Fo-WLCSP的两侧。由于工业标准的临时接合工艺，积层互连结构的逐层形成需要长循环时间和高制造成本。临时接合可能降低制造良率并且增加缺陷。
发明内容
存在对Fo-WLCSP中的简单并且有成本效益的双侧互连结构的需要。因此，在一个实施例中，本发明是一种制作半导体器件的方法，其包括以下步骤：提供衬底，所述衬底包括形成在所述衬底的第一和第二相反表面上的第一和第二导电层；在所述衬底上形成多个引线柱(wire stud)；将半导体小片安装到所述引线柱之间的所述衬底上；在所述半导体小片上形成第一互连结构；将第一密封剂沉积在所述衬底、半导体小片和第一互连结构上；以及在所述第一密封剂和第一互连结构上形成第二互连结构并且所述第二互连结构与所述引线柱电耦合。
在另一实施例中，本发明是一种制作半导体器件的方法，其包括以下步骤：提供衬底；在所述衬底上形成垂直互连结构；将半导体小片安装到所述衬底上；在所述半导体小片上形成第一互连结构；将第一密封剂沉积在所述衬底和半导体小片上；以及在所述第一密封剂和第一互连结构上形成第二互连结构。
在另一实施例中，本发明是一种制作半导体器件的方法，其包括以下步骤：提供第一互连结构；提供半导体小片；在所述半导体小片上形成保护层；将所述半导体小片安装到所述第一互连结构上；在所述第一互连结构上形成多个柱形凸起(stud bump)；将密封剂沉积在所述第一互连结构和半导体小片上；去除所述保护层以暴露所述半导体小片；以及在所述密封剂和半导体小片上形成第二互连结构。
在另一实施例中，本发明是一种半导体器件，其包括衬底和形成在所述衬底上的垂直互连结构。半导体小片被安装到所述衬底上。第一互连结构被形成在所述半导体小片上。第一密封剂被沉积在所述衬底和半导体小片上。第二互连结构被形成在所述第一密封剂和第一互连结构上。
附图说明
图1示意了其中不同类型的封装被安装到其表面上的印刷电路板(PCB)；
图2a-2c示意了安装到PCB上的有代表性的半导体封装的更多细节；
图3a-3e示意了具有被锯齿型街沟分开的多个半导体小片的半导体晶片；
图4a-4g示意了形成内插板衬底的过程，其中半导体小片被安装到该衬底上；
图5a-5h示意了在Fo-WLCSP中形成积层互连结构和内插板衬底作为双侧互连结构的过程；
图6示意了具有根据图5a-5h的双侧互连结构的Fo-WLCSP；
图7a-7d示意了在Fo-WLCSP中形成积层互连结构和内插板衬底作为双侧互连结构的另一过程；
图8示意了具有根据图7a-7d的双侧互连结构的Fo-WLCSP；
图9a-9d示意了在Fo-WLCSP中形成积层互连结构和内插板衬底作为双侧互连结构的过程；
图10示意了具有根据图9a-9d的双侧互连结构的Fo-WLCSP；
图11示意了在双侧互连结构之间具有柱形凸起(stud bump)的Fo-WLCSP；
图12示意了其中密封剂沿内插板衬底的侧面延伸的Fo-WLCSP；
图13示意了其中密封剂被置于半导体小片的有源表面的一部分上的Fo-WLCSP；
图14示意了在互连结构上具有掩膜层的Fo-WLCSP；
图15示意了具有引线框作为互连结构的Fo-WLCSP；以及
图16a-16f示意了在Fo-WLCSP中形成顶部和底部积层互连结构的过程。
具体实施方式
参考附图在以下说明中用一个或多个实施例对本发明进行描述，在附图中相同的标记表示相同的或类似的元件。虽然就用于达到本发明的目标的最佳模式而言对本发明进行了描述，但本领域的技术人员将理解的是，本发明旨在涵盖可以被包括在本发明的精神和范围内的替代方案、修改以及等同物，本发明的精神和范围由以下公开内容和附图所支持的所附权利要求及其等同物限定。
半导体器件通常使用两个复杂的制造工艺来制造：前端制造和后端制造。前端制造涉及多个小片在半导体晶片的表面上的形成。晶片上的每个小片都包含有源和无源电部件，其被电连接以形成功能电路。诸如晶体管和二极管的有源电部件具有控制电流流动的能力。诸如电容器、电感器以及电阻器的无源电部件在电压与电流之间产生对于执行电路功能所必需的关系。
无源和有源部件通过一系列工艺步骤形成在半导体晶片的表面上，所述一系列工艺步骤包括掺杂、沉积、光刻、蚀刻以及平面化。掺杂通过诸如离子注入或热扩散的技术将杂质引入半导体材料中。掺杂工艺通过响应于电场或基电流动态地改变半导体材料的电导率来改变有源器件中的半导体材料的电导率。晶体管包含根据需要被布置以使该晶体管能够在电场或基电流被施加时促进或限制电流的流动的不同类型和程度的掺杂的区域。
有源和无源部件由具有不同电特性的材料的层形成。所述层能够通过部分地由被沉积的材料的类型确定的各种沉积技术来形成。例如，薄膜沉积可能涉及化学气相淀积(CVD)、物理气相沉积(PVD)、电解电镀以及无电镀工艺。每一层通常都被图形化以形成有源部件、无源部件或部件之间的电连接的部分。
后端制造指将完成的晶片切割或分割成单独的半导体小片并且进而对半导体小片进行封装以用于结构支撑和环境隔离。为了分割出半导体小片，沿被称为锯齿型街沟或划线的、晶片的非功能区域刻痕并且截断晶片。使用激光切割工具或锯条来分割晶片。在分割之后，单独的半导体小片被安装到封装衬底上，所述封装衬底包括用于与其他系统部件的互连的管脚或接触垫。形成在半导体小片上的接触垫进而被连接到封装内的接触垫。电连接能够用焊料凸起、柱形凸起、导电胶或线接合来进行。密封剂或其他成型材料被沉积在封装上以提供物理支撑和电隔离。完成的封装进而被插入电系统中，并且使半导体器件的功能对于其他系统部件可用。
图1示意了具有芯片载体衬底或印刷电路板(PCB) 52的电子器件50，其中多个半导体封装被安装在所述芯片载体衬底或印刷电路板(PCB) 52的表面上。取决于应用，电子器件50能够具有一种类型的半导体封装或多种类型的半导体封装。出于示意的目的在图1中示出了不同类型的半导体封装。
电子器件50可以是使用半导体封装来执行一个或多个电功能的独立系统。备选地，电子器件50可以是较大系统的子部件。例如，电子器件50可以是蜂窝电话、个人数字助理(PDA)、数码摄像机(DVC)或其他电子通信设备的部分。备选地，电子器件50可以是图形卡、网络接口卡或能够被插入计算机中的其他信号处理卡。半导体封装能够包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件或其他半导体小片或电部件。小型化和重量降低对于产品被市场接受来说是必要的。半导体器件之间的距离必须被减小以达到较高的密度。
在图1中，PCB 52提供了用于安装在该PCB上的半导体封装的结构支撑和电互连的一般的衬底。导电信号迹线54使用蒸发、电解电镀、无电镀、丝网印刷或其他适当的金属沉积工艺形成在PCB 52的表面上或PCB 52的各层内。信号迹线54提供半导体封装、所安装的部件以及其他外部系统部件中的每一个之间的电通信。迹线54还向半导体封装中的每一个提供电源和地连接。
在一些实施例中，半导体器件具有两个封装级。第一级封装是用于将半导体小片机械地并且电性地附接至中间载体的技术。第二级封装涉及将中间载体机械地并且电性地附接至PCB。在其他实施例中，半导体器件可以仅具有第一级封装，其中小片直接被机械地并且电性地安装到PCB上。
出于示意的目的，若干类型的第一级封装，包括接合线封装56和倒装芯片58在PCB52上示出。此外，若干类型的第二级封装，包括球栅阵列(BGA) 60、凸起芯片载体(BCC) 62、双列直插式封装(DIP) 64、栅格阵列(LGA) 66、多芯片模块(MCM) 68、方形扁平无引脚封装(QFN) 70以及方形扁平封装72被示出为安装在PCB 52上。取决于系统要求，以第一和第二级封装样式的任何组合配置的、半导体封装的任何组合以及其他电子部件能够被连接到PCB 52。在一些实施例中，电子器件50包括单个附接的半导体封装，而其他实施例需要多个互连的封装。通过在单个衬底上组合一个或多个半导体封装，制造商能够将预制部件并入电子器件和系统中。因为半导体封装包括成熟的功能，所以电子器件能够使用不那么昂贵的部件和精简了的制造工艺来制造。结果得到的器件不太可能失效并且对于制造而言不那么昂贵，从而对于消费者来说导致较低的成本。
图2a-2c示出了示例性的半导体封装。图2a示意了安装在PCB 52上的DIP 64的更多细节。半导体小片74包括包含形成在小片内并且根据小片的电设计电互连的模拟或数字电路的有源区域，所述模拟或数字电路被实现为有源器件、无源器件、导电层以及介电层。例如，所述电路能够包括一个或多个晶体管、二极管、电感器、电容器、电阻器以及形成在半导体小片74的有源区域内的其他电路元件。接触垫76是诸如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金 (Au)或银(Ag)的导电材料的一个或多个层，并且被电连接到形成在半导体小片74内的电路元件。在DIP 64的组装期间，使用金-硅共晶层或诸如热环氧树脂或环氧树脂的粘结材料将半导体小片74安装到中间载体78上。封装主体包括诸如聚合物或陶瓷的绝缘封装材料。导体引线80和接合线82在半导体小片74与PCB 52之间提供电互连。密封剂84被沉积在封装上以通过防止湿气和微粒进入封装并且污染半导体小片74或接合线82来进行环境保护。
图2b示意了安装在PCB 52上的BCC 62的更多细节。使用底层填料或环氧树脂粘结材料92将半导体小片88安装到载体90上。接合线94在接触垫96与98之间提供第一级封装互连。成型化合物或密封剂100被沉积在半导体小片88和接合线94上以为器件提供物理支撑和电隔离。使用诸如电解电镀或无电镀的适当的金属沉积工艺在PCB 52的表面上形成接触垫102以防止氧化。接触垫102被电连接到PCB 52中的一个或多个导电信号迹线54。凸起104被形成在BCC 62的接触垫98与PCB 52的接触垫102之间。
在图2c中，以倒装芯片式第一级封装将半导体小片58面朝下安装到中间载体106上。半导体小片58的有源区域108包含根据小片的电设计形成的模拟或数字电路，所述模拟或数字电路被实现为有源器件、无源器件、导电层以及介电层。例如，所述电路能够包括一个或多个晶体管、二极管、电感器、电容器、电阻器以及有源区域108内的其他电路元件。半导体小片58通过凸起110被电性地并且机械地连接到载体106。
使用凸起112以BGA式第二级封装将BGA 60电性地并且机械地连接到PCB 52。通过凸起110、信号线114以及凸起112将半导体小片58电连接到PCB 52中的导电信号迹线54。成型化合物或密封剂116被沉积在半导体小片58和载体106上以为器件提供物理支撑和电隔离。倒装芯片半导体器件提供了从半导体小片58上的有源器件到PCB 52上的导电轨迹的短的导电路径，以便减少信号传播距离、降低电容并且改善总的电路性能。在另一实施例中，能够在没有中间载体106的情况下使用倒装芯片式第一级封装直接将半导体小片58机械地并且电性地连接到PCB 52。
图3a示出了具有用于结构支撑的基衬底材料122的半导体晶片120，所述基衬底材料122诸如为硅、锗、砷化镓、磷化铟或碳化硅。多个半导体小片或部件124形成在晶片120上，被非有源的小片间晶片区域或锯齿型街沟126分开，如在上文中所描述的那样。锯齿型街沟126提供了切割区域以将半导体晶片120分割成单独的半导体小片124。
图3b示出了半导体晶片120的一部分的截面图。每个半导体小片124都具有背表面128和有源表面130，所述有源表面130包含形成在小片内并且根据小片的电设计和功能电互连的模拟或数字电路，所述模拟或数字电路被实现为有源器件、无源器件、导电层以及介电层。例如，所述电路可以包括一个或多个晶体管、二极管以及形成在有源表面130内的其他电路元件以实现模拟电路或数字电路，诸如数字信号处理器(DSP)、ASIC、存储器或其他信号处理电路。半导体小片124还可以包含诸如电感器、电容器以及电阻器的集成无源器件(IPD)，以用于RF信号处理。
使用PVD、CVD、电解电镀、无电镀工艺或其他适当的金属沉积工艺在有源表面130上形成导电层132。导电层132可以是Al、Cu、Sn、Ni、Au、Ag或其他适当的导电材料的一个或多个层。导电层132作为电连接到有源表面130上的电路的接触垫进行操作。导电层132能够被形成为并排置于距半导体小片124的边缘第一距离处的接触垫，如图3b所示。备选地，导电层132能够被形成为以多行偏移的接触垫，使得第一行接触垫被置于距小片的边缘第一距离处，并且与第一行交替的第二行接触垫被置于距小片的边缘第二距离处。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在有源表面130和导电层132上形成绝缘或钝化层134。绝缘层134包含二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)或者具有类似结构和绝缘特性的其他材料的一个或多个层。使用激光器136通过激光直接烧蚀(LDA)去除绝缘层134的一部分以暴露导电层132。备选地，经由图形化的光致抗蚀剂层通过蚀刻工艺去除绝缘层134的一部分以暴露导电层132。
在图3c中，半导体晶片120的背表面128经历使用研磨机137的背面研磨操作，在这之后是用于减小晶片的厚度的抛光步骤。在图3d中，小片附接粘结膜或胶带138在分割之前被层叠到经抛光的背表面128上。
在图3e中，使用锯条或激光切割工具139贯穿锯齿型街沟126将半导体晶片120分割成单独的半导体小片124。
图4a-4g示意了内插板衬底的形成，其中半导体小片被安装到该衬底上。图4a示出了芯衬底(core substrate)140，其包括采用酚醛棉纸、环氧树脂、树脂、玻璃布、毛玻璃、聚酯及其他增强纤维或织物的组合的、聚四氟乙烯预浸渍(预浸处理)、FR-4、FR-1、CEM-1或CEM-3的一个或多个层叠的层。备选地，芯衬底140包含一个或多个绝缘或介电层。
使用激光钻孔、机械钻孔或深反应离子蚀刻(DRIE)贯穿芯衬底140形成多个通孔。使用电解电镀、无电镀工艺或其他适当的沉积工艺以Al、Cu、Sn、Ni、Au、Ag、钛(Ti)、钨(W)或其他适当的导电材料来填充通孔以形成z向垂直互连导电通孔144。在一个实施例中，Cu通过无电镀和电镀术沉积在通孔的侧壁上。通孔用导电胶或带填料的堵塞树脂来填充。
使用诸如印刷、PVD、CVD、溅射、电解电镀以及无电镀的图形化和金属沉积工艺在芯衬底140的第一表面和导电通孔144上形成导电层或再分布层(RDL) 146。导电层146包括Al、Cu、Sn、Ni、Au、Ag或其他适当的导电材料的一个或多个层。导电层146被电连接到导电通孔144。
使用PVD、CVD、印刷、旋涂、喷涂、狭缝式涂布、滚涂、层叠、烧结或热氧化在芯衬底140的第一表面和导电层146上形成绝缘或钝化层148。绝缘层148包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、二氧化铪(HfO2)、苯并环丁烯(BCB)、聚酰亚胺(PI)、聚苯并恶唑(PBO)、有或没有填料或纤维的聚合物介电抗蚀剂或者具有类似结构和介电特性的其他材料的一个或多个层。在另一实施例中，绝缘层148是掩膜层。
使用诸如印刷、PVD、CVD、溅射、电解电镀以及无电镀的图形化和金属沉积工艺在芯衬底140的与第一表面相对的第二表面和导电通孔144上形成导电层或RDL 150。导电层150包括Al、Cu、Sn、Ni、Au、Ag或其他适当的导电材料的一个或多个层。导电层150被电连接到导电通孔144和导电层146。在另一实施例中，在形成导电层146和/或导电层150之后贯穿芯衬底140形成导电通孔144。
使用PVD、CVD、印刷、旋涂、喷涂、狭缝式涂布、滚涂、层叠、烧结或热氧化在芯衬底140的第二表面和导电层150上形成绝缘或钝化层152。绝缘层152包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PI、PBO、有或没有填料或纤维的聚合物介电抗蚀剂或者具有类似结构和介电特性的其他材料的一个或多个层。在一个实施例中，绝缘层148和152包括用于增强弯曲强度的填料和纤维，诸如硅石、Al2O3或玻璃纤维。使用激光器154通过LDA去除绝缘层152的一部分以暴露导电层150。在另一实施例中，绝缘层152是掩膜层。
结果得到的内插板衬底155根据半导体小片124的电功能经由导电层146和150以及导电通孔144垂直地并且横向地跨衬底提供电互连。衬底155在中间阶段，即在安装半导体小片124之前被检查和测试以通过开路/短路探测或自动范围检查而被已知为良好。根据半导体小片124的设计和功能，导电层146和150的部分与导电通孔144是电共用的或电绝缘的。
衬底155还可以是包括有源表面的多层柔性层压制品、陶瓷、铜箔、玻璃或半导体晶片，所述有源表面包含用于实现模拟电路或数字电路的一个或多个晶体管、二极管及其他电路元件。
在图4b中，引线柱156通过压缩接合、缝编接合、球焊接合或楔焊接合附接到衬底155的导电层146。引线柱156在与作为基部156a被示出的导电层146接触时压缩。杆部156b能够被压缩到(cut to)适当长度，例如250-500 µm。在一个实施例中，引线柱156包括Cu、Al或金属合金。引线柱156提供3D垂直互连结构。
图4c示出了其中导电层150被绝缘层152覆盖的衬底155的实施例，即导电层150没有通过LDA或蚀刻工艺被暴露。
在图4d中，在背表面128朝衬底定向的情况下使用例如拾取和放置操作将来自图3c的半导体小片124安装到内插板衬底155上。采用小片附接粘结剂或膜138将半导体小片124固定到衬底155的绝缘层148上。图4e示出了半导体小片124安装到衬底155上作为重构晶片158。半导体小片124是在安装到衬底155上之前已被测试的已知为良好的小片(KGD)。衬底155具有足够的尺寸来容纳多个半导体小片。
在另一实施例中，诸如可脱离干膜、介电抗蚀剂或光致抗蚀剂的保护层160被形成在绝缘层134和导电层132上，如图4f所示。
在另一实施例中，密封剂162被沉积在半导体小片124周围。积层互连结构164被形成在绝缘层134、导电层132以及密封剂162上，如图4g所示。积层互连结构164包括绝缘层166、导电层168、绝缘层170、导电层172以及绝缘层174。积层互连结构164在中间阶段，即在分割之前被检查和测试以通过开路/短路探测或自动范围检查而被已知为良好。使用锯条或激光切割工具176贯穿衬底155分割重构晶片158以分开半导体小片124。
图5a-5h相对于图1和2a-2c示意了在Fo-WLCSP中形成积层互连结构和内插板衬底作为双侧互连结构的过程。图5a示出了载体或临时衬底180，其包含用于结构支撑的、诸如硅、聚合物、氧化铍、玻璃、铁合金或其他适当的低成本刚性材料的、可再使用或牺牲的基材。载体180可以是圆形的或矩形的。包括可压缩粘结脱离(releasing)膜184的界面层或双侧胶带182作为临时粘结接合膜、蚀刻停止层或热脱离层(thermal release layer)形成在载体180上。半导体小片124在被安装到衬底140上时被接合到载体180上的可压缩粘结脱离膜184，其中积层互连结构164朝载体定向。图5b示出了安装到载体180上的半导体小片124和衬底140，其中导电层172和绝缘层174被嵌入载体180上的可压缩脱离膜184内。衬底180具有足够的尺寸来容纳多个半导体小片124。
在图5c中，使用膏印刷(paste printing)、压缩成型、传递成型、液体封装成型、真空层叠、旋涂或其他适当的涂敷器将密封剂或成型化合物188沉积在载体180、衬底155、半导体小片124以及引线柱156上及它们的周围。密封剂188可以是聚合物合成材料，诸如带填料的环氧树脂、带填料的环氧丙烯酸酯或带适当填料的聚合物。密封剂188是不导电的并且在环境方面保护半导体器件免受外部元件和污染物影响。
在图5d中，载体180、界面层182以及可压缩脱离膜184通过化学蚀刻、机械剥离、化学机械平面化(CMP)、机械研磨、热烘、UV光、激光扫描或湿法剥离被去除。附加的背面研磨可以被应用于控制翘曲。使用激光器190通过LDA去除密封剂188的一部分以暴露引线柱156以及积层互连结构164的导电层172和绝缘层174。
在图5e中，使用PVD、CVD、印刷、旋涂、喷涂、狭缝式涂布、滚涂、层叠、烧结或热氧化在密封剂188、积层互连结构164以及所暴露的引线柱156上形成绝缘或钝化层196。绝缘层196包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、有或没有填料或纤维的聚合物介电抗蚀剂或者具有类似结构和绝缘特性的其他材料的一个或多个层。
使用诸如印刷、PVD、CVD、溅射、电解电镀以及无电镀的图形化和金属沉积工艺在绝缘层196、积层互连结构164以及所暴露的引线柱156上形成导电层或RDL 198。导电层198包括Al、Cu、Ti、TiW、Sn、Ni、Au、Ag或其他适当的导电材料的一个或多个层。导电层198的一个部分被电连接到积层互连结构164的导电层172。导电层198的另一部分被电连接到引线柱156。取决于半导体小片124的设计和功能，导电层198的其他部分可以是电共用的或电绝缘的。
使用PVD、CVD、印刷、旋涂、喷涂、狭缝式涂布、滚涂、层叠、烧结或热氧化在绝缘层196和导电层198上形成绝缘或钝化层200。绝缘层200包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、有或没有填料或纤维的聚合物介电抗蚀剂或者具有类似结构和绝缘特性的其他材料的一个或多个层。通过LDA或蚀刻工艺经由图形化的光致抗蚀剂层去除绝缘层200的一部分以暴露导电层198。
使用蒸发、电解电镀、无电镀、球滴(ball drop)或丝网印刷工艺将导电凸起材料沉积在导电层198上。在可选焊剂溶液的情况下，凸起材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸起材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用适当的附接或接合工艺将凸起材料接合到导电层198上。在一个实施例中，通过将凸起材料加热至其熔点以上使该材料回流以形成球体或凸起202。在一些应用中，凸起202被二次回流以改进与导电层198的电接触。在一个实施例中，凸起202被形成在具有润湿层、阻挡层以及粘结层的UBM上。凸起还可以被压缩接合或热压缩接合到导电层198上。凸起202表示能够被形成在导电层198上的一种类型的互连结构。该互连结构还能够使用接合线、导电胶、柱形凸起、微凸起或其他电互连。
绝缘层196和202与导电层198及凸起202的组合构成积层互连结构204。积层互连结构204在附加的器件集成之前被检查和测试以被已知为良好。
在图5f中，背面研磨胶带或支撑胶带194被应用在积层互连结构204上。用研磨机192以研磨操作去除密封剂188的一部分以使表面平整并且暴露衬底155的绝缘层152。化学蚀刻或CMP工艺还能够被用于去除由研磨操作产生的机械损伤并且使密封剂188平整。图5g示出了在研磨操作之后的衬底155，其中通过激光器193和/或剥离及清洗工艺从导电层150和绝缘层152去除任何剩余的密封剂。
在图5h中，背面研磨胶带或支撑胶带194被去除并且使用锯条或激光切割工具208贯穿密封剂188和积层互连结构204将半导体小片124分割成单独的双侧Fo-WLCSP 210。图6示出了分割之后的Fo-WLCSP 210。半导体小片124经由积层互连结构164、积层互连结构204以及引线柱156电连接到衬底155以用于与外部器件的连接。衬底155和积层互连结构164和204在Fo-WLCSP 210的相对侧(双侧)为半导体小片124提供垂直和横向互连。衬底155在不同时间形成并且独立于积层互连结构164和204。衬底155在小片安装之前的形成和测试简化了制造工艺并且降低了成本。其中引线柱156在衬底155与积层互连结构之间提供垂直互连的积层互连结构164和204的稍后形成在Fo-WLCSP 210的相对侧使用于半导体小片124的垂直和横向互连完整。
在另一实施例中，从图4g继续，半导体小片124被安装到载体220上，其中衬底140的绝缘层152朝该载体定向，如图7a所示。导电层150可以被绝缘层152完全覆盖。高温(大于200°C)可脱离接合胶带222被施加在载体220上。备选地，具有可选填料或纤维的永久介电接合层222被施加在载体220上。衬底140的导电层146和绝缘层148被压缩到载体220上的可脱离接合胶带222中。与图4f中的保护层160类似的保护层可以被形成在积层互连结构164的绝缘层174上。备选地，绝缘层174可以是带填料并且厚度大于25 µm的介电材料。
使用膏印刷、压缩成型、传递成型、液体封装成型、真空层叠、旋涂或其他适当的涂敷器将密封剂或成型化合物226沉积在载体220、衬底155、半导体小片124以及引线柱156上。密封剂226可以是聚合物合成材料，诸如带填料的环氧树脂、带填料的环氧丙烯酸酯或带适当填料的聚合物。密封剂226是不导电的并且在环境方面保护半导体器件不受外部元件和污染物影响。
在图7b中，使用激光器228通过LDA去除密封剂226的一部分以暴露引线柱156以及积层互连结构164的导电层172和绝缘层174。
在图7c中，使用PVD、CVD、印刷、旋涂、喷涂、狭缝式涂布、滚涂、层叠、烧结或热氧化在密封剂226、积层互连结构164以及所暴露的引线柱156上形成绝缘或钝化层230。绝缘层230包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、有或没有填料或纤维的聚合物介电抗蚀剂或者具有类似结构和绝缘特性的其他材料的一个或多个层。
使用诸如印刷、PVD、CVD、溅射、电解电镀以及无电镀的图形化和金属沉积工艺在绝缘层230、积层互连结构164以及所暴露的引线柱156上形成导电层或RDL 232。导电层232包括Al、Cu、Ti、TiW、Sn、Ni、Au、Ag或其他适当的导电材料的一个或多个层。导电层232的一个部分被电连接到积层互连结构164的导电层172。导电层232的另一部分被电连接到引线柱156。取决于半导体小片124的设计和功能，导电层232的其他部分可以是电共用的或电绝缘的。
使用PVD、CVD、印刷、旋涂、喷涂、狭缝式涂布、滚涂、层叠、烧结或热氧化在绝缘层230和导电层232上形成绝缘或钝化层234。绝缘层234包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、有或没有填料或纤维的聚合物介电抗蚀剂或者具有类似结构和绝缘特性的其他材料的一个或多个层。通过LDA或蚀刻工艺经由图形化的光致抗蚀剂层去除绝缘层234的一部分以暴露导电层232。
使用蒸发、电解电镀、无电镀、球滴或丝网印刷工艺将导电凸起材料沉积在导电层232上。在可选焊剂溶液的情况下，凸起材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸起材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用适当的附接或接合工艺将凸起材料接合到导电层232上。在一个实施例中，通过将凸起材料加热至其熔点以上使该材料回流以形成球体或凸起236。在一些应用中，凸起236被二次回流以改进与导电层232的电接触。在一个实施例中，凸起236被形成在具有润湿层、阻挡层以及粘结层的UBM上。凸起还可以被压缩接合或热压缩接合到导电层232上。凸起236表示能够被形成在导电层232上的一种类型的互连结构。该互连结构还能够使用接合线、导电胶、柱形凸起、微凸起或其他电互连。
绝缘层230和234与导电层232及凸起236的组合构成积层互连结构238。积层互连结构238在附加的器件集成之前被检查和测试以被已知为良好。
在图7d中，载体220和可脱离接合胶带222通过化学蚀刻、机械剥离、CMP、机械研磨、热烘、UV光、激光扫描或湿法剥离被去除。载体220在永久接合材料222的情况下可以部分地被去除。使用锯条或激光切割工具239贯穿密封剂226和积层互连层238将半导体小片124分割成单独的双侧Fo-WLCSP 240。图8示出了分割之后的Fo-WLCSP 240。半导体小片124经由积层互连结构164、积层互连结构238以及引线柱156被电连接到衬底155以用于与外部器件的连接。衬底155以及积层互连结构164和238在Fo-WLCSP 240的相对侧(双侧)为半导体小片124提供垂直和横向互连。衬底155在不同时间形成并且独立于积层互连结构164和238。衬底155在小片安装之前的形成和测试简化了制造工艺并且降低了成本。其中引线柱156在衬底155与积层互连结构之间提供垂直互连的积层互连结构164和238的稍后形成在Fo-WLCSP 240的相对侧使用于半导体小片124的垂直和横向互连完整。
在另一实施例中，从图4g继续，衬底155在半导体小片124被安装到衬底上的情况下保持为未被分割(见图4c)，如图9a所示。密封剂或成型化合物242被沉积在衬底155、半导体小片124以及引线柱156上。
在图9b中，使用激光器243通过LDA去除密封剂242的一部分以暴露引线柱156以及积层互连结构164的导电层172和绝缘层174。
在图9c中，使用PVD、CVD、印刷、旋涂、喷涂、狭缝式涂布、滚涂、层叠、烧结或热氧化在密封剂242、积层互连结构164以及所暴露的引线柱156上形成绝缘或钝化层244。绝缘层244包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、有或没有填料或纤维的聚合物介电抗蚀剂或者具有类似结构和绝缘特性的其他材料的一个或多个层。
使用诸如印刷、PVD、CVD、溅射、电解电镀以及无电镀的图形化和金属沉积工艺在绝缘层244、积层互连结构164以及所暴露的引线柱156上形成导电层或RDL 246。导电层246包括Al、Cu、Sn、Ni、Au、Ag或其他适当的导电材料的一个或多个层。导电层246的一个部分被电连接到积层互连结构164的导电层172。导电层246的另一部分被电连接到引线柱156。取决于半导体小片124的设计和功能，导电层246的其他部分可以是电共用的或电绝缘的。
使用PVD、CVD、印刷、旋涂、喷涂、狭缝式涂布、滚涂、层叠、烧结或热氧化在绝缘层244和导电层246上形成绝缘或钝化层248。绝缘层248包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、有或没有填料或纤维的聚合物介电抗蚀剂或者具有类似结构和绝缘特性的其他材料的一个或多个层。通过LDA或蚀刻工艺经由图形化的光致抗蚀剂层去除绝缘层248的一部分以暴露导电层246。
使用蒸发、电解电镀、无电镀、球滴或丝网印刷工艺将导电凸起材料沉积在导电层246上。在可选焊剂溶液的情况下，凸起材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸起材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用适当的附接或接合工艺将凸起材料接合到导电层246上。在一个实施例中，通过将凸起材料加热到其熔点以上使该材料回流以形成球体或凸起250。在一些应用中，凸起250被二次回流以改进与导电层246的电接触。在一个实施例中，凸起250被形成在具有润湿层、阻挡层以及粘结层的UBM上。凸起还可以被压缩接合或热压缩接合到导电层246上。凸起250表示能够被形成在导电层246上的一种类型的互连结构。该互连结构还能够使用接合线、导电胶、柱形凸起、微凸起或其他电互连。
绝缘层244和248与导电层246及凸起250的组合构成积层互连结构252。积层互连结构252在附加的器件集成之前被检查和测试以被已知为良好。
在图9d中，使用激光器254通过LDA去除绝缘层152的一部分以暴露导电层150。使用锯条或激光切割工具255贯穿衬底155、密封剂242以及积层互连结构252将半导体小片124分割成单独的双侧Fo-WLCSP 256。图10示出了分割之后的Fo-WLCSP 256。半导体小片124经由积层互连结构164、积层互连结构252以及引线柱156被电连接到衬底155以用于与外部器件的连接。衬底155以及积层互连结构164和252在Fo-WLCSP 256的相对侧(双侧)为半导体小片124提供垂直和横向互连。衬底155在不同时间形成并且独立于积层互连结构164和252。衬底155在小片安装之前的形成和测试简化了制造工艺并且降低了成本。其中引线柱156在衬底155与积层互连结构之间提供垂直互连的积层互连结构164和252的稍后形成在Fo-WLCSP 256的相对侧使用于半导体小片124的垂直和横向互连完整。
图11示意了与图10类似的Fo-WLCSP 260的实施例，其中柱形凸起262被置于衬底155与积层互连结构252之间。柱形凸起262将衬底155的导电层146电连接到积层互连结构252的导电层246。积层互连结构164包括至少一个RDL层，例如导电层168。
图12示意了与图5a-5h类似的Fo-WLCSP 270的实施例，其中柱形凸起272被置于衬底155与积层互连结构204之间。柱形凸起272将衬底155的导电层146电连接到积层互连结构204的导电层198。密封剂188沿衬底155的侧表面延伸到绝缘层152的上表面。积层互连结构164包括至少一个RDL层，例如导电层168。
图13示意了与图5a-5h类似的Fo-WLCSP 280的实施例，其中柱形凸起282被置于衬底155与积层互连结构204之间。柱形凸起282将衬底155的导电层146电连接到积层互连结构204的导电层198。密封剂188沿衬底155的侧表面延伸到绝缘层152的上表面。密封剂188覆盖半导体小片124的侧表面以及该半导体小片的有源表面130的一部分。
图14示意了与图5a-5h类似的Fo-WLCSP 290的实施例，其中柱形凸起292被置于衬底155与积层互连结构204之间。柱形凸起292将衬底155的导电层146电连接到积层互连结构204的导电层198。密封剂188覆盖半导体小片124的侧表面和该半导体小片的有源表面130的一部分。衬底155被去除并且用掩膜层294代替。通过LDA或蚀刻工艺经由图形化的光致抗蚀剂层去除掩膜层294的一部分以暴露导电层146。
图15示意了与图5a-5h类似的Fo-WLCSP 300的实施例，其中引线框302被嵌入密封剂304内。柱形凸起306被置于引线框302与积层互连结构204之间。密封剂188覆盖半导体小片124的侧表面和该半导体小片的有源表面130的一部分。通过LDA或蚀刻工艺经由图形化的光致抗蚀剂层去除密封剂304的一部分以暴露引线框302。
图16a-16f相对于图1和2a-2c示意了在Fo-WLCSP中形成顶部和底部积层互连结构的过程。图16a示出了用于结构支撑的载体或临时衬底310，所述载体或临时衬底310包含诸如硅、聚合物、氧化铍、玻璃或其他适当的低成本刚性材料的牺牲基材。
使用PVD、CVD、印刷、旋涂、喷涂、狭缝式涂布、滚涂、层叠、烧结或热氧化在载体310上形成绝缘或钝化层312。绝缘层312包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、有或没有填料或纤维的聚合物介电抗蚀剂或者具有类似结构和绝缘特性的其他材料的一个或多个层。在一个实施例中，绝缘层312包括用于增强弯曲强度的玻璃布、玻璃丝网、填料或纤维，诸如硅石、Al2O3或玻璃纤维。
使用诸如铜箔层叠、印刷、PVD、CVD、喷溅、电解电镀以及无电镀的图形化和金属沉积工艺在绝缘层312上形成导电层或RDL 314。导电层314包括Al、Cu、Sn、Ni、Au、Ag或其他适当的导电材料的一个或多个层。在一个实施例中，导电层314是用光致抗蚀剂或油墨印刷图形化的铜箔。备选地，导电层314包括Ti (TiW)/Cu种子层，在其之后是光刻和选择性电镀。取决于半导体小片的设计和功能，导电层314的部分可以是电共用的或电绝缘的。
在图16b中，使用PVD、CVD、印刷、旋涂、喷涂、狭缝式涂布、滚涂、层叠、烧结或热氧化在绝缘层312和导电层314上形成绝缘或钝化层316。绝缘层316包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、有或没有填料或纤维的聚合物介电抗蚀剂或者具有类似结构和绝缘特性的其他材料的一个或多个层。在一个实施例中，绝缘层316包括用于增强弯曲强度的玻璃布、玻璃丝网、填料或纤维，诸如硅石、Al2O3或玻璃纤维。使用激光器318通过LDA去除绝缘层316的一部分以暴露导电层314。备选地，通过蚀刻工艺经由图形化的光致抗蚀剂层去除绝缘层316的一部分以暴露导电层314。导电层314和绝缘层316在中间阶段，即在安装半导体小片320之前被检查和测试以通过开路/短路探测或自动范围检查而被已知为良好。
图16c示出了来自与图3a类似的半导体晶片的半导体小片320，其中背表面322和有源表面324包含形成在小片内并且根据小片的电设计和功能电互连的模拟或数字电路，所述模拟或数字电路被实现为有源器件、无源器件、导电层以及介电层。例如，该电路可以包括形成在有源表面324内以实现诸如DSP、ASIC、存储器的模拟电路或数字电路或者其他信号处理电路的一个或多个晶体管、二极管及其他电路元件。半导体小片320还可以包含诸如电感器、电容器以及电阻器的IPD，用于RF信号处理。
使用PVD、CVD、电解电镀、无电镀工艺或其他适当的金属沉积工艺在有源表面324上形成导电层326。导电层326可以是Al、Cu、Sn、Ni、Au、Ag或其他适当的导电材料的一个或多个层。导电层326作为电连接到有源表面324上的电路的接触垫进行操作。
使用PVD、CVD、印刷、旋涂、喷涂、狭缝式涂布、滚涂、层叠、烧结或热氧化在有源表面324和导电层326上形成绝缘或钝化层328。绝缘层328包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、有或没有填料或纤维的聚合物介电抗蚀剂或者具有类似结构和绝缘特性的其他材料的一个或多个层。通过LDA或蚀刻工艺经由图形化的光致抗蚀剂层去除绝缘层328的一部分以暴露导电层326。
使用PVD、CVD、印刷、旋涂、喷涂、狭缝式涂布、滚涂、层叠、烧结或热氧化在绝缘层328和导电层326上形成绝缘或钝化层330。绝缘层330包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、有或没有填料或纤维的聚合物介电抗蚀剂或者具有类似结构和绝缘特性的其他材料的一个或多个层。通过LDA或蚀刻工艺经由图形化的光致抗蚀剂层去除绝缘层330的一部分以暴露导电层326。
使用PVD、CVD、印刷、旋涂、喷涂、狭缝式涂布、滚涂、层叠、烧结或热氧化在绝缘层330和导电层326上形成保护层332。保护层332包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或者具有类似结构和绝缘特性的其他材料的一个或多个层。
采用诸如环氧树脂的小片附接粘结剂334将半导体小片320安装到绝缘层316上。柱形凸起336被形成在导电层314上。使用导电胶340使分立半导体器件338冶金地并且电性地与导电层314耦合。分立半导体器件338可以是电感器、电容器、电阻器、晶体管或二极管。
在图16d中，使用膏印刷、压缩成型、传递成型、液体封装成型、真空层叠、旋涂或其他适当的涂敷器将密封剂或成型化合物342沉积在绝缘层316、半导体小片320、柱形凸起336以及分立半导体器件338上及它们的周围。密封剂342可以是聚合物合成材料，诸如带填料的环氧树脂、带填料的环氧丙烯酸酯或带适当填料的聚合物。密封剂342是不导电的并且在环境方面保护半导体器件不受外部元件和污染物影响。
在图16e中，保护层332被去除以暴露绝缘层330和密封剂342中的浅腔中的导电层326。使用PVD、CVD、印刷、旋涂、喷涂、狭缝式涂布、滚涂、层叠、烧结或热氧化在半导体小片320、密封剂342以及柱形凸起336上形成绝缘或钝化层350。绝缘层350包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、有或没有填料或纤维的聚合物介电抗蚀剂或者具有类似结构和绝缘特性的其他材料的一个或多个层。通过LDA或蚀刻工艺经由图形化的光致抗蚀剂层去除绝缘层350的一部分以暴露导电层326和柱形凸起336。
使用诸如印刷、PVD、CVD、溅射、电解电镀以及无电镀的图形化和金属沉积工艺在绝缘层350和柱形凸起336上形成导电层或RDL 352。导电层352包括Al、Cu、Sn、Ni、Au、Ag或其他适当的导电材料的一个或多个层。导电层352的一个部分被电连接到半导体小片320的导电层326。导电层352的另一部分被电连接到柱形凸起336。取决于半导体小片320的设计和功能，导电层352的其他部分可以是电共用的或电绝缘的。
使用PVD、CVD、印刷、旋涂、喷涂、狭缝式涂布、滚涂、层叠、烧结或热氧化在绝缘层350和导电层352上形成绝缘或钝化层354。绝缘层354包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、有或没有填料或纤维的聚合物介电抗蚀剂或者具有类似结构和绝缘特性的其他材料的一个或多个层。通过LDA或蚀刻工艺经由图形化的光致抗蚀剂层去除绝缘层354的一部分以暴露导电层326和柱形凸起352。
使用诸如印刷、PVD、CVD、溅射、电解电镀以及无电镀的图形化和金属沉积工艺在绝缘层354和导电层352上形成导电层或RDL 356。导电层356包括Al、Cu、Sn、Ni、Au、Ag或其他适当的导电材料的一个或多个层。导电层356的一个部分被电连接到导电层352。取决于半导体小片320的设计和功能，导电层356的其他部分可以是电共用的或电绝缘的。
使用PVD、CVD、印刷、旋涂、喷涂、狭缝式涂布、滚涂、层叠、烧结或热氧化在绝缘层354和导电层356上形成绝缘或钝化层358。绝缘层358包含SiO2、Si3N4、SiON、Ta2O5、Al2O3、有或没有填料或纤维的聚合物介电抗蚀剂或者具有类似结构和绝缘特性的其他材料的一个或多个层。通过LDA或蚀刻工艺经由图形化的光致抗蚀剂层去除绝缘层358的一部分以暴露导电层356。
使用蒸发、电解电镀、无电镀、球滴或丝网印刷工艺将导电凸起材料沉积在导电层356上。在可选焊剂溶液的情况下，凸起材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸起材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用适当的附接或接合工艺将凸起材料接合到导电层356上。在一个实施例中，通过将凸起材料加热到其熔点以上使该材料回流以形成球体或凸起360。在一些应用中，凸起360被二次回流以改进与导电层356的电接触。在一个实施例中，凸起360被形成在具有润湿层、阻挡层以及粘结层的UBM上。凸起还可以被压缩接合或热压缩接合到导电层356上。凸起360表示能够被形成在导电层356上的一种类型的互连结构。该互连结构还能够使用接合线、导电胶、柱形凸起、微凸起或其他电互连。
绝缘层350、354和358与导电层352和356及凸起360的组合构成积层互连结构362。积层互连结构362在附加的器件集成之前被检查和测试以被已知为良好。
在图16f中，通过化学蚀刻、机械剥离、CMP、机械研磨、热烘、UV光、激光扫描或湿法剥离去除载体310以暴露导电层314和绝缘层316。附加的背面研磨可以被应用于控制翘曲。使用激光器366通过LDA去除绝缘层312的一部分以暴露导电层314。备选地，通过LDA或蚀刻工艺经由图形化的光致抗蚀剂层去除绝缘层312的一部分以暴露导电层314。
在Fo-WLCSP 370中，半导体小片320经由积层互连结构362和柱形凸起336被电连接到导电层314。积层互连结构362和导电层314在Fo-WLCSP 370的相对侧(双侧)为半导体小片320提供垂直和横向互连。导电层314在不同时间形成并且独立于积层互连结构362。导电层314在小片安装之前的形成和测试简化了制造工艺并且降低了成本。其中柱形凸起336在导电层314与积层互连结构之间提供垂直互连的积层互连结构362的稍后形成在Fo-WLCSP 370的相对侧使用于半导体小片320的垂直和横向互连完整。
虽然已经详细地示意了本发明的一个或多个实施例，但技术人员将理解，可以对那些实施例进行修改和调整而不背离如在以下权利要求中所阐述的本发明的范围。

Claims (15)

1.一种制作半导体器件的方法，其包括：
提供衬底，所述衬底包括在所述衬底的表面上形成的第一导电层；
在所述衬底的所述表面上形成多个引线柱；
将半导体小片安装到所述引线柱之间的所述衬底的表面上；
在与所述衬底相对的所述半导体小片的表面上形成第一互连结构；
提供载体；
将所述衬底、引线柱、半导体小片和第一互连结构布置在所述载体上，其中所述第一互连结构朝所述载体来定向；
将第一密封剂沉积在所述载体、衬底、半导体小片和第一互连结构上；
去除所述载体；以及
在所述第一密封剂和第一互连结构上形成第二互连结构，并且在去除所述载体后所述第二互连结构电连接到所述引线柱。
2.根据权利要求1所述的方法，其还包括：
在所述半导体小片周围沉积第二密封剂；以及
在所述半导体小片和第二密封剂上形成所述第一互连结构。
3.根据权利要求1所述的方法，其还包括从所述第一互连结构上去除所述第一密封剂的一部分。
4.根据权利要求1所述的方法，其还包括从所述衬底上去除所述第一密封剂的一部分。
5.一种制作半导体器件的方法，其包括：
提供第一互连结构；
提供半导体小片；
将所述半导体小片安装到所述第一互连结构上；
在所述第一互连结构上形成多个柱形凸起；
将所述第一互连结构、半导体小片以及柱形凸起布置在载体上，其中所述半导体小片位于所述载体与所述第一互连结构之间；
将密封剂沉积在所述第一互连结构、半导体小片和柱形凸起上；
在沉积所述密封剂之后去除所述载体；以及
在去除所述载体之后在所述密封剂和半导体小片上形成第二互连结构，其中所述半导体小片布置在所述第一互连结构和所述第二互连结构之间。
6.根据权利要求5所述的方法，还包括在沉积所述密封剂之前通过下列方式在所述半导体小片上形成第三互连结构：
在所述半导体小片上形成第一绝缘层；
在所述第一绝缘层上形成第一导电层；以及
在所述第一导电层上形成第二绝缘层。
7.根据权利要求6所述的方法，其还包括通过激光直接烧蚀去除所述第一绝缘层的一部分。
8.根据权利要求6所述的方法，其还包括：
在所述第二绝缘层上形成第二导电层；以及
在所述第二导电层上形成第三绝缘层。
9.根据权利要求5所述的方法，其中形成所述第二互连结构包括：
在所述密封剂和半导体小片上形成第一绝缘层；
在所述第一绝缘层上形成第一导电层，其中所述第一导电层接触所述柱形凸起；
在所述第一绝缘层和第一导电层上形成第二绝缘层；以及
在所述第二绝缘层和第一导电层上形成导电凸起。
10.一种半导体器件，其包括：
衬底；
形成在所述衬底上的垂直互连结构；
安装到所述衬底上的半导体小片；
形成在所述半导体小片上的积层互连结构，其中所述积层互连结构包括第一导电层和布置在所述第一导电层上的绝缘层；
沉积在所述衬底、半导体小片、积层互连结构和垂直互连结构上的第一密封剂，其中所述第一导电层从所述第一密封剂暴露，其中所述第一密封剂覆盖与所述半导体小片相对的所述衬底的表面；以及
形成在所述第一密封剂和积层互连结构上的第二互连结构。
11.根据权利要求10所述的半导体器件，其中所述衬底包括形成在所述衬底的第一和第二相反表面上的第二导电层和第三导电层。
12.根据权利要求10所述的半导体器件，其还包括沉积在所述半导体小片周围的第二密封剂，其中所述积层互连结构被形成在所述半导体小片和第二密封剂上。
13.根据权利要求10所述的半导体器件，其中所述第一密封剂被形成在所述半导体小片的一部分上。
14.根据权利要求10所述的半导体器件，其中所述第一密封剂被形成在所述衬底的侧表面上。
15.根据权利要求10所述的半导体器件，其中所述垂直互连结构包括引线柱或柱形凸起。
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US9385052B2 (en) 2016-07-05
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US10163737B2 (en) 2018-12-25
CN103681397B (zh) 2018-09-04
SG10201601160XA (en) 2016-03-30
US20160276232A1 (en) 2016-09-22
US20230096463A1 (en) 2023-03-30
SG10201601117YA (en) 2016-03-30
KR102205119B1 (ko) 2021-01-20
SG2013056270A (en) 2014-04-28
CN103681468A (zh) 2014-03-26
US10192796B2 (en) 2019-01-29
KR102067840B1 (ko) 2020-02-11
US20140077362A1 (en) 2014-03-20
KR20140035803A (ko) 2014-03-24
SG10201601155UA (en) 2016-03-30
CN103681468B (zh) 2019-08-30
US20140077361A1 (en) 2014-03-20
US20140077363A1 (en) 2014-03-20
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US11569136B2 (en) 2023-01-31
KR102126586B1 (ko) 2020-06-24
US9978654B2 (en) 2018-05-22
TW201411749A (zh) 2014-03-16
KR20200010521A (ko) 2020-01-30
KR20140035804A (ko) 2014-03-24
CN203644756U (zh) 2014-06-11
TW201411791A (zh) 2014-03-16
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US20190115268A1 (en) 2019-04-18
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