CN103681607B - 半导体器件及其制作方法 - Google Patents

半导体器件及其制作方法 Download PDF

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Publication number
CN103681607B
CN103681607B CN201310142037.3A CN201310142037A CN103681607B CN 103681607 B CN103681607 B CN 103681607B CN 201310142037 A CN201310142037 A CN 201310142037A CN 103681607 B CN103681607 B CN 103681607B
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substrate
conductive column
semiconductor
semiconductor element
sealant
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CN103681607A (zh
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沈权
沈一权
俊谟具
P.C.马里穆图
林耀剑
林诗轩
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

半导体器件及其制作方法。一种半导体器件，具有包括基底和从基底延伸的多个导电柱的衬底。该衬底可以是晶片形状、面板、或已单体化的形式。导电柱可以具有圆形、矩形、锥形、或中间变窄的形状。半导体管芯通过基底中的开孔被设置在导电柱之间。半导体管芯在导电柱上面延伸或者被设置在导电柱的下面。密封剂沉积在半导体管芯上并且围绕导电柱。基底和密封剂的一部分被去除以电隔离导电柱。在半导体管芯、密封剂、和导电柱上形成互连结构。在半导体管芯、密封剂、和导电柱上形成绝缘层。半导体封装设置在半导体管芯上并电连接到导电柱。

Description

半导体器件及其制作方法
要求国内优先权
本申请要求于2012年9月17日提交的美国临时申请NO.61/702,171的权益，在此通过引用并入该申请。
技术领域
本发明总体上涉及半导体器件，且更具体地涉及一种半导体器件和用具有基底和从基底延伸的导电柱的衬底在嵌入式管芯封装中形成垂直互连结构的方法。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池、以及数字微镜器件（DMD）。
半导体器件执行多种功能，例如信号处理、高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的结构允许通过施加电场或基极电流（base current）或者通过掺杂工艺来操纵（manipulated）它的电导率。掺杂将杂质引入到半导体材料中以操纵和控制半导体器件的电导率。
半导体器件包括有源和无源电结构。有源结构（包括双极和场效应晶体管）控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构（包括电阻器、电容器、和电感器）产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速操作和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个半导体管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化（singulating）单个半导体管芯并且封装管芯以提供结构支撑和环境隔离。在此使用的术语“半导体管芯”指词的单数和复数形式两者，并且因此可以指单个半导体器件和多个半导体器件两者。
半导体制造的一个目标是制作更小的半导体器件。更小的器件通常消耗更少的功率、具有更高的性能、并且能够被更高效地制造。另外，更小的半导体器件具有更小的占位空间（footprint），其对于更小的终端产品来说是期望的。通过改善前端工艺导致产生具有更小、更高密度的有源和无源部件的半导体管芯可以实现更小的半导体管芯尺寸。通过改善电互连和封装材料，后端工艺可以产生具有更小占位空间的半导体器件封装。
半导体封装经常使用导电柱或通孔作为穿过例如在顶面互连结构和底面互连结构之间的围绕半导体管芯的密封剂的垂直互连。通常通过蚀刻或激光钻孔并填充或电镀导电材料来形成穿过密封剂的通孔。导电通孔的形成耗时并且需要昂贵的设备。
发明内容
存在对嵌入式管芯封装中的简单且节省成本的垂直互连结构的需要。因此，在一个实施例中，本发明是一种制作半导体器件的方法，包括以下步骤：提供包括基底和从基底延伸的多个导电柱的衬底，通过基底中的开孔将半导体管芯设置在导电柱之间，在半导体管芯上和导电柱周围沉积密封剂，以及除去基底以电隔离所述导电柱。
在另一个实施例中，本发明是一种制作半导体器件的方法，包括以下步骤：提供包括多个导电柱的衬底，将半导体管芯设置在导电柱之间，在半导体管芯上和导电柱周围沉积密封剂，以及在半导体管芯、密封剂和导电柱上形成互连结构。
在另一个实施例中，本发明是一种包括包含多个导电柱的衬底的半导体器件。半导体管芯设置在导电柱之间。密封剂沉积在半导体管芯上和导电柱周围。互连结构形成在半导体管芯、密封剂和导电柱上。
在另一个实施例中，本发明是一种包括多个导电柱的半导体器件，所述导电柱包含在所述导电柱之间的固定间隔。半导体管芯设置在导电柱之间。密封剂沉积在半导体管芯上和导电柱周围。互连结构形成在半导体管芯和导电柱上。
附图说明
图1示出了具有安装到其表面的不同类型封装的印刷电路板（PCB）；
图2a-2c示出安装到PCB的典型半导体封装的更多细节；
图3a-3c示出了具有由划片街区（saw street）分开的多个半导体管芯的半导体晶片；
图4示出了具有基底和从基底延伸的导电柱的晶片形状的衬底；
图5示出了具有基底和从基底延伸的导电柱的带状衬底；
图6a-6c示出了具有基底和从基底延伸的导电柱的已单体化的衬底；
图7a-7b示出了导电柱的替换实施例；
图8a-8t示出了用具有基底和导电柱的衬底在嵌入式管芯封装中形成垂直互连结构的工艺；
图9示出了具有作为垂直互连结构的导电柱的嵌入式管芯封装；以及
图10a-10b示出了具有嵌入式管芯封装的PoP布置，该嵌入式管芯封装具有作为垂直互连的导电柱。
具体实施方式
在下面参考附图的描述中以一个或多个实施例来描述本发明，在附图中相似的数字表示相同或类似的元件。虽然根据用来实现本发明的目的的最佳方式描述本发明，但是本领域技术人员将理解的是，它旨在覆盖可以被包含在由下列公开和各图所支持的所附权利要求及其等效物限定的本发明的精神和范围内的替代物、变型、和等效物。
半导体器件通常使用两种复杂的制造工艺来制造：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流流动的能力。无源电部件，例如电容器、电感器和电阻器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。掺杂工艺通过响应于电场或基极电流动态改变半导体材料电导率来改变有源器件中的半导体材料的电导率。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使得晶体管在施加电场或基极电流时能够促进或限制电流的流动。
通过具有不同电特性材料的层来形成有源和无源部件。所述层可以通过部分地由被沉积材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀、以及无电极电镀工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
后端制造指的是将已完成的晶片切割或单体化成单个半导体管芯，并且然后封装半导体管芯用以结构支撑和环境隔离。为了单体化半导体管芯，沿着被叫做划片街区或划线的晶片非功能区域刻划和断开所述晶片。使用激光切割工具或锯条来单体化晶片。在单体化之后，单个半导体管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块（stud bump）、导电胶、或线结合来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入到电系统中并且使得半导体器件的功能可用于其它系统部件。
图1示出具有芯片载体衬底或印刷电路板（PCB）52的电子器件50，所述芯片载体衬底或印刷电路板（PCB）52具有多个安装在其表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图1中示出了不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是蜂窝式电话、个人数字助理（PDA）、数码摄像机（DVC）、或其它电子通信装置的一部分。可替换地，电子器件50可以是被插入到计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。对于将被市场接受的产品而言，小型化和减轻重量是必要的。半导体器件之间的距离必须被减小以实现更高的密度。
在图1中，PCB 52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。使用蒸发、电解电镀、无电极电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线54形成在PCB 52的表面上或各层内。信号迹线54提供每个半导体封装、被安装部件以及其它外部系统部件之间的电通信。迹线54也为每个半导体封装提供了电源和地连接。
在一些实施例中，半导体器件具有两个封装级。第一级封装是用来将半导体管芯以机械和电气方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电气的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电气的方式直接安装到PCB。
为了说明的目的，几种第一级封装，包括结合线封装56和倒装芯片58，被示出在PCB 52上。另外，几种第二级封装，包括球栅阵列（BGA）60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、岸面栅格阵列（land grid array，LGA）66、多芯片模块（MCM）68、四侧无引脚扁平封装（quad flat non-leaded package，QFN）70、以及四侧扁平封装72被示出安装在PCB 52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，而其它实施例要求多互连封装。通过在单一衬底上组合一个或多个半导体封装，制造商可以在电子器件和系统中并入预先制作的部件。由于半导体封装包括复杂功能，因此电子器件可以使用不太昂贵的部件和流水线制造工艺来制造。所得到的器件不大可能失效并且制造起来花费较少，对用户而言导致更低的成本。
图2a-2c示出示例性的半导体封装。图2a示出安装在PCB 52上的DIP 64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电气设计形成在管芯内并电互连的有源器件、无源器件、导电层和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是一层或多层的导电材料，例如铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、或银（Ag），并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，利用金硅共晶层或粘附材料（例如热的环氧或环氧树脂）将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和结合线82提供半导体管芯74和PCB 52之间的电气互连。密封剂84被沉积在封装上以通过防止湿气和粒子进入封装并污染半导体管芯74或结合线82来保护环境。
图2b示出安装在PCB 52上的BCC 62的更多细节。半导体管芯88利用底层填充材料或环氧树脂粘附材料92被安装到载体90上。结合线94在接触焊盘96和98之间提供第一级封装互连。模塑料或密封剂100被沉积在半导体管芯88和结合线94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用合适的金属沉积工艺（例如电解电镀或无电极电镀）形成在PCB 52的表面上以防止氧化。接触焊盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104形成在BCC 62的接触焊盘98和PCB 52的接触焊盘102之间。
在图2C中，利用倒装芯片形式的第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电气设计形成的有源器件、无源器件、导电层、以及介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被电连接和机械连接到载体106。
BGA 60利用凸块112被电连接和机械连接到具有BGA型第二级封装的PCB 52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到PCB 52中的导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB 52。
图3a示出了具有用于结构支撑的基底衬底材料122（例如硅、锗、砷化镓、磷化铟、或碳化硅）的半导体晶片120。多个半导体管芯或部件124形成在晶片120上，被非有源的管芯间的晶片区域或划片街区126分开，如上所述。划片街区126提供切割区域以将半导体晶片120单体化成单个半导体管芯124。
图3b示出半导体晶片120的一部分的截面图。每个半导体管芯124具有后表面128和包含模拟或数字电路的有源表面130，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面130内的其它电路元件以实现模拟电路或数字电路，例如数字信号处理器（DSP）、ASIC、存储器、或其它信号处理电路。半导体管芯124也可以包括集成无源器件（IPD），例如电感器、电容器、和电阻器，用于RF信号处理。
利用PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在有源表面130上形成导电层132。导电层132可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层132用作电连接到有源表面130上的电路的接触焊盘。导电层132可以被形成为离半导体管芯124的边缘为第一距离的并排设置的接触焊盘，如图3b中所示。可替换地，导电层132可以被形成为这样的接触焊盘：所述接触焊盘以多行偏移，使得第一行接触焊盘被设置得离管芯的边缘为第一距离，并且与第一行交替的第二行接触焊盘被设置得离管芯的边缘为第二距离。
在图3c中，使用锯条或激光切割工具134将半导体晶片120经由划片街区126单体化成单个的半导体管芯124。
图4示出了晶片形衬底或插入机构140，所述衬底或插入机构包括基底142和从基底延伸的多行导电柱或引线144。在一个实施例中，衬底140是使用引线框架制造技术（例如冲压）制成的未被单体化的预先形成的或预先制作的层压衬底。衬底140包括在导电柱144之间的多个管芯开孔146，所述管芯开孔146具有足够的尺寸来通过该开孔安装半导体管芯。
图5示出了包括基底152和从所述基底延伸的多行导电柱或导电引线154的面板或带状衬底或插入机构150。在一个实施例中，衬底150是使用引线框架制造技术（例如冲压）制成的未被单体化的预先形成的或预先制作的层压衬底。衬底150包括在导电柱154之间的多个管芯开孔156，所述管芯开孔156具有足够的尺寸来通过该开孔安装半导体管芯。
图6a示出了包括基底162和从所述基底延伸的多行导电柱或导电引线164的已单体化的衬底或插入机构160。在一个实施例中，衬底160是使用引线框架制造技术（例如冲压）制成的预先形成的或预先制作的层压衬底。衬底140-160可以是金、银、镍、铂、铜、铜合金（包括镍、铁、锌、锡、铬、银、和磷中的一种或多种元素）、或者其它合适的导电材料。衬底160包括在导电柱164之间的开孔166，所述开孔具有足够的尺寸来通过该开孔安装半导体管芯。
图6b示出了具有基底162和从所述基底延伸的多行导电柱或引线164的衬底160的沿图6a的线6b-6b获取的截面图。图6c示出了为了加固和刚性增强在基底162中具有凹口168的衬底160的截面图。导电柱164可以是矩形、圆形、六边形、或者其它几何形状。在一个实施例中，基底162具有100-200微米（μm）的厚度，并且柱164具有80-300μm的高度，50-250μm的直径或截面宽度，和100-500μm的间距。导电柱164也可以具有锥形的形状，如图7a所示，其中较窄端在30-200μm的范围，较宽端在50-300μm的范围。图7b示出了具有较薄的中间部分的柱164。由于从基底162延伸的性质，导电柱164在各柱之间具有固定的间隔。衬底140和150的基底和柱具有和图6b-6c和图7a-7b相似的截面。
相对于图1和图2a-2c，图8a-8t示出了用具有基底和导电柱的衬底在嵌入式管芯封装中形成垂直互连结构的工艺。图8a示出了包括用于结构支撑的牺牲基底材料的载体或临时衬底170的俯视图，所述牺牲基底材料例如为硅、聚合物、氧化铍、玻璃、带子、或其它合适的低成本的刚性材料。载体170可以是晶片形状或矩形的。粘性层或带172被施加到载体170。图8b示出了载体170和粘性层172的截面图。
在图8c中，以导电柱144面向所述载体来将衬底140置于载体170上。图8d示出了沿着图8e的线8d-8d获取的被安装到载体170的衬底140，其中导电柱144被固定到粘性层172，图8e示出了安装到载体170的衬底140的俯视图。
在图8f中，利用例如拾取和放置操作以有源表面130面向载体来通过衬底140中的开孔146将来自图3c的半导体管芯124安装到载体170。半导体管芯124也可以通过衬底150中的开孔156，或通过衬底160中的开孔166被安装到载体170。图8g示出了被安装到在衬底140的开孔146内的载体170的粘性层172的半导体管芯124并且后表面128在衬底140上面延伸。图8h示出了替代实施例，其中半导体管芯124被安装到在衬底140的开孔146内的载体170的粘性层172并且后表面128被设置在衬底140的基底142下面。图8i示出了被安装到在衬底140的开孔146内的载体170的半导体管芯124的俯视图。
在图8j中，使用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或者其它合适的施加器将密封剂或模塑料174沉积到半导体管芯124、衬底140和载体170上面。密封剂174可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂174是不导电的并且在环境上保护半导体器件免受外部元件和污染物的影响。图8k示出了依照图8h的实施例密封剂174被沉积在半导体管芯124、衬底140、和载体170上。
在图8l中，载体170和粘性层172通过化学蚀刻、机械剥离、化学机械平坦化（CMP）、机械研磨、热烘焙、UV光、激光扫描、或湿法脱模被去除，以暴露半导体管芯124和导电柱144。
在图8m中，使用图案化和金属沉积工艺（例如溅射、电解电镀、和无电极电镀）将导电层或再分配层（RDL）180形成在半导体管芯124、导电柱144、和密封剂174上面。导电层180可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。导电层180的一部分被电连接到导电柱144。导电层180的另一部分被电连接到半导体管芯124的导电层132。导电层180的其它部分根据半导体管芯124的设计和功能可以共电或被电隔离。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层182形成在半导体管芯124、密封剂174、和导电层180上。绝缘层182包括一层或多层的二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、或其它具有相似绝缘和结构特性的材料。绝缘层182的一部分被去除以暴露导电层180。
使用图案化和金属沉积工艺，例如溅射、电解电镀、和无电极电镀，将导电层或RDL184形成在导电层180和绝缘层182上。导电层184可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。导电层184的一部分电连接到导电层180。导电层184的其它部分根据半导体管芯124的设计和功能可以共电或被电隔离。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层186形成在绝缘层182和导电层184上。绝缘层186包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或其它具有相似绝缘和结构特性的材料。绝缘层186的一部分被去除以暴露导电层184。
导电层180和184与绝缘层182和186的组合构成了被形成在半导体管芯124、导电柱144、和密封剂174上的装配互连结构188。导电层180和184以及绝缘层182和186可包括IPD，例如电容器、电感器、或电阻器。
在图8n中，将背衬带（backing tape）190施加到装配互连结构188用于背面研磨操作。在图8o中，衬底140的基底142以及半导体管芯124和密封剂174的一部分由研磨机192去除。图8p示出了在背面研磨操作后的组件，其中导电柱144在密封剂174内被电隔离。图8q示出了在背面研磨操作后的组件的俯视图，其中导电柱144在围绕半导体管芯124的密封剂174内被电隔离。
在图8r中，使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化将绝缘或钝化层196形成在半导体管芯124和密封剂174上。绝缘层196包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或其它具有相似绝缘和结构特性的材料。绝缘层196的一部分使用激光器198通过激光直接烧蚀被去除以暴露导电柱144。可替换地，绝缘层196的一部分通过图案化的光致抗蚀剂层使用蚀刻工艺被去除以暴露导电柱144。在从绝缘层196暴露的导电柱144上可施加可选的焊接材料或保护涂层199。
在图8s中，背衬带190被去除。使用蒸发、电解电镀、无电极电镀、球滴、或丝网印刷工艺将导电凸块材料沉积在导电层184上。凸块材料可以是具有可选的焊剂溶液的Al、Sn、Ni、Au、Ag、铅（Pb）、Bi、Cu、焊料，及其组合。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。使用合适的附着或结合工艺将凸块材料结合到导电层184。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球或凸块200。在一些应用中，凸块200被二次回流以改善与导电层184的电接触。在一个实施例中，凸块200形成在具有浸润层、阻挡层、和粘性层的UBM上。凸块也可以被压缩结合或热压缩结合到导电层184。凸块200代表了能被形成在导电层184上的一种互连结构。该互连结构也可使用结合线、导电膏、柱形凸块、微凸块、或者其它电互连。
在图8t中，使用锯条或激光切割工具202通过在导电柱144之间的密封剂174将半导体管芯124单体化成单个的嵌入式管芯封装204。图9示出了单体化后的嵌入式管芯封装204。半导体管芯124通过互连结构188电连接到导电柱144，所述导电柱144为嵌入式管芯提供垂直电互连。通过将衬底140-160放置在载体170上并且将半导体管芯124设置在衬底中的开孔内来将导电柱144形成在密封剂174中。衬底的基底被去除以电隔离所述导电柱。装配互连结构188形成在半导体管芯124和密封剂174上。
图10a-10b示出了以层叠封装（PoP）布置堆叠半导体封装的实施例。在图10a中，半导体封装210包括使用管芯附着粘合剂216被安装到衬底214的半导体管芯或部件212。衬底214包括导电迹线218。半导体管芯或部件220使用管芯附着粘合剂222被安装到半导体管芯212。多个结合线224被连接在形成在半导体管芯212和220的有源表面上的接触焊盘与衬底214的导电迹线218之间。密封剂226沉积在半导体管芯212和220、衬底214、和结合线224上。凸块228形成在衬底214的与半导体管芯212和220相对的导电迹线218上。
图10b示出了安装到来自图5的嵌入式管芯封装204的半导体封装210，其中凸块228被结合到导电柱144作为层叠封装（PoP）230。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行修改和改编。

Claims (15)

1.一种制作半导体器件的方法，包括：
提供包括基底和从基底延伸的多个导电柱的衬底，其中衬底的基底包括通过基底的开孔；
在衬底的导电柱位于衬底的基底与载体之间的情况下将衬底安装到所述载体上；
在将衬底安装到所述载体上之后，通过基底中的开孔设置半导体管芯；
在半导体管芯上和导电柱周围沉积密封剂；以及
除去基底以电隔离所述导电柱。
2.根据权利要求1的方法，还包括在半导体管芯、密封剂和导电柱上形成互连结构。
3.根据权利要求1的方法，还包括在半导体管芯、密封剂和导电柱上形成绝缘层。
4.根据权利要求1的方法，其中衬底的基底包括凹口。
5.一种制作半导体器件的方法，包括：
提供衬底，该衬底包括通过该衬底形成的开孔和从该衬底延伸的多个导电柱；
将所述衬底设置在载体上；
在将所述衬底设置在所述载体上后，通过衬底的开孔并且在导电柱之间设置半导体管芯；
在半导体管芯上和导电柱周围沉积密封剂；以及
在半导体管芯、密封剂和导电柱上形成互连结构。
6.根据权利要求5的方法，还包括在半导体管芯、密封剂和导电柱上形成绝缘层。
7.根据权利要求5的方法，其中半导体管芯的高度大于导电柱的高度。
8.根据权利要求5的方法，还包括除去衬底的一部分以电隔离导电柱。
9.根据权利要求5的方法，还包括将半导体封装设置在半导体管芯上并且电连接到导电柱。
10.一种半导体器件，包括：
衬底，包括基底和从该基底延伸的多个导电柱，其中通过所述基底形成开孔；
设置在开孔内并且在导电柱之间的半导体管芯，其中在俯视图中该半导体管芯在开孔内；
沉积在半导体管芯上并围绕导电柱的密封剂；和
形成在半导体管芯和导电柱上的互连结构。
11.根据权利要求10的半导体器件，进一步包括形成在半导体管芯、密封剂、和导电柱上的绝缘层。
12.根据权利要求10的半导体器件，其中导电柱包括圆形、矩形、锥形、或中间变窄的形状。
13.根据权利要求10的半导体器件，还包括在半导体管芯上形成的装配互连结构。
14.根据权利要求10的半导体器件，其中衬底还包括凹口。
15.根据权利要求10的半导体器件，其中以导电柱面向载体来将衬底设置在所述载体上。
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