SG10201800267XA - Semiconductor device and method of using substrate having base andconductive posts to form vertical interconnect structure inembedded die package - Google Patents
Semiconductor device and method of using substrate having base andconductive posts to form vertical interconnect structure inembedded die packageInfo
- Publication number
- SG10201800267XA SG10201800267XA SG10201800267XA SG10201800267XA SG10201800267XA SG 10201800267X A SG10201800267X A SG 10201800267XA SG 10201800267X A SG10201800267X A SG 10201800267XA SG 10201800267X A SG10201800267X A SG 10201800267XA SG 10201800267X A SG10201800267X A SG 10201800267XA
- Authority
- SG
- Singapore
- Prior art keywords
- inembedded
- andconductive
- posts
- substrate
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 title 1
Classifications
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- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Applications Claiming Priority (2)
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US201261702171P | 2012-09-17 | 2012-09-17 | |
US13/800,807 US9559039B2 (en) | 2012-09-17 | 2013-03-13 | Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die package |
Publications (1)
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SG10201800267XA true SG10201800267XA (en) | 2018-02-27 |
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SG10201601736QA SG10201601736QA (en) | 2012-09-17 | 2013-07-02 | Semiconductor device and method of using substrate having base andconductive posts to form vertical interconnect structure inembedded die package |
SG10201800267XA SG10201800267XA (en) | 2012-09-17 | 2013-07-02 | Semiconductor device and method of using substrate having base andconductive posts to form vertical interconnect structure inembedded die package |
SG2013051404A SG2013051404A (en) | 2012-09-17 | 2013-07-02 | Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die package |
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SG10201601736QA SG10201601736QA (en) | 2012-09-17 | 2013-07-02 | Semiconductor device and method of using substrate having base andconductive posts to form vertical interconnect structure inembedded die package |
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SG2013051404A SG2013051404A (en) | 2012-09-17 | 2013-07-02 | Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die package |
Country Status (4)
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US (2) | US9559039B2 (en) |
CN (1) | CN103681607B (en) |
SG (3) | SG10201601736QA (en) |
TW (1) | TWI623048B (en) |
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KR101195786B1 (en) | 2008-05-09 | 2012-11-05 | 고쿠리츠 다이가쿠 호진 큐슈 코교 다이가쿠 | Chip-size double side connection package and method for manufacturing the same |
US9312193B2 (en) | 2012-11-09 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress relief structures in package assemblies |
KR20140126598A (en) * | 2013-04-23 | 2014-10-31 | 삼성전자주식회사 | semiconductor package and method for manufacturing of the same |
JP2015076465A (en) * | 2013-10-08 | 2015-04-20 | イビデン株式会社 | Printed wiring board, printed wiring board manufacturing method, and package-on-package |
TWI550791B (en) * | 2014-01-16 | 2016-09-21 | 矽品精密工業股份有限公司 | Semiconductor package and manufacturing method thereof |
MY171261A (en) * | 2014-02-19 | 2019-10-07 | Carsem M Sdn Bhd | Stacked electronic packages |
TWI591762B (en) * | 2014-06-30 | 2017-07-11 | 恆勁科技股份有限公司 | Package apparatus and manufacturing method thereof |
KR101563909B1 (en) * | 2014-08-19 | 2015-10-28 | 앰코 테크놀로지 코리아 주식회사 | Method for manufacturing Package On Package |
CN104332456A (en) * | 2014-09-04 | 2015-02-04 | 华进半导体封装先导技术研发中心有限公司 | Wafer-level fan-out stacked packaging structure and manufacturing process thereof |
US10468381B2 (en) * | 2014-09-29 | 2019-11-05 | Apple Inc. | Wafer level integration of passive devices |
KR102384863B1 (en) * | 2015-09-09 | 2022-04-08 | 삼성전자주식회사 | Semiconductor chip package and method of manufacturing the same |
KR102487563B1 (en) * | 2015-12-31 | 2023-01-13 | 삼성전자주식회사 | Semiconductor package and methods for fabricating the same |
US10903166B2 (en) * | 2016-01-28 | 2021-01-26 | Intel IP Corporation | Integrated circuit packages |
US11272618B2 (en) | 2016-04-26 | 2022-03-08 | Analog Devices International Unlimited Company | Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits |
TWI567897B (en) * | 2016-06-02 | 2017-01-21 | 力成科技股份有限公司 | Thin fan-out stacked chip package and its manufacturing method |
US20180096974A1 (en) * | 2016-09-30 | 2018-04-05 | Nanya Technology Corporation | Semiconductor package and manufacturing method thereof |
US20180114786A1 (en) * | 2016-10-21 | 2018-04-26 | Powertech Technology Inc. | Method of forming package-on-package structure |
MY191544A (en) * | 2016-12-27 | 2022-06-30 | Intel Corp | Multi-conductor interconnect structure for a microelectronic device |
US10181447B2 (en) | 2017-04-21 | 2019-01-15 | Invensas Corporation | 3D-interconnect |
US10468339B2 (en) | 2018-01-19 | 2019-11-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Heterogeneous fan-out structure and method of manufacture |
US10497635B2 (en) | 2018-03-27 | 2019-12-03 | Linear Technology Holding Llc | Stacked circuit package with molded base having laser drilled openings for upper package |
SG10201802515PA (en) | 2018-03-27 | 2019-10-30 | Delta Electronics Int’L Singapore Pte Ltd | Packaging process |
US11735570B2 (en) * | 2018-04-04 | 2023-08-22 | Intel Corporation | Fan out packaging pop mechanical attach method |
US10879119B2 (en) * | 2018-09-28 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating a semiconductor device |
US11410977B2 (en) | 2018-11-13 | 2022-08-09 | Analog Devices International Unlimited Company | Electronic module for high power applications |
CN111063674A (en) * | 2019-12-06 | 2020-04-24 | 中国电子科技集团公司第三十八研究所 | PoP three-dimensional packaging-oriented vertical interconnection structure and manufacturing method |
US11844178B2 (en) | 2020-06-02 | 2023-12-12 | Analog Devices International Unlimited Company | Electronic component |
US12040284B2 (en) | 2021-11-12 | 2024-07-16 | Invensas Llc | 3D-interconnect with electromagnetic interference (“EMI”) shield and/or antenna |
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US6010769A (en) * | 1995-11-17 | 2000-01-04 | Kabushiki Kaisha Toshiba | Multilayer wiring board and method for forming the same |
DE10320646A1 (en) * | 2003-05-07 | 2004-09-16 | Infineon Technologies Ag | Electronic component, typically integrated circuit, system support and manufacturing method, with support containing component positions in lines and columns, starting with coating auxiliary support with photosensitive layer |
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US7842542B2 (en) | 2008-07-14 | 2010-11-30 | Stats Chippac, Ltd. | Embedded semiconductor die package and method of making the same using metal frame carrier |
US7838337B2 (en) * | 2008-12-01 | 2010-11-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming an interposer package with through silicon vias |
US7993941B2 (en) | 2008-12-05 | 2011-08-09 | Stats Chippac, Ltd. | Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant |
US8354304B2 (en) | 2008-12-05 | 2013-01-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant |
US7955942B2 (en) * | 2009-05-18 | 2011-06-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming a 3D inductor from prefabricated pillar frame |
US8169058B2 (en) * | 2009-08-21 | 2012-05-01 | Stats Chippac, Ltd. | Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars |
US8383457B2 (en) * | 2010-09-03 | 2013-02-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
US8105872B2 (en) * | 2010-06-02 | 2012-01-31 | Stats Chippac, Ltd. | Semiconductor device and method of forming prefabricated EMI shielding frame with cavities containing penetrable material over semiconductor die |
JP5479247B2 (en) * | 2010-07-06 | 2014-04-23 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US8097490B1 (en) * | 2010-08-27 | 2012-01-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die |
US8354297B2 (en) * | 2010-09-03 | 2013-01-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die |
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2013
- 2013-03-13 US US13/800,807 patent/US9559039B2/en active Active
- 2013-04-23 CN CN201310142037.3A patent/CN103681607B/en active Active
- 2013-07-02 SG SG10201601736QA patent/SG10201601736QA/en unknown
- 2013-07-02 SG SG10201800267XA patent/SG10201800267XA/en unknown
- 2013-07-02 SG SG2013051404A patent/SG2013051404A/en unknown
- 2013-07-18 TW TW102125704A patent/TWI623048B/en active
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2016
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US9559039B2 (en) | 2017-01-31 |
SG2013051404A (en) | 2014-04-28 |
CN103681607A (en) | 2014-03-26 |
SG10201601736QA (en) | 2016-04-28 |
US10242948B2 (en) | 2019-03-26 |
TW201413845A (en) | 2014-04-01 |
CN103681607B (en) | 2019-01-18 |
TWI623048B (en) | 2018-05-01 |
US20140077389A1 (en) | 2014-03-20 |
US20170098610A1 (en) | 2017-04-06 |
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