TWI591762B - 封裝裝置及其製作方法 - Google Patents

封裝裝置及其製作方法 Download PDF

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Publication number
TWI591762B
TWI591762B TW103122515A TW103122515A TWI591762B TW I591762 B TWI591762 B TW I591762B TW 103122515 A TW103122515 A TW 103122515A TW 103122515 A TW103122515 A TW 103122515A TW I591762 B TWI591762 B TW I591762B
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Taiwan
Prior art keywords
layer
conductive pillar
mold compound
wire
component
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TW103122515A
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English (en)
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TW201601247A (zh
Inventor
胡竹青
許詩濱
周鄂東
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恆勁科技股份有限公司
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Priority to TW103122515A priority Critical patent/TWI591762B/zh
Priority to CN201410322921.XA priority patent/CN105321926A/zh
Priority to US14/492,716 priority patent/US20150382469A1/en
Publication of TW201601247A publication Critical patent/TW201601247A/zh
Application granted granted Critical
Publication of TWI591762B publication Critical patent/TWI591762B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
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    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections

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Description

封裝裝置及其製作方法
本發明是有關於一種封裝裝置及其製作方法，特別是有關於一種半導體封裝裝置及其製作方法。
在新一代的電子產品中，不斷追求更輕薄短小，更要求產品具有多功能與高性能，因此，積體電路(Integrated Circuit,IC)必須在有限的區域中容納更多電子元件以達到高密度與微型化之要求，為此電子產業開發新型構裝技術，將電子元件埋入基板中，大幅縮小構裝體積，也縮短電子元件與基板的連接路徑，另外還可利用增層技術(Build-Up)增加佈線面積，以符合輕薄短小及多功能的潮流趨勢。
圖1為傳統之玻璃纖維基板封裝結構。玻璃纖維基板封裝結構10包括有玻璃纖維基板100，例如可為玻纖環氧樹脂銅箔基板(Bismaleimide Triazine,BT)之FR-4型號或FR-5型號，其中玻璃纖維基板100係經由機械鑚孔或雷射鑚孔(Laser Via)而形成複數個圓形導通孔110，圓形導電柱層(circular conductive pillar layer)120設置在圓形導通孔110中，第一導電層132、134分別設置在玻璃纖維基板100上且與圓形導電柱層120電性導通，絕緣層140覆蓋在玻璃纖維基板100上，並再經由機械鑚孔或雷射 鑽孔而形成複數個圓形導通孔110，第二導電層152、154設置在絕緣層150上且經由圓形導電柱層120與第一導電層132、134電性導通。
上述傳統之玻璃纖維基板封裝結構10，其應用機械鑚孔或雷射鑚孔之物理機制僅能形成具圓形導通孔之圓形導電柱層120，然而圓形導電柱層120具有較大之截面積，對於製作高密度佈線之基板將造成一定的限制，使得基板之成本過於昂貴而不具備產業優勢的競爭。
本發明提出一種封裝裝置，其係可使用鑄模化合物層(Molding Compound Layer)為無核心基板(Coreless Substrate)之主體材料，並利用電鍍非圓形導電柱層(Non-circular conductive pillar layer)形成導通孔與預封包互連系統(Molded Interconnection System,MIS)封裝方式於基板製作中順勢將內接元件埋入於基板之內，形成高密度佈線面積之疊層結構。
本發明提出一種封裝裝置之製作方法，其係可使用較低成本的封膠(Molding Compound)搭配電鍍非圓形導電柱層的導通孔方法，以取代藉由對玻璃纖維基板機械鑚孔或雷射鑚孔的導通孔方法，其可提高佈線面積，進而提升生產效能。
在一實施例中，本發明提出一種封裝裝置，其包括一第一導線層、一第一導電柱層、一第一鑄模化合物層、一第二導線層以及一防焊層。第一導線層具有相對之一第一表面與一第二表面。第一導電柱層設置於第一導線層之第二表面上，其中第一導電柱層係為一非圓形導電柱層。第一鑄模化合物層設置於第一導線層與第一導電柱層之部分區域內。第二導線層設置於第一鑄模化合 物層與第一導電柱層之一端上。防焊層設置於第一鑄模化合物層與第二導線層上。
在另一實施例中，本發明提出一種封裝裝置之製作方法，其步驟包括：提供一金屬承載板，其具有相對之一第一表面與一第二表面；形成一第一導線層於金屬承載板之第二表面上；形成一第一導電柱層於第一導線層上，其中第一導電柱層係為一非圓形導電柱層；形成一第一鑄模化合物層包覆第一導線層與第一導電柱層並位於金屬承載板之第二表面上，其中第一導線層與第一導電柱層嵌設於第一鑄模化合物層內；露出第一導電柱層之一端；形成一第二導線層於第一鑄模化合物層與露出之第一導電柱層之一端上；形成一防焊層於該第一鑄模化合物層與第二導線層上；移除金屬承載板之部分區域以形成一窗口，其中第一導線層與第一鑄模化合物層從窗口露出。
10‧‧‧玻璃纖維基板封裝結構
100‧‧‧玻璃纖維基板
110‧‧‧圓形導通孔
120‧‧‧圓形導電柱層
120A‧‧‧圓形導電柱層
120B1‧‧‧圓形導電柱層
120B2‧‧‧圓形導電柱層
132、134‧‧‧第一導電層
140‧‧‧絕緣層
152、154‧‧‧第二導電層
20‧‧‧封裝裝置
200‧‧‧第一導線層
202‧‧‧第一表面
204‧‧‧第二表面
210‧‧‧金屬層
220‧‧‧第一導電柱層
220A‧‧‧矩形導電柱層
220B1‧‧‧矩形導電柱層
220B2‧‧‧矩形導電柱層
220B3‧‧‧矩形導電柱層
220B4‧‧‧矩形導電柱層
222‧‧‧凹型結構
224‧‧‧部分區域
226‧‧‧第一導電柱層之一端
230‧‧‧內接元件
240‧‧‧第一鑄模化合物層
250‧‧‧第二導線層
260‧‧‧防焊層
270‧‧‧外接元件
280‧‧‧第二鑄模化合物層
290‧‧‧金屬球
30‧‧‧製作方法
步驟S302-步驟S334
300‧‧‧金屬承載板
302‧‧‧第一表面
304‧‧‧第二表面
306‧‧‧窗口
310‧‧‧第一光阻層
320‧‧‧第二光阻層
330‧‧‧第三光阻層
410‧‧‧圓形導電層
420‧‧‧矩形導電層
C‧‧‧切割製程
D~K‧‧‧間距
W1~W4‧‧‧寬邊
圖1為傳統之玻璃纖維基板封裝結構。
圖2為本發明較佳實施例之封裝裝置示意圖。
圖3為圓形導電柱層與矩形導電柱層上視圖。
圖4為傳統之圓形導電柱層上視圖。
圖5為本發明第一實施例之矩形導電柱層上視圖。
圖6為本發明第二實施例之矩形導電柱層上視圖。
圖7為本發明第三實施例之矩形導電柱層上視圖。
圖8為本發明較佳實施例之封裝裝置製作方法流程圖。
圖9A至圖9Q為本發明較佳實施例之封裝裝置製作示意圖。
圖2為本發明較佳實施例之封裝裝置示意圖。封裝裝置20，其包括一第一導線層200、一金屬層210、一第一導電柱層220、一內接元件230、一第一鑄模化合物層240、一第二導線層250以及一防焊層260，但不以此為限。
第一導線層200具有相對之一第一表面202與一第二表面204。在本實施例中，第一導線層200係應用電鍍(Electrolytic Plating)技術所形成，但並不以此為限。其中第一導線層200可以為圖案化導線層，其包括至少一走線或至少一晶片座，第一導線層200之材質可以為金屬，例如是銅。。金屬層210設置於第一導線層200之第一表面202上。
第一導電柱層220設置於第一導線層200之第二表面204上，並且與第一導線層200形成一凹型結構222，其中第一導電柱層220係為一非圓形導電柱層(non-circular conductive pillar layer)。在一實施例中，第一導電柱層220可為一矩形導電柱層(rectangular conductive pillar layer)、一八角形導電柱層(octagonal conductive pillar layer)、一橢圓形導電柱層(oval conductive pillar layer)或任意形狀之非圓形導電柱層，此外，第一導電柱層220亦可以為圖案化導線層，例如一走線或一晶片座，但皆不以此為限。內接元件230設置並電性連結於凹型結構222內之第一導線層200之第二表面204上。在一實施例中，內接元件230係為一主動元件、一被動元件或一半導體晶片，但並不以此為限。
第一鑄模化合物層240設置於第一導線層200與第一導電柱層220之部分區域224內，其中內接元件230嵌設於第一鑄模化合物層240內，在本實施例中，第一鑄模化合物層240不露出於 第一導線層200之第一表面202與第一導電柱層220之一端226，第一鑄模化合物層240設置於第一導線層200與第一導電柱層220之全部區域內，但並不以此為限。此外，第一鑄模化合物層240係具有酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)、矽基樹脂(Silicone-Based Resin)或其他適當之鑄模化合物，但並不以此為限。第二導線層250設置於第一鑄模化合物層240與第一導電柱層220之一端226上，此外，第二導線層250可以為圖案化導線層，例如一走線或一晶片座。防焊層260設置於第一鑄模化合物層240與第二導線層250上。
其中，封裝裝置20更可包括一外接元件270、一第二鑄模化合物層280及複數個金屬球290。外接元件270設置並電性連結於第一導線層200之第一表面202上。第二鑄模化合物層280設置於外接元件270與第一導線層200之第一表面202上，其中外接元件270嵌設於第二鑄模化合物層280內。複數個金屬球290設置於第二導線層250上。在一實施例中，外接元件270係為一主動元件、一被動元件、一半導體晶片或一軟性電路板，但並不以此為限。
在此要特別說明，本發明即是利用具有與傳統圓形導電柱層相同電阻(Resistance,R)之非圓形導電柱層來做取代，根據電阻公式為電阻，其中ρ為電阻係數(resistivity)、L為電阻長度、A為電阻截面積，故只要圓形導電柱層與非圓形導電柱層之電阻係數ρ、電阻長度L與電阻截面積A皆相同，則圓形導電柱層與非圓形導電柱層之電阻亦相同，即非圓形導電柱層可以維持原來相同電阻之電學特性。例如圖3為圓形導電柱層與矩形導電柱層上視圖，其中圓形導電柱層120A之直徑R1=10μm，故其圓形截面積，而矩形導電柱層220A之長 邊L1=15μm與寬邊W1=6μm，故其矩形截面積A2=L1*W1=80pm2，由此可知，本發明可以調整矩形導電柱層220A之寬邊W1明顯小於圓形導電柱層120A之直徑R1，亦即使用矩形之導通孔並維持與圓形導通孔相同截面積下，可有效縮短導通孔到導通孔的中心距離或增加導通孔到導通孔之間的走線數量，達到更高密度佈線設計的方法，或讓相同走線數量的線寬更寬，進而提升生產能力。
舉例而言，圖4為傳統之圓形導電柱層上視圖，其中兩組相同截面積之圓形導電柱層120B1、120B2的直徑R2皆為80μm，並且分別電性連結於圓形導電層410，其中圓形導電層410的直徑R3皆為110μm，在一實施例中，圓形導電層410類似於第二導線層250之走線或晶片座，或是外接元件270之接觸電極，但不以此為限。其中圓形導電層410的點X1與另一圓形導電層410的點X3之間具有間距D=170μm，而圓形導電層410的點X2與另一圓形導電層410的點X3之間具有間距E=60μm，圓形導電柱層120B1、120B2的直徑R2大於間距E，故無法在兩組圓形導電層410之間再增加任何圓形導電柱層。
圖5本發明第一實施例之矩形導電柱層上視圖。請同時比較上述圖4，其係將具有與圓形導電柱層120B1、120B2相同截面積之矩形導電柱層220B1、220B2來做取代，其中兩組相同截面積之矩形導電柱層220B1、220B2的寬邊W2皆為40μm，並且分別電性連結於矩形導電層420，其中矩形導電層420的寬邊W3皆為70μm，在一實施例中，矩形導電層420類似於第二導線層250之走線或晶片座，或是外接元件270之接觸電極，但不以此為限。其中矩形導電層420的點Y1與另一矩形導電層420的點Y3之間具有間距F=170μm，而矩形導電層420的點Y2與另一矩形導電層420的點Y3之間具有間距G=100μm，故可在兩組矩 形導電柱層220B1、220B2之間再新增兩組寬邊W4=20μm之矩形導電柱層220B3，其中矩形導電柱層220B3之間具有間距20μm，矩形導電柱層220B3與兩組矩形導電層420之間也具有間距20μm，上述之間距20μm即為走線或晶片座的封裝容忍度，故相較於圖4之結構，本實施例之設計可增加導通孔到導通孔之間的走線數量，達到更高密度佈線設計的方法。
圖6為本發明第二實施例之矩形導電柱層上視圖。請同時比較上述圖4至圖5，其類似於上述圖4之結構，本實施例係將圖4結構中之兩組矩形導電柱層220B3替換為一組W4=20μm之矩形導電柱層220B3，其中矩形導電層420的點Y1與另一矩形導電層420的點Y3之間具有間距H=130μm，而矩形導電層420的點Y2與另一矩形導電層420的點Y3之間具有間距I=60μm，矩形導電柱層220B3與兩組矩形導電層420之間具有間距20μm，上述之間距20μm即為走線或晶片座的封裝容忍度，故相較於圖4之結構，本實施例之設計可有效縮短導通孔到導通孔的中心距離，達到更高密度佈線設計的方法。
圖7為本發明第三實施例之矩形導電柱層上視圖。請同時比較上述圖4至圖5，其類似於上述圖4之結構，本實施例係將圖4結構中之兩組矩形導電柱層220B3替換為一組寬邊W5=30μm之矩形導電柱層220B4，其中矩形導電層420的點Y1與另一矩形導電層420的點Y3之間具有間距J=170μm，而矩形導電層420的點Y2與另一矩形導電層420的點Y3之間具有間距K=100μm，矩形導電柱層220B4與兩組矩形導電層420之間具有間距35μm，上述之間距35μm即為走線或晶片座的封裝容忍度，故相較於圖4之結構，本實施例之設計可讓相同走線數量的線寬更寬，進而提升生產能力。
圖8為本發明較佳實施例之封裝裝置製作方法流程圖，圖9A 至圖9Q為本發明較佳實施例之封裝裝置製作示意圖。封裝裝置20之製作方法30，其步驟包括：
步驟S302，如圖9A所示，提供一金屬承載板300，其具有相對之一第一表面302與一第二表面304。
步驟S304，如圖9B所示，形成一第一光阻層310於金屬承載板300之第二表面304上與一第二光阻層320於金屬承載板300之第一表面302上。在本實施例中，第一光阻層310係應用微影製程(Photolithography)技術所形成，但並不以此為限。
步驟S306，如圖9C所示，形成一第一導線層200於金屬承載板300之第二表面304上。在本實施例中，第一導線層200係應用電鍍(Electrolytic Plating)技術所形成，但並不以此為限。其中第一導線層200可以為圖案化導線層，其包括至少一走線或至少一晶片座，第一導線層200之材質可以為金屬，例如是銅。
步驟S308，如圖9D所示，形成一第三光阻層330於第一光阻層310與第一導線層200上。在本實施例中，第三光阻層330係應用壓合乾膜光阻製程所形成，但並不以此為限。
步驟S310，如圖9E所示，移除第三光阻層330之部分區域以露出第一導線層200。在本實施例中，移除第三光阻層330之部分區域係應用微影製程(Photolithography)技術所達成，但並不以此為限。
步驟S312，如圖9F所示，形成一第一導電柱層220於第一導線層200上。其中第一導電柱層220係為一非圓形導電柱層。在一實施例中，第一導電柱層220可為一矩形導電柱層、一八角形導電柱層、一橢圓形導電柱層或任意形狀之非圓形導電柱層，但不以此為限。在本實施例中，第一導電柱層220係應用電鍍(Electrolytic Plating)技術所形成，但並不以此為限。其中，第一導電柱層220包括至少一導電柱，其形成對應於第一導線層200 之走線與晶片座上，第一導電柱層220之材質可以為金屬，例如是銅。
步驟S314，如圖9G所示，移除第一光阻層310、第二光阻層320與第三光阻層330，其中第一導電柱層220與第一導線層200形成一凹型結構222。
步驟S316，如圖9H所示，提供一內接元件230設置並電性連結於凹型結構222內之第一導線層200上。
步驟S318，如圖9I所示，形成一第一鑄模化合物層240包覆第一導線層200與第一導電柱層220並位於金屬承載板300之第二表面304上，其中內接元件230、第一導線層200與第一導電柱層220嵌設於第一鑄模化合物層240內。在本實施例中，第一鑄模化合物層240係應用轉注鑄模(Transfer Molding)之封裝技術所形成，第一鑄模化合物層240之材質可包括酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)、矽基樹脂(Silicone-Based Resin)或其他適當之鑄模化合物，在高溫和高壓下，以液體狀態包覆內接元件230、第一導線層200與第一導電柱層220，其固化後形成第一鑄模化合物層240。第一鑄模化合物層240亦可包括適當之填充劑，例如是粉狀之二氧化矽。
在另一實施例中，亦可應用注射鑄模(Injection Molding)或壓縮鑄模(Compression Molding)之封裝技術形成第一鑄模化合物層240。
其中，形成第一鑄模化合物層240之步驟可包括：提供一鑄模化合物，其中鑄模化合物具有樹脂及粉狀之二氧化矽。加熱鑄模化合物至液體狀態。注入呈液態之鑄模化合物於金屬承載板300之第二表面304上，鑄模化合物在高溫和高壓下包覆內接元件230、第一導線層200與第一導電柱層220。固化鑄模化合物，使鑄模化合物形成第一鑄模化合物層240，但形成第一鑄模化合 物層240之步驟並不以此為限。
步驟S320，如圖9J所示，露出第一導電柱層220之一端226。在本實施例中，露出第一導電柱層220係應用磨削(Grinding)方式移除第一鑄模化合物層240之一部分，以露出第一導電柱層220之一端226。較佳但非限定地，第一導電柱層220之一端226與第一鑄模化合物層240實質上對齊，例如是共面。在另一實施例中，可在形成第一鑄模化合物層240的同時，露出第一導電柱層220之一端226，而無需移除第一鑄模化合物層240的任何部分。
步驟S322，如圖9K所示，形成一第二導線層250於第一鑄模化合物層240與露出之第一導電柱層220之一端226上。在一實施例中，第二導線層250係可應用無電鍍(Electroless Plating)技術、濺鍍(Sputtering Coating)技術或蒸鍍(Thermal Coating)技術所形成，但並不以此為限。其中第二導線層250可以為圖案化導線層，其包括至少一走線或至少一晶片座，並形成對應於露出之第一導電柱層220之一端226上，第二導線層250之材質可以為金屬，例如是銅。
步驟S324，如圖9L所示，形成一防焊層260於第一鑄模化合物層240與第二導線層250上，並露出部份之第二導線層250。其中，防焊層260具有絕緣第二導線層250之各走線電性的功效。
步驟S326，如圖9M所示，移除金屬承載板300之部分區域以形成一窗口306，其中第一導線層200與第一鑄模化合物層240從窗口306露出。在本實施例中，移除金屬承載板300之部分區域係應用微影製程(Photolithography)與蝕刻製程(Etch Process)所達成，第一導線層200之走線與晶片座亦可從窗口306露出，此外，金屬承載板300所留下之部分區域即形成一金屬層210。
步驟S328，如圖9N所示，提供一外接元件270設置並電性 連結於第一導線層200之第一表面202上。在一實施例中，外接元件270係為一主動元件、一被動元件、一半導體晶片或一軟性電路板，但並不以此為限。
步驟S330，如圖9O所示，形成一第二鑄模化合物層280包覆外接元件270並位於第一導線層200之第一表面202與第一鑄模化合物層240上，其中外接元件270嵌設於第二鑄模化合物層280內。在本實施例中，第二鑄模化合物層280係應用轉注鑄模(Transfer Molding)之封裝技術所形成，第二鑄模化合物層280之材質可包括酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)、矽基樹脂(Silicone-Based Resin)或其他適當之鑄模化合物，在高溫和高壓下，以液體狀態包覆外接元件270並位於第一導線層200之第一表面202與第一鑄模化合物層240上，其固化後形成第二鑄模化合物層280。第二鑄模化合物層280亦可包括適當之填充劑，例如是粉狀之二氧化矽。
在另一實施例中，亦可應用注射鑄模(Injection Molding)或壓縮鑄模(Compression Molding)之封裝技術形成第二鑄模化合物層280。
步驟S332，如圖9P所示，形成複數個金屬球290於第二導線層250上。每一金屬球290之材質可以為任何金屬，例如是銅。
步驟S334，如圖9Q所示，最後再進行切割製程C於第一導線層200、金屬層210、第一導電柱層220、第一鑄模化合物層240、第二導線層250或防焊層260等至少其中一層而形成如圖2所示之封裝裝置20。
綜上所述，本發明之封裝裝置，其係利用非圓形導通孔並維持與圓形導通孔相同截面積下，可有效縮短導通孔到導通孔的中心距離或增加導通孔到導通孔之間的走線數量，達到更高密度佈線設計的方法，或讓相同走線數量的線寬更寬，進而提升生產能 力。
惟以上所述之具體實施例，僅係用於例釋本發明之特點及功效，而非用於限定本發明之可實施範疇，於未脫離本發明上揭之精神與技術範疇下，任何運用本發明所揭示內容而完成之等效改變及修飾，均仍應為下述之申請專利範圍所涵蓋。
220B1‧‧‧矩形導電柱層
220B2‧‧‧矩形導電柱層
220B3‧‧‧矩形導電柱層
420‧‧‧矩形導電層
F、G‧‧‧間距
W2~W4‧‧‧寬邊

Claims (19)

  1. 一種封裝裝置，其包括：一第一導線層，其具有相對之一第一表面與一第二表面；一第一導電柱層，其設置於該第一導線層之該第二表面上，其中該第一導電柱層係為一非圓形導電柱層；一第一鑄模化合物層，其設置於該第一導線層與該第一導電柱層之部分區域內；一第二導線層，其設置於該第一鑄模化合物層與該第一導電柱層之一端上；一外接元件，其設置並電性連結於該第一導線層之該第一表面上；一第二鑄模化合物層，其設置於該外接元件與該第一導線層之該第一表面上，其中該外接元件嵌設於該第二鑄模化合物層內；及複數個金屬球，其設置於該第二導線層上；以及一防焊層，其設置於該第一鑄模化合物層與該第二導線層上。
  2. 如申請專利範圍第1項所述之封裝裝置，其更包括一金屬層，其中該金屬層設置於該第一導線層之該第一表面上。
  3. 如申請專利範圍第1項所述之封裝裝置，其中該第一導電柱層與該第一導線層形成一凹型結構。
  4. 如申請專利範圍第3項所述之封裝裝置，其更包括一內接元件，其中該內接元件設置並電性連結於該凹型結構內之該第一導 線層之該第二表面上，並且嵌設於該第一鑄模化合物層內。
  5. 如申請專利範圍第4項所述之封裝裝置，其中該內接元件係為一主動元件、一被動元件或一半導體晶片。
  6. 如申請專利範圍第1項所述之封裝裝置，其中該第一鑄模化合物層不露出於該第一導線層之該第一表面與該第一導電柱層之一端。
  7. 如申請專利範圍第1項所述之封裝裝置，其中該外接元件係為一主動元件、一被動元件、一半導體晶片或一軟性電路板。
  8. 如申請專利範圍第1項所述之封裝裝置，其中該第一鑄模化合物層係具有酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)、矽基樹脂(Silicone-Based Resin)或其他適當之鑄模化合物。
  9. 如申請專利範圍第1項所述之封裝裝置，其中該非圓形導電柱層係為一矩形導電柱層、一八角形導電柱層、一橢圓形導電柱層或任意形狀之非圓形導電柱層。
  10. 一種封裝裝置之製作方法，其步驟包括：提供一金屬承載板，其具有相對之一第一表面與一第二表面；形成一第一導線層於該金屬承載板之該第二表面上；形成一第一導電柱層於該第一導線層上，其中該第一導電柱層係為一非圓形導電柱層；形成一第一鑄模化合物層包覆該第一導線層與該第一導電柱層並位於該金屬承載板之該第二表面上，其中該第一導線 層與該第一導電柱層嵌設於該第一鑄模化合物層內；露出該第一導電柱層之一端；形成一第二導線層於該第一鑄模化合物層與露出之該第一導電柱層之一端上；形成一防焊層於該第一鑄模化合物層與該第二導線層上；以及移除該金屬承載板之部分區域以形成一窗口，其中該第一導線層與該第一鑄模化合物層從該窗口露出。
  11. 如申請專利範圍第10項所述之製作方法，其中該第一導電柱層與該第一導線層形成一凹型結構。
  12. 如申請專利範圍第11項所述之製作方法，其更包括提供一內接元件，其中該內接元件設置並電性連結於該凹型結構內之該第一導線層上，並且嵌設於該第一鑄模化合物層內。
  13. 如申請專利範圍第12項所述之製作方法，其中該內接元件係為一主動元件、一被動元件或一半導體晶片。
  14. 如申請專利範圍第10項所述之製作方法，其更包括：提供一外接元件設置並電性連結於該第一導線層之一第一表面上；形成一第二鑄模化合物層包覆該外接元件並位於該第一導線層之該第一表面與該第一鑄模化合物層上，其中該外接元件嵌設於該第二鑄模化合物層內；及形成複數個金屬球於該第二導線層上。
  15. 如申請專利範圍第10項所述之製作方法，其中形成該第一導電柱層於該第一導線層上之前之步驟包括：形成一第一光阻層於該金屬承載板之該第二表面上與一第二光阻層於該金屬承載板之該第一表面上；形成該第一導線層於該金屬承載板之該第二表面上；形成一第三光阻層於該第一光阻層與該第一導線層上；移除該第三光阻層之部分區域以露出該第一導線層；形成該第一導電柱層於該第一導線層上；及移除該第一光阻層、該第二光阻層與該第三光阻層。
  16. 如申請專利範圍第12項所述之製作方法，其中形成該第一鑄模化合物層之步驟包括：提供一鑄模化合物，其中該鑄模化合物具有樹脂及粉狀之二氧化矽；加熱該鑄模化合物至液體狀態；注入呈液態之該鑄模化合物於該金屬承載板之該第二表面上，該鑄模化合物在高溫和高壓下包覆該內接元件、該第一導線層與該第一導電柱層；及固化該鑄模化合物，使該鑄模化合物形成該第一鑄模化合物層。
  17. 如申請專利範圍第14項所述之製作方法，其中該外接元件係為一主動元件、一被動元件、一半導體晶片或一軟性電路板。
  18. 如申請專利範圍第10項所述之製作方法，其中該第一鑄模化合 物層係具有有酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)、矽基樹脂(Silicone-Based Resin)或其他適當之鑄模化合物。
  19. 如申請專利範圍第10項所述之製作方法，其中該非圓形導電柱層係為一矩形導電柱層、一八角形導電柱層、一橢圓形導電柱層或任意形狀之非圓形導電柱層。
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