TWI543327B - 半導體承載元件 - Google Patents

半導體承載元件 Download PDF

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Publication number
TWI543327B
TWI543327B TW102144935A TW102144935A TWI543327B TW I543327 B TWI543327 B TW I543327B TW 102144935 A TW102144935 A TW 102144935A TW 102144935 A TW102144935 A TW 102144935A TW I543327 B TWI543327 B TW I543327B
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Taiwan
Prior art keywords
layer
semiconductor
dielectric layer
carrier component
electrical
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TW102144935A
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English (en)
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TW201419486A (zh
Inventor
周輝星
林建福
菲索 歐
林少雄
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先進封裝技術私人有限公司
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Publication of TW201419486A publication Critical patent/TW201419486A/zh
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Publication of TWI543327B publication Critical patent/TWI543327B/zh

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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Description

半導體承載元件
本發明是有關於一種半導體承載元件，且特別是有關於一種導電層埋設於介電層的半導體承載元件。
傳統的半導體結構包括基板、晶片及銲線。基板例如是塑膠或陶瓷基板，其用以承載晶片。基板具有相對之第一面與第二面且包括接墊及導通貫孔。晶片設於基板之第一面上，銲線連接晶片與位於基板之第一面上之接墊。基板之接墊係透過導通貫孔電性連接於基板之第二面。
然而，由於導通貫孔係貫穿基板，因此降低基板的結構強度。且，由於導通貫孔降低基板的結構強度，為了不使基板的結構強度過低，導通貫孔相距基板之外側面一較大距離，藉以提升基板的結構強度至一正常範圍，但如此將導致半導體封裝件的尺寸無法縮小。此外，基板的厚度一般也較厚，使半導體封裝件的厚度無法縮小。
本發明係有關於一種半導體承載元件，半導體承載元件之介電層包覆導柱層，導柱層係電性連接半導體承載元件之 相對二側，由於介電層的厚度較薄，可有效縮小半導體封裝件的尺寸。
根據本發明之一實施例，提出一種半導體承載元件。半導體承載元件包括一介電層、一導線層、一導柱層及一電鍍導電層。介電層具有相對之一第一表面與一第二表面。導線層係埋設於介電層中，且暴露於介電層之第二表面。導柱層係埋設於介電層中，且暴露於介電層之第一表面，並與導線層電性相連。電鍍導電層設置在介電層之第一表面及暴露出的導柱層上。
根據本發明之另一實施例，提出一種半導體承載元件。半導體承載元件包括一介電層、複數個走線、複數個電性接墊及複數個導電柱。介電層具有相對之一第一表面與一第二表面。走線係埋設於介電層中，且暴露於介電層之第二表面。電性接墊設置於介電層之第一表面上。導電柱係埋設於介電層中，且暴露於介電層之第一表面，其中，導電柱與走線及電性接墊電性相連。
根據本發明之另一實施例，提出一種半導體封裝件。半導體封裝件包括一介電層、複數個走線、複數個電性接墊、複數個導電柱及至少一半導體元件。介電層具有相對之一第一表面與一第二表面。走線係埋設於介電層中，且暴露於介電層之第二表面。電性接墊設置在介電層之第一表面上。導電柱係埋設於介電層中，且暴露於介電層之第一表面，其中，導電柱與走線及電性接墊電性相連。半導體元件設置在介電層之第二表面上，並 電性連接走線。
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：
100‧‧‧半導體封裝件
102‧‧‧電性載板
102a‧‧‧第一面
102b‧‧‧第二面
102c‧‧‧側面
104、304‧‧‧導線層
104a‧‧‧導線表面
106、306‧‧‧走線
106a‧‧‧走線表面
108、308‧‧‧晶片座
108a‧‧‧晶片座表面
110‧‧‧導電柱
110a‧‧‧一端
110b‧‧‧端面
112‧‧‧第一封裝體
112a‧‧‧第一封裝表面
112b‧‧‧封裝側面
112c‧‧‧第二封裝表面
114‧‧‧電鍍導電層
114a‧‧‧餘留部
116‧‧‧缺口
118a‧‧‧第一表面處理層
118b‧‧‧第二表面處理層
120、220、320‧‧‧半導體承載元件
132‧‧‧電性接點
134、334‧‧‧電鍍固環
122、130‧‧‧半導體元件
122a‧‧‧主動表面
124‧‧‧銲線
126‧‧‧第二封裝體
128‧‧‧黏膠
S102-S126‧‧‧步驟
第1圖繪示依照本發明一實施例之半導體封裝件的製造方法流程圖。
第2A至2M圖繪示依照本發明一實施例之半導體封裝件的製造示意圖。
第3A至3B圖繪示依照本發明另一實施例之半導體承載元件之製造過程圖。
第4圖繪示第2J圖中半導體承載元件之上視圖。
第5A圖繪示依照本發明另一實施例之半導體承載元件之剖視圖。
第5B圖繪示第5A圖中半導體承載元件之上視圖。
請參照第1圖及第2A至2M圖，第1圖繪示依照本發明一實施例之半導體封裝件的製造方法流程圖，第2A至2M圖繪示依照本發明一實施例之半導體封裝件的製造示意圖。
於步驟S102中，如第2A圖所示，提供一電性載板102。其中，電性載板102具有相對之第一面102a與第二面102b。電性載板102可以是金屬板(plate)，例如是銅、鐵或鋼板。
於步驟S104中，如第2B圖所示，應用例如是微影製程 (photolithography)技術及電鍍技術(electrolytic plating)，形成一導線層104於電性載板102之第二面102b。其中，導線層104例如是圖案化導線層，其包括至少一走線106及至少一晶片座108。導線層104之材質可以是金屬，例如是銅。
於步驟S106中，如第2C圖所示，應用例如是微影製程(photolithography)技術及電鍍方法(electrolytic plating)，形成一導柱層於導線層104上。其中，導柱層包括至少一導電柱110，其形成於對應之走線106及晶片座108上。導電柱110之材質可以是金屬，例如是銅。
於步驟s108中，如第2D圖所示，應用例如是轉注成型(transfer molding)之封裝技術，形成一第一封裝體112包覆導線層104及導柱層且覆蓋第二面102b。本實施例中，第一封裝體112係以導線層104及導柱層做為封裝對像。第一封裝體112之材質可包括酚醛基樹脂(novolac-based resin)、環氧基樹脂(epoxy-based resin)、矽基樹脂(silicone-based resin)或其他適當之包覆劑，在高溫和高壓下，以液體狀態包覆導線層104及導柱層，其固化後形成第一封裝體112。第一封裝體112亦可包括適當之填充劑，例如是粉狀之二氧化矽。
形成第一封裝體112之步驟大致如下：提供一包覆劑，其中包覆劑包括樹脂及粉狀之二氧化矽；然後，加熱包覆劑至液體狀態；注入包覆劑於電性載板102之第二面102b上，包覆劑在高溫和高壓下包覆導線層104及導柱層(包括至少一導電柱110)；然後，固化包覆劑形成第一封裝體112。
於其他實施態樣中，亦可應用注射成型(injection molding) 或壓縮成型(compression molding)形成第一封裝體112。
較佳但非限定地，在形成第一封裝體112前，可形成一黏附層(未繪示)於導線層104的表面及導柱層的表面，加強與第一封裝體112的黏力，提高可靠性。
於步驟S110中，如第2E圖所示，應用例如是磨削(grinding)方式，移除第一封裝體112之一部分，以露出導電柱110之一端110a的端面110b。第一封裝體112被磨削後露出一第一封裝表面112a，導電柱110被磨削後露出端面110b，較佳但非限定地，導電柱110之端面110b與第一封裝表面112a係實質上對齊，例如是共面。在其他實施態樣中，可在形成第一封裝體112的同時，露出導電柱110之一端110a的端面110b，而無需移除第一封裝體112的任何部分。
於步驟S112中，如第2F圖所示，形成一電鍍導電層114完全地包覆電性載板102、第一封裝體112及露出之導電柱110之該端110a。例如，應用例如是無電鍍法(electroless plating)，形成電鍍導電層114完全地包覆電性載板102之整個第一面102a、整個側面102c及露出之第二面102b、第一封裝體112之第一封裝表面112a及封裝側面112b以及露出之導電柱110之該端110a。在本步驟S112中，電鍍導電層114的厚度大約介於6μm至10μm之間。此外，電鍍導電層114例如是單層之銅(Cu)層或其他種類之金屬層。
此外，電鍍導電層114亦可為多層金屬層。例如，於另一實施態樣中，步驟S112更包括以下二步驟：首先，應用無電鍍法(electroless plating)，形成一種子層(seed layer)(未繪示)完全地包覆電性載板102、 第一封裝體112及露出之導電柱110之該端110a。該種子層之包覆範圍相似於上述電鍍導電層114的包覆範圍；然後，應用電鍍方法(electrolytic plating)，形成一子導電層完全地包覆該種子層。其中，該子導電層例如是銅層或其他種類之金屬層。上述種子層的厚度例如是介於約1μm至2μm之間，而上述子導電層的厚度例如是介於約5μm至8μm之間。
於步驟S114中，如第2G圖所示，形成至少一缺口116，其中，導線層104及第一封裝體112從缺口116露出。例如，應用微影製程或蝕刻技術，移除電性載板102之一部分，以形成缺口116貫穿電鍍導電層114之一部分及電性載板102之一部分。導線層104之導線表面104a及第一封裝體112之第二封裝表面112c係從缺口116露出，其中，導線表面104a及第二封裝表面112c係相對於第一封裝表面112a。晶片座108具有晶片座表面108a，走線106具有走線表面106a，晶片座表面108a與走線表面106a定義上述導線表面104a。較佳但非限定地，如以蝕刻技術移除部份電性載板102，則導線層104更可包括一蝕刻阻擋層(未繪示)，其介於電性載板102與導線層104之間。蝕刻阻擋層的材質例如是鎳(Ni)與金(Au)中至少一者。
在部份之電性載板102後，電性載板102之餘留部可形成一電鍍固環134，其環繞第一封裝體112之周邊。電鍍固環134透過電鍍導電層114電性連接於導電柱110和導線層104。
於步驟S116中，如第2H圖所示，形成第一表面處理層(first surface finishing)118a於露出之導線層104上。例如，應用電鍍技術形成第一表面處理層118a於導線層104中從缺口116露出之整個導線表面104a。
其他實施態樣中，可應用例如是微影製程，形成第一表面處理層118a於導線層104中從缺口116露出之部分導線表面104a上。例如，第一表面處理層118a僅形成於走線106之走線表面106a上，而不形成於晶片座108之晶片座表面108a上。又例如，第一表面處理層118a可僅形成於走線106之部分走線表面106a上。
第一表面處理層118a的材質例如是鎳(Ni)、鈀(Pa)與金(Au)中至少一者，其可應用例如是電鍍技術形成。
由於步驟S114之電鍍導電層114電性接觸於導電柱110，使導線層104可透過導電柱110電性連接於電鍍導電層114。最外圍之電鍍固環134可與電鍍設備的電極電性連接，讓電流透過電鍍導電層114以電鍍方法形成第一表面處理層118a於導線層104上。進一步地說，如第2H圖所示，雖然走線106與晶片座108被第一封裝體112隔離(包括相鄰二走線之間)，然藉由電鍍導電層114電性連接全部的導線層104，可於相同製程中以電鍍法一次形成第一表面處理層118a於全部的導線層104上。
於步驟S118中，如第2I圖所示，應用例如是化學蝕刻(chemical etching)方法，移除全部的電鍍導電層114，以露出導電柱110之一端110a的端面110b與第一封裝表面112a。移除電鍍導電層114後，導線層104的每一走線106及每一晶片座108相互隔離。
於步驟S120中，如第2J圖所示，應用例如是無電鍍法(electroless plating)，形成第二表面處理層(second surface finishing)118b於露出之導電柱110之一端110a的端面110b上。至此，形成本實施例之半導體承載元件120。
請參照第4圖，其繪示第2J圖中半導體承載元件之上視圖。由第4圖可知，導線層104與電鍍固環134被第一封裝體112隔離，然此非用以限制本發明。於其他實施態樣中，請參照第5A第5B圖，第5A圖繪示依照本發明另一實施例之半導體承載元件之剖視圖，第5B圖繪示第5A圖中半導體承載元件之上視圖。半導體承載元件320之導線層304電性連接於半導體承載元件320之電鍍固環334，其中，每一走線306及每一晶片座308更相互連接並電性接觸於電鍍固環334。
如第2J圖所示，電鍍導電層114全部被移除，然此非用以限制本發明，以下係舉例說明。
請參照第3A至3B圖，其繪示依照本發明另一實施例之半導體承載元件之製造過程圖。
如第3A圖所示，電鍍導電層114之一部分被移除而保留一餘留部(remaining portion)114a，電鍍導電層114之餘留部114a至少覆蓋導電柱110。於本實施例中，電鍍導電層114之餘留部114a覆蓋導電柱110之整個端面110b及露出之第一封裝體112之第一封裝表面112a的一部分。進一步地說，電鍍導電層114之餘留部114a的面積大於導電柱110之端面110b之面積，以此較大面積的餘留部114a作為電性接墊(bond pad)，有助於提升電性品質。於其他實施態樣中，電鍍導電層114之餘留部114a可僅覆蓋導電柱110之端面110b而不覆蓋第一封裝表面112a。
如第3B圖所示，可應用例如是無電鍍法(electroless plating)，形成第二表面處理層(second surface finishing)118b於電鍍導電層114之餘留部114a上。
如第3B圖所示，餘留部114a可於移除電鍍導電層114之過程中同時形成。進一步地說，本實施例可不需額外製程於導電柱110之端面110b上形成第二表面處理層118b，電鍍導電層114之一部分被移除後，第二表面處理層118b即形成。至此，形成半導體承載元件220。另一實施例中，可對半導體承載元件220執行後續步驟S122至S126之製程，以形成半導體封裝件。
於步驟S122中，如第2K圖所示，鄰近導線層104設置至少一半導體元件122。例如，半導體元件122具有相對之背面與主動表面122a，半導體元件122之背面設於黏膠128上，半導體元件122之主動表面122a係朝上(face-up)並藉由銲線124電性接觸於走線106上之第一表面處理層118a，以電性連接於走線106。此外，半導體元件130之主動面可朝下(face-down)設置且具有數個電性接點132，電性接點132電性接觸於晶片座108與走線106中至少一者上之第一表面處理層118a。半導體元件130的種類例如是覆晶(flip-chip)。其他實施態樣中，若沒有第一表面處理層118a，則半導體元件130之電性接點132可直接電性接觸於晶片座108與走線106中至少一者。
於步驟S124中，如第2L圖所示，應用封裝技術，形成第二封裝體126包覆半導體元件122及銲線124。
於步驟S126中，如第2M圖所示，以切割刀具或雷射，切割第二封裝體126及第一封裝體112，以分離封裝之後的半導體承載元件120。至此，形成半導體封裝件100。
本發明上述實施例之半導體承載元件的製造方法及應用其 之半導體封裝件的製造方法，半導體承載元件之封裝體包覆導電柱，導電柱係電性連接半導體承載元件之相對二側，由於封裝體的厚度較薄，可有效縮小半導體封裝件的尺寸。此外，此製造方法可用以形成電鍍表面處理層於相互隔離的走線與晶片座，有助於提升產品的穩定性與可靠性。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
110a‧‧‧一端
110b‧‧‧端面
112‧‧‧第一封裝體
112a‧‧‧第一封裝表面
118b‧‧‧第二表面處理層
120‧‧‧半導體承載元件
134‧‧‧電鍍固環

Claims (75)

  1. 一種半導體承載元件，包括：一介電層，具有相對之一第一表面與一第二表面；一導線層，係埋設於該介電層中，且暴露於該介電層之該第二表面；一導柱層，係埋設於同一該介電層中，且暴露於同一該介電層之該第一表面，並與該導線層電性相連；以及一電鍍導電層，設置在該介電層之該第一表面及暴露出的該導柱層上。
  2. 如申請專利範圍第1項所述的半導體承載元件，更包括：一電性載板，設置在該介電層的該第二表面上。
  3. 如申請專利範圍第2項所述之半導體承載元件，其中該電性載板係為金屬板，包括鋼或銅。
  4. 如申請專利範圍第1項所述之半導體承載元件，其中該導線層包括至少一走線。
  5. 如申請專利範圍第4項所述之半導體承載元件，其中該導線層更包括至少一晶片座。
  6. 如申請專利範圍第1項所述之半導體承載元件，其中該導線層及該導柱層之材質係為銅。
  7. 如申請專利範圍第1項所述之半導體承載元件，其中該導線層更包括一蝕刻阻擋層。
  8. 如申請專利範圍第7項所述之半導體承載元件，其中該蝕 刻阻擋層之材質係為鎳或金。
  9. 如申請專利範圍第1項所述之半導體承載元件，更包括：一第一表面處理層，係設置在暴露於該介電層之該第二表面的該導線層之至少一部分上。
  10. 如申請專利範圍第1項所述之半導體承載元件，其中該介電層係由包括樹脂材料的包覆劑形成。
  11. 如申請專利範圍第10項所述之半導體承載元件，其中該包覆劑更包括一填充材料。
  12. 如申請專利範圍第11項所述之半導體承載元件，其中該樹脂材料係為環氧基樹脂，該填充材料係為粉狀之二氧化硅。
  13. 如申請專利範圍第1項所述之半導體承載元件，其中該介電層係以轉注成型、注射成型或壓縮成型的方式形成。
  14. 如申請專利範圍第1項所述之半導體承載元件，其中該介電層包覆該導線層及該導柱層。
  15. 如申請專利範圍第1項所述之半導體承載元件，更包括：一黏附層，係設置在該導線層及該導柱層上，以加強與該介電層的黏力。
  16. 如申請專利範圍第2項所述的半導體承載元件，其中該電性載板具有至少一凹部，該導線層及該介電層從該凹部露出。
  17. 如申請專利範圍第16項所述之半導體承載元件，其中該介電層更具有側面，該電鍍導電層並設置在該介電層之側面及該電性載板上。
  18. 如申請專利範圍第17項所述之半導體承載元件，其中該導線層透過該導柱層與該電鍍導電層電性連於該電性載板。
  19. 如申請專利範圍第16項所述之半導體承載元件，其中該導線層包括複數個走線，該些走線係相互隔離。
  20. 如申請專利範圍第19項所述之半導體承載元件，其中該導柱層包括複數個導電柱，該電鍍導電層電性連接該些導電柱，且該些導電柱係與該些走線電性相連。
  21. 如申請專利範圍第19項所述之半導體承載元件，更包括：一第一表面處理層，係使用電鍍方法，透過該電性載板、該電鍍導電層及該導柱層一次形成在該些走線上。
  22. 如申請專利範圍第1項所述之半導體承載元件，其中該電鍍導電層包括一種子層及一子導電層。
  23. 如申請專利範圍第16項所述之半導體承載元件，其中該電性載板之凹部係透過移除該電性載板之一部分形成。
  24. 如申請專利範圍第23項所述之半導體承載元件，其中該電性載板之一餘留部形成一電鍍固環，該電鍍固環環繞該介電層之周邊。
  25. 如申請專利範圍第24項所述之半導體承載元件，其中該電鍍固環透過該電鍍導電層與該導柱層電性連於該導線層。
  26. 如申請專利範圍第1項所述之半導體承載元件，其中該 電鍍導電層包括複數個電性接墊。
  27. 如申請專利範圍第26項所述之半導體承載元件，其中該電鍍導電層更包括一餘留部，該餘留部與該些電性接墊相連並向該介電層之該第一表面延伸。
  28. 如申請專利範圍第27項所述之半導體承載元件，其中該些電性接墊覆蓋露出的該導電柱之至少一部分。
  29. 一種半導體承載元件，包括：一介電層，具有相對之一第一表面與一第二表面；複數個走線，係埋設於該介電層中，且暴露於該介電層之該第二表面；複數個電性接墊，設置在該介電層之該第一表面上；以及複數個導電柱，係埋設於同一該介電層中，且暴露於同一該介電層之該第一表面，其中，該些導電柱與該些走線及該些電性接墊電性相連。
  30. 如申請專利範圍第29項所述的半導體承載元件，更包括：一電性載板，設置在該介電層的該第二表面上。
  31. 如申請專利範圍第30項所述之半導體承載元件，其中該電性載板係為金屬板，包括鋼或銅。
  32. 如申請專利範圍第29項所述之半導體承載元件，其中該些走線係相互隔離。
  33. 如申請專利範圍第29項所述之半導體承載元件，更包 括：一第一表面處理層，係設置在暴露於該介電層之該第二表面的該些走線之至少一部分上。
  34. 如申請專利範圍第29項所述之半導體承載元件，其中該介電層係由包括樹脂材料的包覆劑形成。
  35. 如申請專利範圍第34項所述之半導體承載元件，其中該包覆劑更包括一填充材料。
  36. 如申請專利範圍第35項所述之半導體承載元件，其中該樹脂材料係為環氧基樹脂，該填充材料係為粉狀之二氧化硅。
  37. 如申請專利範圍第29項所述之半導體承載元件，其中該介電層係以轉注成型、注射成型或壓縮成型的方式形成。
  38. 如申請專利範圍第29項所述之半導體承載元件，其中該介電層包覆該些走線及該些導電柱。
  39. 如申請專利範圍第29項所述之半導體承載元件，更包括：一黏附層，係設置在該些走線及該些導電柱上，以加強與該介電層的黏力。
  40. 如申請專利範圍第30項所述的半導體承載元件，其中該電性載板具有至少一凹部，該些走線及該介電層從該凹部露出。
  41. 如申請專利範圍第40項所述之半導體承載元件，其中該電性載板之凹部係透過移除該電性載板之一部分形成。
  42. 如申請專利範圍第41項所述之半導體承載元件，其中該 電性載板之一餘留部形成一電鍍固環，該電鍍固環環繞該介電層之周邊。
  43. 如申請專利範圍第42項所述之半導體承載元件，其中該些走線電性連於該電鍍固環。
  44. 如申請專利範圍第29項所述之半導體承載元件，其中各該導電柱具有一端面，該導電柱之該端面與該介電層之該第一表面係露出且實質上對齊。
  45. 如申請專利範圍第44項所述之半導體承載元件，其中該些電性接墊設置在該些導電柱之該端面上，且電性連接該些導電柱。
  46. 如申請專利範圍第45項所述之半導體承載元件，其中該些電性接墊覆蓋該些導電柱之該端面之至少一部分。
  47. 如申請專利範圍第45項所述之半導體承載元件，其中該些電性接墊的面積大於該些導電柱之該端面的面積。
  48. 如申請專利範圍第29項所述之半導體承載元件，更包括：一第二表面處理層，係設置在該些電性接墊上。
  49. 如申請專利範圍第29項所述之半導體承載元件，更包括：一餘留部，該餘留部與該些電性接墊相連並向該介電層之該第一表面延伸。
  50. 如申請專利範圍第49項所述之半導體承載元件，其中餘 留部包括一種子層及一子導電層。
  51. 一種半導體封裝件，包括：一介電層，具有相對之一第一表面與一第二表面；複數個走線，係埋設於該介電層中，且暴露於該介電層之該第二表面；複數個電性接墊，設置在該介電層之該第一表面上；複數個導電柱，係埋設於同一該介電層中，且暴露於同一該介電層之該第一表面，其中，該些導電柱與該些走線及該些電性接墊電性相連；以及至少一半導體元件，設置在該介電層之該第二表面上，並電性連接該些走線。
  52. 如申請專利範圍第51項所述之半導體封裝件，其中該半導體元件具有相對之背面與主動表面，該半導體元件係以朝上方式設置，其中該背面由一黏膠黏附於該介電層之該第二表面，該主動表面面向遠離該介電層之該第二表面的方向且以打線方式電性連接該些走線。
  53. 如申請專利範圍第51項所述之半導體封裝件，其中該半導體元件具有相對之背面與主動表面，該半導體元件以主動表面面向該介電層之該第二表面的朝下方式設置，且通過一連接件電性接觸於該些走線。
  54. 如申請專利範圍第51項所述之半導體封裝件，更包括：一第二介電層，包覆該至少一半導體元件。
  55. 如申請專利範圍第51項所述之半導體封裝件，更包括：一第一表面處理層，係設置在暴露於該介電層之該第二表面的該些走線之至少一部分上。
  56. 如申請專利範圍第51項所述之半導體封裝件，更包括：一電性載板，設置於該介電層之上。
  57. 如申請專利範圍第56項所述之半導體封裝件，其中該電性載板具有至少一凹部，且該些走線從該凹部露出。
  58. 如申請專利範圍第57項所述之半導體封裝件，其中該半導體元件係設置於該凹部內。
  59. 如申請專利範圍第56項所述之半導體封裝件，其中該電性載板係為金屬板，包括鋼或銅。
  60. 如申請專利範圍第57項所述之半導體封裝件，其中該電性載板之凹部係透過移除該電性載板之一部分形成。
  61. 如申請專利範圍第60項所述之半導體封裝件，其中該電性載板之一餘留部形成一電鍍固環，該電鍍固環環繞該介電層之周邊。
  62. 如申請專利範圍第61項所述之半導體封裝件，其中該些走線電性連於該電鍍固環。
  63. 如申請專利範圍第51項所述之半導體封裝件，其中該介電層係由包括樹脂材料的包覆劑形成。
  64. 如申請專利範圍第63項所述之半導體封裝件，其中該包覆劑更包括一填充材料。
  65. 如申請專利範圍第64項所述之半導體封裝件，其中該樹脂材料係為環氧基樹脂，該填充材料係為粉狀之二氧化硅。
  66. 如申請專利範圍第51項所述之半導體封裝件，其中該介電層係以轉注成型、注射成型或壓縮成型的方式形成。
  67. 如申請專利範圍第51項所述之半導體封裝件，其中該介電層包覆該些走線及該些導電柱。
  68. 如申請專利範圍第51項所述之半導體封裝件，更包括：一黏附層，係設置在該些走線及該些導電柱上，以加強與該介電層的黏力。
  69. 如申請專利範圍第51項所述之半導體封裝件，其中各該導電柱具有一端面，該導電柱之該端面與該介電層之該第一表面係露出且實質上對齊。
  70. 如申請專利範圍第69項所述之半導體封裝件，其中該些電性接墊設置在該些導電柱之該端面上，且電性連接該些導電柱。
  71. 如申請專利範圍第70項所述之半導體封裝件，其中該些電性接墊覆蓋該些導電柱之該端面之至少一部分。
  72. 如申請專利範圍第70項所述之半導體封裝件，其中該些電性接墊的面積大於該些導電柱之該端面的面積。
  73. 如申請專利範圍第51項所述之半導體封裝件，更包括：一第二表面處理層，係設置在該些電性接墊上。
  74. 如申請專利範圍第51項所述之半導體封裝件，更包括： 一餘留部，該餘留部與該些電性接墊相連並向該介電層之該第一表面延伸。
  75. 如申請專利範圍第74項所述之半導體封裝件，其中餘留部包括一種子層及一子導電層。
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