CN103824836B - 半导体承载元件及半导体封装件 - Google Patents
半导体承载元件及半导体封装件 Download PDFInfo
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- CN103824836B CN103824836B CN201410059244.7A CN201410059244A CN103824836B CN 103824836 B CN103824836 B CN 103824836B CN 201410059244 A CN201410059244 A CN 201410059244A CN 103824836 B CN103824836 B CN 103824836B
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Abstract
本发明公开一种半导体承载元件及半导体封装件。半导体承载元件包括电性载板、介电层、导线层、导柱层及电镀导电层。电性载板具有至少一凹部。介电层具有相对的第一表面与第二表面。导线层埋设于介电层中,并暴露于介电层的第二表面。导柱层埋设于介电层中且暴露于介电层的第一表面,导柱层与导线层电性相连。电镀导电层设置在介电层的第一表面及露出的导柱层上。
Description
本申请是申请日为2011年8月31日且发明名称为“半导体承载元件的制造方法及应用其的封装件的制造方法”的中国专利申请201110255914.9的分案申请。
技术领域
本发明涉及一种半导体承载元件及半导体封装件,且特别是涉及一种具有凹部的半导体承载元件及半导体封装件。
背景技术
传统的半导体结构包括基板、芯片及焊线。基板例如是塑胶或陶瓷基板,其用以承载芯片。基板具有相对的第一面与第二面且包括接垫及导通贯孔。芯片设于基板的第一面上,焊线连接芯片与位于基板的第一面上的接垫。基板的接垫通过导通贯孔电连接于基板的第二面。
然而,由于导通贯孔贯穿基板,因此降低基板的结构强度。且,由于导通贯孔降低基板的结构强度,为了不使基板的结构强度过低,导通贯孔相距基板的外侧面一较大距离,用于提升基板的结构强度至一正常范围,但如此将导致半导体封装件的尺寸无法缩小。此外,基板的厚度一般也较厚,使半导体封装件的厚度无法缩小。
发明内容
本发明的目的在于提供一种半导体承载元件及半导体封装件,半导体承载元件的封装体包覆导柱层,导柱层电连接半导体承载元件的相对两侧,由于封装体的厚度较薄,可有效缩小半导体封装件的尺寸。
为达上述目的,根据本发明的第一方面,提出一种半导体承载元件。半导体承载元件包括电性载板、介电层、导线层、导柱层及电镀导电层。电性载板具有至少一凹部。介电层具有相对的第一表面与第二表面。导线层埋设 于介电层中,并暴露于介电层的第二表面。导柱层埋设于介电层中且暴露于介电层的第一表面,导柱层与导线层电性相连。电镀导电层设置在介电层的第一表面及露出的导柱层上。其中,导线层及介电层从凹部露出。
根据本发明的第二方面,提出一种半导体承载元件。半导体承载元件包括电性载板、介电层、多个走线、多个电性接垫及多个导电柱。电性载板具有至少一凹部。介电层具有相对的第一表面与第二表面。多个走线埋设于介电层中,并暴露于介电层的第二表面。多个电性接垫设置在介电层的第一表面上。多个导电柱埋设于介电层中且暴露于介电层的第一表面,该些导电柱与该些走线及该些电性接垫电性相连,其中,该些走线及该介电层从凹部露出。
根据本发明的第三方面,提出一种半导体封装件。半导体封装件包括介电层、多个走线、多个电性接垫、多个导电柱及至少一半导体元件。介电层具有相对的第一表面与第二表面。多个走线埋设于介电层中,并暴露于介电层的第二表面。多个电性接垫设置在介电层的第一表面上。多个导电柱埋设于介电层中且暴露于介电层的第一表面,该些导电柱与该些走线及该些电性接垫电性相连。半导体元件设置在介电层的第二表面上,并电性连接走线。
为了对本发明的上述及其他方面有更佳的了解,下文特举实施例,并配合所附附图,作详细说明如下:
附图说明
图1为本发明一实施例的半导体封装件的制造方法流程图;
图2A至图2M为本发明一实施例的半导体封装件的制造示意图;
图3A至图3B为本发明另一实施例的半导体承载元件的制造过程图;
图4为图2J中半导体承载元件的上视图;
图5A为本发明另一实施例的半导体承载元件的剖视图;
图5B为图5A中半导体承载元件的上视图。
主要元件符号说明
100:半导体封装件
102:电性载板
102a:第一面
102b:第二面
102c:侧面
104、304:导线层
104a:导线表面
106、306:走线
106a:走线表面
108、308:芯片座
108a:芯片座表面
110:导电柱
110a:一端
110b:端面
112:第一封装体
112a:第一封装表面
112b:封装侧面
112c:第二封装表面
114:电镀导电层
114a:余留部
116:缺口
118a:第一表面处理层
118b:第二表面处理层
120、220、320:半导体承载元件
132:电性接点
134、334:电镀固环
122、130:半导体元件
122a:主动表面
124:焊线
126:第二封装体
128:粘胶
S102—S126:步骤
具体实施方式
请参照图1及图2A至图2M,图1绘示依照本发明一实施例的半导体封装件的制造方法流程图,图2A至图2M绘示依照本发明一实施例的半导体封装件的制造示意图。
在步骤S102中,如图2A所示,提供一电性载板102。其中,电性载板102具有相对的第一面102a与第二面102b。电性载板102可以是金属板(plate),例如是铜、铁或钢板。
在步骤S104中,如图2B所示,应用例如是光刻制作工艺(photolithography)技术及电镀技术(electrolytic plating),形成一导线层104于电性载板102的第二面102b。其中,导线层104例如是图案化导线层,其包括至少一走线106及至少一芯片座108。导线层104的材质可以是金属,例如是铜。
在步骤S106中,如图2C所示,应用例如是光刻制作工艺(photolithography)技术及电镀方法(electrolytic plating),形成一导柱层于导线层104上。其中,导柱层包括至少一导电柱110,其形成于对应的走线106及芯片座108上。导电柱110的材质可以是金属,例如是铜。
在步骤S108中,如图2D所示,应用例如是转注成型(transfer molding)的封装技术,形成一第一封装体112包覆导线层104及导柱层且覆盖第二面102b。本实施例中,第一封装体112以导线层104及导柱层做为封装对像。第一封装体112的材质可包括酚醛基树脂(novolac-based resin)、环氧基树脂(epoxy-based resin)、硅基树脂(silicone-basedresin)或其他适当的包覆剂,在高温和高压下,以液体状态包覆导线层104及导柱层,其固化后形成第一封装体112。第一封装体112也可包括适当的填充剂,例如是粉状的二氧化硅。
形成第一封装体112的步骤大致如下:提供一包覆剂,其中包覆剂包括树脂及粉状的二氧化硅;然后,加热包覆剂至液体状态;注入包覆剂于电性载板102的第二面102b上,包覆剂在高温和高压下包覆导线层104及导柱层(包括至少一导电柱110);然后,固化包覆剂形成第一封装体112。
在其他实施态样中,也可应用注射成型(injection molding)或压缩成型(compression molding)形成第一封装体112。
较佳但非限定地,在形成第一封装体112前,可形成一粘附层(未绘示)于导线层104的表面及导柱层的表面,加强与第一封装体112的黏力,提高 可靠性。
在步骤S110中,如图2E所示,应用例如是磨削(grinding)方式,移除第一封装体112的一部分,以露出导电柱110的一端110a的端面110b。第一封装体112被磨削后露出一第一封装表面112a,导电柱110被磨削后露出端面110b,较佳但非限定地,导电柱110的端面110b与第一封装表面112a实质上对齐,例如是共面。在其他实施态样中,可在形成第一封装体112的同时,露出导电柱110的一端110a的端面110b,而无需移除第一封装体112的任何部分。
在步骤S112中,如图2F所示,形成一电镀导电层114完全地包覆电性载板102、第一封装体112及露出的导电柱110的该端110a。例如,应用例如是无电镀法(electrolessplating),形成电镀导电层114完全地包覆电性载板102的整个第一面102a、整个侧面102c及露出的第二面102b、第一封装体112的第一封装表面112a及封装侧面112b以及露出的导电柱110的该端110a。在本步骤S112中,电镀导电层114的厚度大约介于6μm至10μm之间。此外,电镀导电层114例如是单层的铜(Cu)层或其他种类的金属层。
此外,电镀导电层114也可为多层金属层。例如,在另一实施态样中,步骤S112还包括以下两个步骤:首先,应用无电镀法(electroless plating),形成一籽晶层(seed layer也称种子层)(未绘示)完全地包覆电性载板102、第一封装体112及露出的导电柱110的该端110a。该籽晶层的包覆范围相似于上述电镀导电层114的包覆范围;然后,应用电镀方法(electrolytic plating),形成一子导电层完全地包覆该籽晶层。其中,该子导电层例如是铜层或其他种类的金属层。上述籽晶层的厚度例如是介于约1μm至2μm之间,而上述子导电层的厚度例如是介于约5μm至8μm之间。
在步骤S114中,如图2G所示,形成至少一缺口116,其中,导线层104及第一封装体112从缺口116露出。例如,应用光刻制作工艺或蚀刻技术,移除电性载板102的一部分,以形成缺口116贯穿电镀导电层114的一部分及电性载板102的一部分。导线层104的导线表面104a及第一封装体112的第二封装表面112c从缺口116露出,其中,导线表面104a及第二封装表面112c相对于第一封装表面112a。芯片座108具有芯片座表面108a,走线106具有走线表面106a,芯片座表面108a与走线表面106a定义上述导线表面104a。较佳但非限定地,如以蚀刻技术移除部分电性载板102,则导线层 104更可包括一蚀刻阻挡层(未绘示),其介于电性载板102与导线层104之间。蚀刻阻挡层的材质例如是镍(Ni)与金(Au)中至少一者。
在部分的电性载板102后,电性载板102的余留部可形成一电镀固环134,其环绕第一封装体112的周边。电镀固环134通过电镀导电层114电连接于导电柱110和导线层104。
在步骤S116中,如图2H所示,形成第一表面处理层(first surface finishing)118a于露出的导线层104上。例如,应用电镀技术形成第一表面处理层118a于导线层104中从缺口116露出的整个导线表面104a。
其他实施态样中,可应用例如是光刻制作工艺,形成第一表面处理层118a于导线层104中从缺口116露出的部分导线表面104a上。例如,第一表面处理层118a仅形成于走线106的走线表面106a上,而不形成于芯片座108的芯片座表面108a上。又例如,第一表面处理层118a可仅形成于走线106的部分走线表面106a上。
第一表面处理层118a的材质例如是镍(Ni)、钯(Pa)与金(Au)中至少一者,其可应用例如是电镀技术形成。
由于步骤S114的电镀导电层114电性接触于导电柱110,使导线层104可通过导电柱110电连接于电镀导电层114。最外围的电镀固环134可与电镀设备的电极电连接,让电流通过电镀导电层114以电镀方法形成第一表面处理层118a于导线层104上。进一步地说,如图2H所示,虽然走线106与芯片座108被第一封装体112隔离(包括相邻两个走线之间),然通过电镀导电层114电连接全部的导线层104,可在相同制作工艺中以电镀法一次形成第一表面处理层118a于全部的导线层104上。
在步骤S118中,如图2I所示,应用例如是化学蚀刻(chemical etching)方法,移除全部的电镀导电层114,以露出导电柱110的一端110a的端面110b与第一封装表面112a。移除电镀导电层114后,导线层104的每一走线106及每一芯片座108相互隔离。
在步骤S120中,如图2J所示,应用例如是无电镀法(electroless plating),形成第二表面处理层(second surface finishing)118b于露出的导电柱110的一端110a的端面110b上。至此,形成本实施例的半导体承载元件120。
请参照图4,其绘示图2J中半导体承载元件的上视图。由图4可知,导线层104与电镀固环134被第一封装体112隔离,然此非用以限制本发明。 在其他实施态样中,请参照图5A及图5B,图5A绘示依照本发明另一实施例的半导体承载元件的剖视图,图5B绘示图5A中半导体承载元件的上视图。半导体承载元件320的导线层304电连接于半导体承载元件320的电镀固环334,其中,每一走线306及每一芯片座308更相互连接并电性接触于电镀固环334。
如图2J所示,电镀导电层114全部被移除,然此非用以限制本发明,以下举例说明。
请参照图3A至图3B,其绘示依照本发明另一实施例的半导体承载元件的制造过程图。
如图3A所示,电镀导电层114的一部分被移除而保留一余留部(remainingportion)114a,电镀导电层114的余留部114a至少覆盖导电柱110。在本实施例中,电镀导电层114的余留部114a覆盖导电柱110的整个端面110b及露出的第一封装体112的第一封装表面112a的一部分。进一步地说,电镀导电层114的余留部114a的面积大于导电柱110的端面110b的面积,以此较大面积的余留部114a作为电性接垫(bond pad),有助于提升电性品质。在其他实施态样中,电镀导电层114的余留部114a可仅覆盖导电柱110的端面110b而不覆盖第一封装表面112a。
如图3B所示,可应用例如是无电镀法(electroless plating),形成第二表面处理层(second surface finishing)118b于电镀导电层114的余留部114a上。
如图3B所示,余留部114a可于移除电镀导电层114的过程中同时形成。进一步地说,本实施例可不需额外制作工艺于导电柱110的端面110b上形成第二表面处理层118b,电镀导电层114的一部分被移除后,第二表面处理层118b即形成。至此,形成半导体承载元件220。另一实施例中,可对半导体承载元件220执行后续步骤S122至S126的制作工艺,以形成半导体封装件。
在步骤S122中,如图2K所示,邻近导线层104设置至少一半导体元件122。例如,半导体元件122具有相对的背面与主动表面122a,半导体元件122的背面设于粘胶128上,半导体元件122的主动表面122a朝上(face-up)并通过焊线124电性接触于走线106上的第一表面处理层118a,以电连接于走线106。此外,半导体元件130的主动面可朝下(face-down)设置且具有 数个电性接点132,电性接点132电性接触于芯片座108与走线106中至少一者上的第一表面处理层118a。半导体元件130的种类例如是覆晶(flip-chip)。其他实施态样中,若没有第一表面处理层118a,则半导体元件130的电性接点132可直接电性接触于芯片座108与走线106中至少一者。
在步骤S124中,如图2L所示,应用封装技术,形成第二封装体126包覆半导体元件122及焊线124。
在步骤S126中,如图2M所示,以切割刀具或激光,切割第二封装体126及第一封装体112,以分离封装之后的半导体承载元件120。至此,形成半导体封装件100。
本发明上述实施例的半导体承载元件及半导体封装件,半导体承载元件的封装体包覆导电柱,导电柱电连接半导体承载元件的相对两侧,由于封装体的厚度较薄,可有效缩小半导体封装件的尺寸。此外,此制造方法可用以形成电镀表面处理层于相互隔离的走线与芯片座,有助于提升产品的稳定性与可靠性。
综上所述,虽然已结合以上实施例揭露了本发明,然而其并非用以限定本发明。本发明所属技术领域中熟悉此技术者,在不脱离本发明的精神和范围内,可作各种的更动与润饰。因此,本发明的保护范围应以附上的权利要求所界定的为准。
Claims (70)
1.一种半导体承载元件,包括:
电性载板;
第一封装体,具有相对的第一表面与第二表面及封装侧面;
导线层,埋设于该第一封装体中,并暴露于该第一封装体的该第二表面;
导柱层,埋设于该第一封装体中且暴露于该第一封装体的该第一表面,该导柱层与该导线层电性相连;以及
电镀导电层,设置在该第一封装体的该第一表面、该封装侧面、该电性载板及露出的该导柱层上,其中该导线层通过该导柱层与该电镀导电层而电性连接于该电性载板。
2.如权利要求1所述的半导体承载元件,其中该电性载板为金属板,包括铜或钢。
3.如权利要求1所述的半导体承载元件,其中该导线层包括至少一走线。
4.如权利要求3所述的半导体承载元件,其中该导线层还包括至少一芯片座。
5.如权利要求1所述的半导体承载元件,其中该导线层及该导柱层的材质为铜。
6.如权利要求1所述的半导体承载元件,其中该导线层还包括蚀刻阻挡层。
7.如权利要求6所述的半导体承载元件,其中该蚀刻阻挡层的材质为镍或金。
8.如权利要求1所述的半导体承载元件,还包括:
第一表面处理层,设置在暴露于该第一封装体的该第二表面的该导线层的至少一部分上。
9.如权利要求1所述的半导体承载元件,其中该第一封装体由包括树脂材料的包覆剂形成。
10.如权利要求9所述的半导体承载元件,其中该包覆剂还包括填充 材料。
11.如权利要求10所述的半导体承载元件,其中该树脂材料为环氧基树脂,该填充材料为粉状的二氧化硅。
12.如权利要求1所述的半导体承载元件,其中该第一封装体是以转注成型、注射成型或压缩成型的方式形成。
13.如权利要求1所述的半导体承载元件,其中该第一封装体包覆该导线层及该导柱层。
14.如权利要求1所述的半导体承载元件,还包括:
粘附层,设置于该导线层及该导柱层上,以加强与该第一封装体的黏力。
15.如权利要求1所述的半导体承载元件,其中该电性载板具有至少一凹部。
16.如权利要求15所述的半导体承载元件,其中该导线层及该第一封装体从该凹部露出。
17.如权利要求1所述的半导体承载元件,其中该导线层包括多个走线,该些走线相互电隔离。
18.如权利要求17所述的半导体承载元件,其中该导柱层包括多个导电柱,该些导电柱与该些走线电性相连。
19.如权利要求18所述的半导体承载元件,还包括:
第一表面处理层,是使用电镀方法,通过该电性载板、该电镀导电层及该导柱层一层形成在该些走线上。
20.如权利要求1所述的半导体承载元件,其中该电镀导电层包括籽晶层及子导电层。
21.如权利要求15所述的半导体承载元件,其中该电性载板的凹部是通过移除该电性载板的一部分而形成。
22.如权利要求21所述的半导体承载元件,其中该电性载板的余留部形成电镀固环,该电镀固环环绕于该第一封装体的周边。
23.如权利要求22所述的半导体承载元件,其中该电镀固环通过该电镀导电层与该导柱层电性连接于该导线层。
24.如权利要求18所述的半导体承载元件,其中该电镀导电层包括多 个电性接垫。
25.如权利要求24所述的半导体承载元件,其中该电镀导电层还包括余留部,该余留部与该些电性接垫相连并朝该第一封装体的该第一表面延伸。
26.如权利要求24所述的半导体承载元件,其中该些电性接垫覆盖露出的该导电柱的至少一部分。
27.一种半导体承载元件,包括:
第一封装体,具有相对的第一表面与第二表面;
多个走线,埋设于该第一封装体中,并暴露于该第一封装体的该第二表面;
多个电性接垫,设置在该第一封装体的该第一表面上;以及
多个导电柱,埋设于该第一封装体中,该些导电柱的一端连接该些走线,该些导电柱的另一端则连接该些电性接垫,使该些走线与该些电性接垫电性相连。
28.如权利要求27所述的半导体承载元件,其中该电性载板为金属板,包括铜或钢。
29.如权利要求27所述的半导体承载元件,其中该些走线相互电隔离。
30.如权利要求27所述的半导体承载元件,还包括:
第一表面处理层,设置在暴露于该第一封装体的该第二表面的该些走线的至少一部分上。
31.如权利要求27所述的半导体承载元件,其中该第一封装体由包括树脂材料的包覆剂形成。
32.如权利要求31所述的半导体承载元件,其中该包覆剂还包括填充材料。
33.如权利要求32所述的半导体承载元件,其中该树脂材料为环氧基树脂,该填充材料为粉状的二氧化硅。
34.如权利要求27所述的半导体承载元件,其中该第一封装体是以转注成型、注射成型或压缩成型的方式形成。
35.如权利要求27所述的半导体承载元件,其中该第一封装体包覆该 些走线及该些导电柱。
36.如权利要求27所述的半导体承载元件,还包括:
粘附层,设置于该些走线及该些导电柱上,以加强与该第一封装体的黏力。
37.如权利要求27所述的半导体承载元件,还包括:
电性载板,设置于该第一封装体上,其中该电性载板具有至少一凹部,该电性载板的凹部是通过移除该电性载板的一部分而形成。
38.如权利要求37所述的半导体承载元件,其中该电性载板的余留部形成电镀固环,该电镀固环环绕于该第一封装体的周边。
39.如权利要求38所述的半导体承载元件,其中该些走线电性连接于该电镀固环。
40.如权利要求27所述的半导体承载元件,其中各该导电柱具有端面,该导电柱的端面露出于该第一封装体的该第一表面且与该第一封装体的该第一表面实质上对齐。
41.如权利要求40所述的半导体承载元件,其中该些电性接垫设置在该些导电柱的端面上,并电性连接该些导电柱。
42.如权利要求41所述的半导体承载元件,其中该些电性接垫覆盖该些导电柱的端面的至少一部分。
43.如权利要求41所述的半导体承载元件,其中该些电性接垫的面积大于该些导电柱的端面的面积。
44.如权利要求27所述的半导体承载元件,还包括:
第二表面处理层,设置在该些电性接垫上。
45.如权利要求27所述的半导体承载元件,还包括:
余留部,该余留部与该些电性接垫相连并朝该第一封装体的该第一表面延伸。
46.如权利要求45所述的半导体承载元件,其中该余留部包括籽晶层及子导电层。
47.一种半导体封装件,包括:
第一封装体,具有相对的第一表面与第二表面;
多个走线,埋设于该第一封装体中,并暴露于该第一封装体的该第二 表面;
多个电性接垫,设置在该第一封装体的该第一表面上;
多个导电柱,埋设于该第一封装体中,该些导电柱的一端连接该些走线,该些导电柱的另一端则连接该些电性接垫,使该些走线与该些电性接垫电性相连;以及
至少一半导体元件,设置在该第一封装体的该第二表面上,并通过该些走线及该些导电柱电性连接该些电性接垫。
48.如权利要求47所述的半导体封装件,其中该半导体元件具有相对的背面与主动表面,该半导体元件以朝上方式设置,其中该背面由粘胶粘附于该第一封装体的该第二表面,该主动表面面向远离该第一封装体的该第二表面的方向且以打线方式电性连接该些走线。
49.如权利要求47所述的半导体封装件,其中该半导体元件具有相对的背面与主动表面,该半导体元件以主动表面面向该第一封装体的该第二表面的朝下方式设置,且通过连接件电性接触于该些走线。
50.如权利要求47所述的半导体封装件,还包括:
第二封装体,包覆该至少一半导体元件。
51.如权利要求47所述的半导体封装件,还包括:
第一表面处理层,设置在暴露于该第一封装体的该第二表面的该些走线的至少一部分上。
52.如权利要求47所述的半导体封装件,还包括:
电性载板,设置于该第一封装体上,其中该电性载板具有至少一凹部且该些走线从该凹部露出。
53.如权利要求52所述的半导体封装件,其中该半导体元件设置于该凹部内。
54.如权利要求52所述的半导体封装件,其中该电性载板为金属板,包括铜或钢。
55.如权利要求52所述的半导体封装件,其中该电性载板的凹部是通过移除该电性载板的一部分而形成。
56.如权利要求55所述的半导体封装件,其中该电性载板的余留部形成电镀固环,该电镀固环环绕于该第一封装体的周边。
57.如权利要求56所述的半导体封装件,其中该些走线电性连接于该电镀固环。
58.如权利要求47所述的半导体封装件,其中该第一封装体由包括树脂材料的包覆剂形成。
59.如权利要求58所述的半导体封装件,其中该包覆剂还包括填充材料。
60.如权利要求59所述的半导体封装件,其中该树脂材料为环氧基树脂,该填充材料为粉状的二氧化硅。
61.如权利要求47所述的半导体封装件,其中该第一封装体是以转注成型、注射成型或压缩成型的方式形成。
62.如权利要求47所述的半导体封装件,其中该第一封装体包覆该些走线及该些导电柱。
63.如权利要求47所述的半导体封装件,还包括:
粘附层,设置于该些走线及该些导电柱上,以加强与该第一封装体的黏力。
64.如权利要求47所述的半导体封装件,其中各该导电柱具有端面,该导电柱的端面露出于该第一封装体的该第一表面且与该第一封装体的该第一表面实质上对齐。
65.如权利要求64所述的半导体封装件,其中该些电性接垫设置在该些导电柱的端面上,并电性连接该些导电柱。
66.如权利要求65所述的半导体封装件,其中该些电性接垫覆盖该些导电柱的端面的至少一部分。
67.如权利要求65所述的半导体封装件,其中该些电性接垫的面积大于该些导电柱的端面的面积。
68.如权利要求47所述的半导体封装件,还包括:
第二表面处理层,设置在该些电性接垫上。
69.如权利要求47所述的半导体封装件,还包括:
余留部,该余留部与该些电性接垫相连并朝该第一封装体的该第一表面延伸。
70.如权利要求69所述的半导体封装件,其中该余留部包括籽晶层及子导电层。
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US20160118349A1 (en) | 2016-04-28 |
CN102299082B (zh) | 2014-04-16 |
TW201209983A (en) | 2012-03-01 |
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US9219027B2 (en) | 2015-12-22 |
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US20120058604A1 (en) | 2012-03-08 |
US8709874B2 (en) | 2014-04-29 |
CN103824836A (zh) | 2014-05-28 |
US20140167240A1 (en) | 2014-06-19 |
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US9583449B2 (en) | 2017-02-28 |
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