WO2018113573A1 - 一种具有低电阻损耗三维封装结构及其工艺方法 - Google Patents

一种具有低电阻损耗三维封装结构及其工艺方法 Download PDF

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WO2018113573A1
WO2018113573A1 PCT/CN2017/116046 CN2017116046W WO2018113573A1 WO 2018113573 A1 WO2018113573 A1 WO 2018113573A1 CN 2017116046 W CN2017116046 W CN 2017116046W WO 2018113573 A1 WO2018113573 A1 WO 2018113573A1
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metal
power device
electroplating
circuit layer
molding compound
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PCT/CN2017/116046
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English (en)
French (fr)
Inventor
林煜斌
沈锦新
梁新夫
孔海申
周青云
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江苏长电科技股份有限公司
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Publication of WO2018113573A1 publication Critical patent/WO2018113573A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/117—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Definitions

  • the invention relates to a three-dimensional package structure with low resistance loss and a processing method thereof, and belongs to the technical field of semiconductor packaging.
  • power devices are an important application field.
  • the so-called power devices control the operation of power electronic devices by integrating the working mode of electric power, and use power electronic devices to provide high-power output.
  • Power devices usually work at high voltage. Under the condition of high current, it generally has the characteristics of high withstand voltage, large working current and large power dissipation.
  • the power device is electrically connected to the substrate by soldering, so this requires metallization of the back surface of the power device to make the contact electrode portion have good electrical contact and increase heat dissipation performance.
  • Back metallization is power device manufacturing.
  • the very important technology in the process its quality has high requirements for reliability, and its process requirements are also quite complicated.
  • the material selection of back metal plating should consider the adhesion with silicon, if the adhesion is not good, the formation There are many contact holes and holes, the bonding mechanical strength is not enough, and the contact thermal resistance at the interface is increased.
  • the thermal matching between the wafer, the solder of the wafer and the layers of the underlying layer must be considered, that is, the materials of each layer need to be ensured.
  • the coefficient of thermal expansion between them is similar. If the difference in thermal expansion coefficient is large, a gap is easily formed between the back plating metal layer and the silicon layer, thereby reducing the reliability performance.
  • the processing process is more difficult, and the problem of wafer cracking is likely to occur during the process, thereby reducing the production yield.
  • the technical problem to be solved by the present invention is to provide a three-dimensional package structure with low resistance loss and a process method thereof for the above prior art, which eliminates the process steps of back metal plating when the power device is fabricated, saves the chip cost, and adopts the first package.
  • the post-etching process buryes the power device inside the substrate, increasing the integration degree of the entire package structure, and directly plating the metal on the surface of the power device for electrical connection in the process, thereby reducing the resistance loss.
  • the technical solution adopted by the present invention to solve the above problems is: a process method having a low resistance loss three-dimensional package structure, the method comprising the following steps:
  • Step one take the metal carrier
  • Step 2 Pre-plating copper layer on the surface of the metal carrier
  • Step three plating metal external pins
  • the outer periphery of the metal outer lead is protected by an epoxy resin material, and the surface of the outer metal pin is exposed to the surface of the molding compound by surface grinding;
  • Step 5 plating the first metal circuit layer
  • Step six electroplating the first conductive metal column
  • Step seven the first power device placement
  • the first metal circuit layer, the first conductive metal pillar and the peripheral region of the first power device are plastically encapsulated by a molding compound, and the first conductive metal pillar and the back surface of the first power device are exposed to the surface of the molding compound by surface grinding;
  • Step 9 Electroplating the second metal circuit layer
  • Step ten electroplating the second conductive metal column
  • Step XI second power device placement
  • the second metal circuit layer, the second conductive metal pillar and the peripheral region of the second power device are plastically encapsulated by a molding compound, and the second conductive metal pillar and the back surface of the second power device are exposed to the surface of the molding compound by surface grinding;
  • Step 13 Electroplating the third metal circuit layer
  • the peripheral region of the third metal circuit layer is plastically sealed with a molding compound
  • Step fifteen carrier etching window
  • Step 16 Electroplating of anti-oxidation metal layer
  • Step 17 Cutting the finished product
  • Step 16 completes the cutting operation of the semi-finished product of the electroplated anti-oxidation metal layer, so that the plastic-molded modules originally integrated in the array assembly manner are cut one by one, and the finished product having the low resistance loss three-dimensional packaging structure is obtained.
  • the thickness of the copper layer in step two is 2 to 10 microns.
  • the copper layer is prepared in the second step by chemical deposition, electrodeposition or vapor deposition.
  • the material of the metal outer lead and the metal wiring layer is copper, aluminum or nickel, and the material of the oxidation resistant metal layer is gold, nickel gold, nickel palladium gold or tin.
  • the plastic sealing method adopts the mold filling method, the spraying equipment spraying method, the film coating method or the brushing method.
  • the etching method in the step 15 is an etching process using copper chloride or ferric chloride.
  • a three-dimensional package structure having a low resistance loss comprising a first metal circuit layer, a first conductive metal pillar and a first power device disposed on a front surface of the first metal circuit layer, and a metal disposed on a back surface of the first metal circuit layer
  • the outer lead, the outer peripheral surface of the metal outer lead encloses a pre-encapsulation material, and the first metal circuit layer, the first conductive metal post and the peripheral region of the first power device are encapsulated with a first molding compound
  • the first conductive metal pillar top and the first power device back surface expose the first molding compound, the first molding material surface is provided with a second metal wiring layer, and the first conductive metal pillar top and the first power device back surface pass a second metal circuit layer is connected, a second conductive metal pillar and a second power device are disposed on the second metal circuit layer, and the second metal circuit layer, the second conductive metal pillar and the second power device are peripherally encapsulated There is a second molding compound, and the surface of the
  • the power device used in the invention saves the process of plating metal on the back side when the chip is fabricated, and saves a complicated chip manufacturing process, which can improve the chip production yield and save the chip cost;
  • the packaging process of the present invention is to embed the power device in the substrate downward, and then electrically plate the metal layer on the back side of the power device to reduce the problem of cracking due to the thin thickness of the chip, and the metal.
  • the layer has high design freedom, can have lower resistance loss, and has simple manufacturing process and better heat dissipation performance;
  • the power device can be buried, or different types of components can be buried according to the function, thereby increasing the integration degree of the entire package.
  • 1 to 38 are schematic views of respective processes of a method for manufacturing a three-dimensional package structure with low resistance loss according to the present invention.
  • 39 is a schematic diagram of a three-dimensional package structure with low resistance loss according to the present invention.
  • a three-dimensional package structure having a low resistance loss in the embodiment includes a first metal wiring layer 7, and the first metal wiring layer 7 is provided with a first conductive metal pillar 9 and a first surface.
  • the power device 11, the back surface of the first metal circuit layer 7 is provided with a metal outer lead 4, and the peripheral portion of the metal outer lead 4 is encapsulated with a pre-encapsulation material 5, the first metal circuit layer 7, first
  • the conductive metal pillar 9 and the peripheral region of the first power device 11 are encapsulated with a first molding compound 10, the top end of the first conductive metal pillar 9 and the back surface of the first power device 11 exposing the first molding compound 10, the first molding compound 10 is provided with a second metal circuit layer 12, and a top end of the first conductive metal pillar 9 and a back surface of the first power device 11 are connected by a second metal circuit layer 12, and the second metal circuit layer 12 is provided with a second conductive metal pillar 15 and a second power device 14, the second metal wiring layer 12, the second conductive pillar
  • Step one take the metal carrier
  • a metal carrier of suitable thickness is taken.
  • the purpose of the plate is to provide support for the circuit fabrication and the circuit layer structure.
  • the material of the plate is mainly metal material, and the material of the metal material can be copper or iron. Material, stainless steel or other metal material with conductive function;
  • Step 2 Pre-plating copper layer on the surface of the metal carrier
  • a copper layer is pre-plated on the surface of the metal carrier, and the thickness of the copper layer is 2-10 micrometers, and the preparation method may be chemical deposition, electrodeposition or vapor deposition;
  • a photoresist material which can be exposed and developed is attached or printed on the front and back sides of the metal carrier of the pre-plated copper layer to protect the subsequent plating metal layer process, and the photoresist material on the surface of the metal carrier is exposed by the exposure developing device.
  • the photoresist material may be a photoresist film or a photoresist;
  • Step four plating metal outer pins
  • a metal outer pin is plated in a region where a part of the photoresist material is removed from the front surface of the metal carrier, and the metal outer lead material is usually copper, aluminum, nickel, etc., and may also be other conductive metal materials;
  • Step 5 removing the photoresist material
  • the photoresist film on the surface of the metal carrier is removed, and the photoresist film can be removed by chemical water softening and high pressure water rinsing;
  • the outer periphery of the metal outer lead of the metal carrier is protected by an epoxy resin material, and the epoxy resin material can be selected according to the product characteristics with or without a filler, and the plastic sealing method can adopt a mold filling method.
  • the surface of the epoxy resin is polished after the epoxy resin is sealed, so as to expose the outer tip of the metal to the surface of the molding body and control the thickness of the epoxy resin;
  • Step 8 Preparation of conductive layer on epoxy surface
  • the conductive layer is prepared on the surface of the polished epoxy resin;
  • the conductive layer may be a metal material such as nickel, titanium, copper, silver, etc., or a non-metallic conductive polymer material such as polyaniline or poly. Pyrrole, polythiophene, etc.; deposition methods are usually chemical deposition, vapor deposition, sputtering, etc.;
  • a photoresist material which can be exposed and developed is attached or printed on the front side of the metal carrier, and the photoresist material is exposed, developed and removed by an exposure developing device to expose the surface of the metal carrier.
  • the photoresist material may be a photoresist film or a photoresist;
  • Step ten electroplating the first metal circuit layer
  • a first metal circuit layer is plated in a region where a portion of the photoresist is removed from the front surface of the metal carrier in step 9.
  • the first metal circuit layer material is usually copper, aluminum, nickel, or the like, and may be other conductive metal materials.
  • a photoresist material which can be exposed and developed is attached or printed on the front side of the metal carrier in step 10, and the photoresist material is exposed, developed and removed by an exposure developing device to expose the surface of the metal carrier.
  • the photoresist material may be a photoresist film or a photoresist;
  • Step 12 Electroplating the first conductive metal column
  • a first conductive metal pillar is plated in a region of the front side of the metal carrier where a portion of the photoresist material is removed, and the first conductive metal pillar is used for conducting and connecting between the three-dimensional package structures;
  • Step 13 Remove the photoresist material
  • the photoresist film on the surface of the metal carrier is removed, and the photoresist film can be removed by chemical water softening and high pressure water rinsing;
  • Step fourteen fast etching
  • the conductive layer exposed on the front side of the metal carrier is removed
  • Step 15 First power device placement
  • a first power device and other required chips are mounted on the first metal circuit layer, and the first power device may be a control chip or a MOS chip;
  • the front side of the metal carrier in the fifteenth step is plastically sealed by a molding compound
  • the plastic sealing method may be a mold filling method, a compression potting method, a spraying method or a film coating method
  • the molding material may be a filler material or An epoxy resin without a filler
  • the surface of the epoxy resin is polished after the epoxy resin is sealed, so as to expose the first conductive metal column and the first power device tip to the surface of the molding body and control the thickness of the epoxy resin;
  • Step 18 Preparation of conductive layer on epoxy surface
  • the surface of the epoxy resin after the step 17 is prepared by conducting a conductive layer;
  • the conductive layer may be a metal material such as nickel, titanium, copper, silver, or the like, or a non-metal conductive polymer material such as poly.
  • a photoresist material capable of exposure development is attached or printed on the front surface of the metal carrier in step 18, and the photoresist material is exposed, developed, and removed by an exposure developing device to expose the surface of the metal carrier.
  • the pattern area of the second metal circuit layer plating is required, and the photoresist material may be a photoresist film or a photoresist;
  • Step 20 electroplating the second metal circuit layer
  • a second metal wiring layer is plated in a region where a portion of the photoresist is removed from the front surface of the metal carrier, and the first conductive metal pillar is connected to the top end of the first power device through the second metal wiring layer.
  • the circuit layer material is usually copper, aluminum, nickel, etc., and may also be other conductive metal materials;
  • a photoresist material which can be exposed and developed is attached or printed on the front side of the metal carrier in step twenty, and the photoresist material is exposed, developed and removed by an exposure developing device to expose the surface of the metal carrier.
  • the pattern area of the second conductive metal pillar plating is required, and the photoresist material may be a photoresist film or a photoresist;
  • Step 22 electroplating the second conductive metal column
  • a second conductive metal pillar is plated in a region where a portion of the photoresist is removed from the front surface of the metal carrier in step 21, and the second conductive metal pillar is used for conducting and connecting between the three-dimensional package structures;
  • Step 23 remove the photoresist material
  • the photoresist film on the surface of the metal carrier is removed, and the photoresist film can be removed by chemical water softening and high pressure water rinsing;
  • the conductive layer exposed on the front side of the metal carrier is removed
  • a second power device is mounted on the second metal circuit layer, and the second power device is a control chip or a MOS chip;
  • the front side of the metal carrier in step 25 is plastically sealed by a molding compound
  • the plastic sealing method may be a mold filling method, a compression potting method, a spraying method or a film coating method
  • the molding material may be a filler material. Or epoxy resin without filler material;
  • the surface of the epoxy resin is polished after the epoxy resin is sealed, so as to expose the second conductive metal pillar and the second power device tip to the surface of the molding body and control the thickness of the epoxy resin;
  • Step 28 Preparation of conductive layer on epoxy surface
  • the conductive layer is prepared on the surface of the epoxy resin after the step 27;
  • the conductive layer may be a metal substance such as nickel, titanium, copper, silver, etc., or a non-metal conductive polymer material, such as Polyaniline, polypyrrole, polythiophene, etc.; deposition methods are usually chemical deposition, vapor deposition, sputtering, etc.;
  • a photoresist material which can be exposed and developed is attached or printed on the front surface of the metal carrier in step 28, and the photoresist material is exposed, developed and removed by an exposure developing device to expose the metal carrier.
  • the surface needs a pattern area for plating the third metal circuit layer, and the photoresist material may be a photoresist film or a photoresist;
  • Step 30 Electroplating the third metal circuit layer
  • a third metal wiring layer is plated in a region where a portion of the photoresist is removed from the front surface of the metal carrier, and a second conductive metal pillar is connected to the top end of the second power device through the third metal wiring layer.
  • the metal circuit layer material is usually copper, aluminum, nickel, etc., and may also be other conductive metal materials;
  • Step 31 Removing the photoresist material
  • the photoresist film on the surface of the metal carrier can be removed by chemical softening and rinsed with high pressure water. Method of removing the photoresist film;
  • the conductive layer exposed on the front side of the metal carrier is removed
  • the front side of the metal carrier in step 32 is plastically sealed by a molding compound
  • the plastic sealing method may be a mold filling method, a compression filling method, a spraying method or a film coating method
  • the molding material may be a filler material. Or epoxy resin without filler material;
  • a photoresist material which can be exposed and developed is attached or printed on the back side of the metal carrier in step thirty-three, and the photoresist material is exposed, developed and removed by an exposure developing device to expose the metal carrier.
  • the pattern area where the surface needs to be etched, the photoresist material may be a photoresist film or a photoresist.
  • Step 35 Carrier etching window
  • a portion of the photoresist material is removed by chemical etching to open the window, and the etching method may be an etching process using copper chloride or ferric chloride;
  • Step 36 Remove the photoresist material
  • the photoresist film on the surface of the metal carrier is removed, and the photoresist film can be removed by chemical water softening and high pressure water rinsing;
  • Step 37 Electroplating anti-oxidation metal layer
  • the metal surface of the metal carrier is exposed to an outer surface of the metal for electroplating of an anti-oxidation metal layer, such as gold, nickel gold, nickel palladium gold, tin, or the like;
  • Step 38 Cutting the finished product
  • the semi-finished product of the electroplated anti-oxidation metal layer is cut in the thirty-seventh step, so that the plastic package modules originally integrated in the array assembly are cut one by one, and the low resistance loss is obtained.
  • the finished product of the three-dimensional package structure is cut in the thirty-seventh step, so that the plastic package modules originally integrated in the array assembly are cut one by one, and the low resistance loss is obtained.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

公开了一种具有低电阻损耗三维封装结构及其工艺方法，包括：取金属载体（2）；预镀铜层（1）；电镀金属外引脚（4）；塑封；电镀第一金属线路层（7）；电镀第一导电金属柱（9）；第一功率器件（11）贴装；塑封；电镀第二金属线路层（12）；电镀第二导电金属柱（15）；第二功率器件（14）贴装；塑封；电镀第三金属线路层（17）；塑封；载体蚀刻开窗；电镀抗氧化金属层（3）；切割成品。

Description

一种具有低电阻损耗三维封装结构及其工艺方法
本申请要求了申请日为2016年12月21日，申请号为201611192139.6，发明名称为“一种具有低电阻损耗三维封装结构及其工艺方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及一种具有低电阻损耗三维封装结构及其工艺方法，属于半导体封装技术领域。
背景技术
在集成电路当中，功率器件是一个重要的应用领域，所谓功率器件，就是通过集成电力的工作方式来控制功率电子器件的工作，利用功率电子器件来提供大功率输出，功率器件通常工作于高电压、大电流的条件下，普遍具备耐压高、工作电流大、自身耗散功率大等特点。一般来说，功率器件是通过焊接的方式电性连接至基板上，所以这就要求功率器件背面金属化来使接触电极部分有良好的电性接触以及增加散热性能，背面金属化是功率器件制造过程中非常重要的技术，其质量对可靠性有很高的要求，其工艺要求也相当复杂，首先背镀金属的材料选择要考虑与硅材的粘附性，如果粘附性不好，形成接触时空洞较多，粘结机械强度不够，增大了界面上的接触热阻；另外还需考虑晶圆、晶圆焊料与底层的各层之间的热匹配度，即需要保证各层材料之间的热膨胀系数要相近，若热膨胀系数差异较大，则背镀金属层和硅层之间容易形成缝隙，降低其可靠性能。尤其对于尺寸大而厚度薄的晶圆来说加工制程更加困难，在制程中很容易出现晶圆破裂的问题，从而降低生产良率。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种具有低电阻损耗三维封装结构及其工艺方法，功率器件制作的时候省去背镀金属的工艺步骤，节省芯片成本，并且采用先封装后蚀刻工艺流程，将功率器件埋入基板内部，增加整个封装结构的集成度，制程中在功率器件表面直接电镀金属进行电性连接，可降低电阻损耗。
本发明解决上述问题所采用的技术方案为：一种具有低电阻损耗三维封装结构的工艺方法，所述方法包括以下步骤：
步骤一、取金属载体
步骤二、金属载体表面预镀铜层
步骤三、电镀金属外引脚
在金属载体正面通过电镀形成金属外引脚；
步骤四、环氧树脂塑封
在金属外引脚外围区域利用环氧树脂材料进行塑封保护，并通过表面研磨使金属外引脚顶端露出塑封料表面；
步骤五、电镀第一金属线路层
在步骤四的塑封料表面通过电镀形成第一金属线路层；
步骤六、电镀第一导电金属柱
在步骤五的第一金属线路层上通过电镀形成第一导电金属柱；
步骤七、第一功率器件贴装
在第一金属线路层上贴装第一功率器件；
步骤八、塑封
将第一金属线路层、第一导电金属柱和第一功率器件外围区域采用塑封料进行塑封，并通过表面研磨使第一导电金属柱和第一功率器件背面露出塑封料表面；
步骤九、电镀第二金属线路层
在步骤八的塑封料表面通过电镀形成第二金属线路层，通过第二金属线路层将第一导电金属柱和第一功率器件背面相连接；
步骤十、电镀第二导电金属柱
在步骤九的第二金属线路层上通过电镀形成第二导电金属柱；
步骤十一、第二功率器件贴装
在第二金属线路层上贴装第二功率器件；
步骤十二、塑封
将第二金属线路层、第二导电金属柱和第二功率器件外围区域采用塑封料进行塑封，并通过表面研磨使第二导电金属柱和第二功率器件背面露出塑封料表面；
步骤十三、电镀第三金属线路层
在步骤十二的塑封料表面通过电镀形成第三金属线路层，通过第三金属线路层将第二导电金属柱和第二功率器件背面相连接；
步骤十四、塑封
将第三金属线路层外围区域采用塑封料进行塑封；
步骤十五、载体蚀刻开窗
在金属载体背面进行蚀刻开窗，使金属外引脚背面露出；
步骤十六、电镀抗氧化金属层
在露出的金属外引脚背面通过电镀形成抗氧化金属层；
步骤十七、切割成品
将步骤十六完成电镀抗氧化金属层的半成品进行切割作业，使原本以阵列式集合体方式集成在一起的塑封体模块一颗颗切割独立开来，制得具有低电阻损耗三维封装结构成品。
步骤二中的铜层厚度在2～10微米。
步骤二中铜层的制备方式是化学沉积、电沉积或者气相沉积。
所述金属外引脚和金属线路层的材料是铜、铝或镍，所述抗氧化金属层的材料采用金、镍金、镍钯金或锡。
塑封方式采用模具灌胶方式、喷涂设备喷涂方式、贴膜方式或是刷胶的方式。
步骤十五中的蚀刻方法采用氯化铜或者氯化铁的蚀刻工艺。
一种具有低电阻损耗三维封装结构，它包括第一金属线路层，所述第一金属线路层正面设置有第一导电金属柱和第一功率器件，所述第一金属线路层背面设置有金属外引脚，所述金属外引脚外围区域包封有预包封料，所述第一金属线路层、第一导电金属柱和第一功率器件外围区域包封有第一塑封料，所述第一导电金属柱顶端和第一功率器件背面露出第一塑封料，所述第一塑封料表面设置有第二金属线路层，所述第一导电金属柱顶端和第一功率器件背面之间通过第二金属线路层相连接，所述第二金属线路层上设置有第二导电金属柱和第二功率器件，所述第二金属线路层、第二导电金属柱和第二功率器件外围包封有第二塑封料，所述第二塑封料表面设置有第三金属线路层，所述第三金属线路层外围包封有第三塑封料。
与现有技术相比，本发明的优点在于：
1、本发明中所使用的功率器件在芯片制作的时候省去背面电镀金属的工艺制程，省去一道复杂的芯片制作工艺，可以提高芯片生产良率，节省芯片成本；
2、本发明的封装工艺方法是将功率器件朝下埋入基板内，然后在功率器件背面电镀金属层来进行电性连接，这样可以减少因为芯片厚度过薄而导致的破裂的问题，而且金属层的设计自由度高，可具有较低电阻损耗，且制作工艺简单，散热性能也比较好；
3、本发明的封装工艺方法中可以将功率器件埋入，也可以根据功能需要埋入不同类型的元器件，增加整个封装的集成度。
附图说明
图1～图38为本发明一种具有低电阻损耗三维封装结构工艺方法的各工序示意图。
图39为本发明一种具有低电阻损耗三维封装结构的示意图。
其中：
铜层1
金属载体2
抗氧化层3
金属外引脚4
预包封料5
导电层6
第一金属线路层7
第一金属凸点8
第一导电金属柱9
第一塑封料10
第一功率器件11
第二金属线路层12
第二金属凸点13
第二功率器件14
第二导电金属柱15
第二塑封料16
第三金属线路层17
第三塑封料18。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
如图39所示，本实施例中的一种具有低电阻损耗三维封装结构，它包括第一金属线路层7，所述第一金属线路层7正面设置有第一导电金属柱9和第一功率器件11，所述第一金属线路层7背面设置有金属外引脚4，所述金属外引脚4外围区域包封有预包封料5，所述第一金属线路层7、第一导电金属柱9和第一功率器件11外围区域包封有第一塑封料10，所述第一导电金属柱9顶端和第一功率器件11背面露出第一塑封料10，所述第一塑封料10表面设置有第二金属线路层12，所述第一导电金属柱9顶端和第一功率器件11背面之间通过第二金属线路层12相连接，所述第二金属线路层12上设置有第二导电金属柱15和第二功率器件14，所述第二金属线路层12、第二导电金属柱15和第二功率器件14外围包封有第二塑封料16，所述第二塑封料16表面设置有第三金属线路层17，所述第三金属线路层17外围包封有第三塑封料18。
其工艺方法如下：
步骤一、取金属载体
参见图1，取一片厚度合适的金属载体，此板材使用的目的是为线路制作及线路层结构提供支撑，此板材的材质主要以金属材料为主，而金属材料的材质可以是铜材，铁材，不锈钢材或其它具有可导电功能的金属物质；
步骤二、金属载体表面预镀铜层
参见图2，在金属载体表面预镀铜层，铜层厚度在2～10微米，制备方式可以是化学沉积、电沉积或者气相沉积；
步骤三、光刻作业
参见图3，在预镀铜层的金属载体正面及背面贴覆或印刷可进行曝光显影的光阻材料，以保护后续电镀金属层工艺作业，并利用曝光显影设备对金属载体表面的光阻材料进行曝光、显影与去除部分光阻材料，以露出金属载体表面需要进行金属外引脚电镀的图形区域，光阻材料可以是光阻膜，也可以是光刻胶；
步骤四、电镀金属外引脚
参见图4，在步骤四中金属载体正面去除部分光阻材料的区域内电镀上金属外引脚，金属外引脚材料通常是铜、铝、镍等，也可以是其它导电金属物质；
步骤五、去除光阻材料
参见图5，去除金属载体表面的光阻膜，可以采用化学药水软化并采用高压水冲洗的方法去除光阻膜；
步骤六、环氧树脂塑封
参见图6，在金属载体正面的金属外引脚外围区域利用环氧树脂材料进行塑封保护，环氧树脂材料可以依据产品特性选择有填料或者没有填料的种类，塑封方式可以采用模具灌胶方式、喷涂设备喷涂方式、贴膜方式或是刷胶的方式；
步骤七、表面研磨
参见图7，在完成环氧树脂塑封后进行环氧树脂表面研磨，目的是使金属外引脚顶端露出塑封体表面以及控制环氧树脂的厚度；
步骤八、环氧树脂表面导电层制备
参见图8，在研磨后的环氧树脂表面进行导电层制备；导电层可以是金属类物质，如镍、钛、铜、银等，也可以使非金属导电高分子材料，如聚苯胺、聚吡咯、聚噻吩等；沉积方式通常为化学沉积、气相沉积、溅射等；
步骤九、光刻作业
参见图9，在步骤八金属载体正面贴覆或印刷可进行曝光显影的光阻材料，并利用曝光显影设备对光阻材料进行曝光、显影与去除部分光阻材料，以露出金属载体表面需要进行第一金属线路层电镀的图形区域，光阻材料可以是光阻膜，也可以是光刻胶；
步骤十、电镀第一金属线路层
参见图10，在步骤九中金属载体正面去除部分光阻材料的区域内电镀上第一金属线路层，第一金属线路层材料通常是铜、铝、镍等，也可以是其它导电金属物质；
步骤十一、光刻作业
参见图11，在步骤十金属载体正面贴覆或印刷可进行曝光显影的光阻材料，并利用曝光显影设备对光阻材料进行曝光、显影与去除部分光阻材料，以露出金属载体表面需 要进行第一导电金属柱电镀的图形区域，光阻材料可以是光阻膜，也可以是光刻胶；
步骤十二、电镀第一导电金属柱
参见图12，在步骤十一中金属载体正面去除部分光阻材料的区域内电镀第一导电金属柱，该第一导电金属柱用于三维封装结构之间的导通及连接；
步骤十三、去除光阻材料
参见图13，去除金属载体表面的光阻膜，可以采用化学药水软化并采用高压水冲洗的方法去除光阻膜；
步骤十四、快速蚀刻
参见图14，去除金属载体正面露出的导电层；
步骤十五、第一功率器件贴装
参见图15，在第一金属线路层上贴装第一功率器件以及其他所需的芯片，第一功率器件可为控制芯片或MOS芯片；
步骤十六、塑封
参见图16，将步骤十五中的金属载体正面采用塑封料进行塑封，塑封方式可以采用模具灌胶方式、压缩灌胶、喷涂方式或是用贴膜方式，所述塑封料可以采用有填料物质或是无填料物质的环氧树脂；
步骤十七、表面研磨
参见图17，在完成环氧树脂塑封后进行环氧树脂表面研磨，目的是使第一导电金属柱和第一功率器件顶端露出塑封体表面以及控制环氧树脂的厚度；
步骤十八、环氧树脂表面导电层制备
参见图17，在步骤十七研磨后的环氧树脂表面进行导电层制备；导电层可以是金属类物质，如镍、钛、铜、银等，也可以使非金属导电高分子材料，如聚苯胺、聚吡咯、聚噻吩等；沉积方式通常为化学沉积、气相沉积、溅射等；
步骤十九、光刻作业
参见图19，在步骤十八的金属载体正面贴覆或印刷可进行曝光显影的光阻材料，并利用曝光显影设备对光阻材料进行曝光、显影与去除部分光阻材料，以露出金属载体表面需要进行第二金属线路层电镀的图形区域，光阻材料可以是光阻膜，也可以是光刻胶；
步骤二十、电镀第二金属线路层
参见图20，在步骤十九中金属载体正面去除部分光阻材料的区域内电镀上第二金属线路层，通过第二金属线路层将第一导电金属柱和第一功率器件顶端相连接，金属线路层材料通常是铜、铝、镍等，也可以是其它导电金属物质；
步骤二十一、光刻作业
参见图21，在步骤二十金属载体正面贴覆或印刷可进行曝光显影的光阻材料，并利用曝光显影设备对光阻材料进行曝光、显影与去除部分光阻材料，以露出金属载体表面 需要进行第二导电金属柱电镀的图形区域，光阻材料可以是光阻膜，也可以是光刻胶；
步骤二十二、电镀第二导电金属柱
参见图22，在步骤二十一中金属载体正面去除部分光阻材料的区域内电镀第二导电金属柱，该第二导电金属柱用于三维封装结构之间的导通及连接；
步骤二十三、去除光阻材料
参见图23，去除金属载体表面的光阻膜，可以采用化学药水软化并采用高压水冲洗的方法去除光阻膜；
步骤二十四、快速蚀刻
参见图24，去除金属载体正面露出的导电层；
步骤二十五、第二功率器件贴装
参见图25，在第二金属线路层上贴装第二功率器件，第二功率器件为控制芯片或MOS芯片；
步骤二十六、塑封
参见图26，将步骤二十五中的金属载体正面采用塑封料进行塑封，塑封方式可以采用模具灌胶方式、压缩灌胶、喷涂方式或是用贴膜方式，所述塑封料可以采用有填料物质或是无填料物质的环氧树脂；
步骤二十七、表面研磨
参见图27，在完成环氧树脂塑封后进行环氧树脂表面研磨，目的是使第二导电金属柱和第二功率器件顶端露出塑封体表面以及控制环氧树脂的厚度；
步骤二十八、环氧树脂表面导电层制备
参见图27，在步骤二十七研磨后的环氧树脂表面进行导电层制备；导电层可以是金属类物质，如镍、钛、铜、银等，也可以使非金属导电高分子材料，如聚苯胺、聚吡咯、聚噻吩等；沉积方式通常为化学沉积、气相沉积、溅射等；
步骤二十九、光刻作业
参见图29，在步骤二十八的金属载体正面贴覆或印刷可进行曝光显影的光阻材料，并利用曝光显影设备对光阻材料进行曝光、显影与去除部分光阻材料，以露出金属载体表面需要进行第三金属线路层电镀的图形区域，光阻材料可以是光阻膜，也可以是光刻胶；
步骤三十、电镀第三金属线路层
参见图30，在步骤二十九中金属载体正面去除部分光阻材料的区域内电镀上第三金属线路层，通过第三金属线路层将第二导电金属柱和第二功率器件顶端相连接，金属线路层材料通常是铜、铝、镍等，也可以是其它导电金属物质；
步骤三十一、去除光阻材料
参见图31，去除金属载体表面的光阻膜，可以采用化学药水软化并采用高压水冲洗 的方法去除光阻膜；
步骤三十二、快速蚀刻
参见图32，去除金属载体正面露出的导电层；
步骤三十三、塑封
参见图33，将步骤三十二中的金属载体正面采用塑封料进行塑封，塑封方式可以采用模具灌胶方式、压缩灌胶、喷涂方式或是用贴膜方式，所述塑封料可以采用有填料物质或是无填料物质的环氧树脂；
步骤三十四、光刻作业
参见图34，在步骤三十三的金属载体背面贴覆或印刷可进行曝光显影的光阻材料，并利用曝光显影设备对光阻材料进行曝光、显影与去除部分光阻材料，以露出金属载体表面需要进行蚀刻的图形区域，光阻材料可以是光阻膜，也可以是光刻胶。
步骤三十五、载体蚀刻开窗
参见图35，在步骤三十四中金属载体背面去除部分光阻材料的区域进行化学蚀刻开窗，蚀刻方法可以采用氯化铜或者氯化铁的蚀刻工艺；
步骤三十六、去除光阻材料
参见图36，去除金属载体表面的光阻膜，可以采用化学药水软化并采用高压水冲洗的方法去除光阻膜；
步骤三十七、电镀抗氧化金属层
参见图37，在步骤三十六中去除光阻材料后，金属载体表面裸露在外的金属表面进行抗氧化金属层电镀，如金、镍金、镍钯金、锡等；
步骤三十八、切割成品
参见图38，将步骤三十七完成电镀抗氧化金属层的半成品进行切割作业，使原本以阵列式集合体方式集成在一起的塑封体模块一颗颗切割独立开来，制得具有低电阻损耗三维封装结构成品。
除上述实施例外，本发明还包括有其他实施方式，凡采用等同变换或者等效替换方式形成的技术方案，均应落入本发明权利要求的保护范围之内。

Claims (2)

  1. 一种具有低电阻损耗三维封装结构的工艺方法，其特征在于所述方法包括以下步骤：
    步骤一、取金属载体
    步骤二、金属载体表面预镀铜层
    步骤三、电镀金属外引脚
    在金属载体正面通过电镀形成金属外引脚；
    步骤四、环氧树脂塑封
    在金属外引脚外围区域利用环氧树脂材料进行塑封保护，并通过表面研磨使金属外引脚顶端露出塑封料表面；
    步骤五、电镀第一金属线路层
    在步骤四的塑封料表面通过电镀形成第一金属线路层；
    步骤六、电镀第一导电金属柱
    在步骤五的第一金属线路层上通过电镀形成第一导电金属柱；
    步骤七、第一功率器件贴装
    在第一金属线路层上贴装第一功率器件；
    步骤八、塑封
    将第一金属线路层、第一导电金属柱和第一功率器件外围区域采用塑封料进行塑封，并通过表面研磨使第一导电金属柱和第一功率器件背面露出塑封料表面；
    步骤九、电镀第二金属线路层
    在步骤八的塑封料表面通过电镀形成第二金属线路层，通过第二金属线路层将第一导电金属柱和第一功率器件背面相连接；
    步骤十、电镀第二导电金属柱
    在步骤九的第二金属线路层上通过电镀形成第二导电金属柱；
    步骤十一、第二功率器件贴装
    在第二金属线路层上贴装第二功率器件；
    步骤十二、塑封
    将第二金属线路层、第二导电金属柱和第二功率器件外围区域采用塑封料进行塑封，并通过表面研磨使第二导电金属柱和第二功率器件背面露出塑封料表面；
    步骤十三、电镀第三金属线路层
    在步骤十二的塑封料表面通过电镀形成第三金属线路层，通过第三金属线路层将第二导电金属柱和第二功率器件背面相连接；
    步骤十四、塑封
    将第三金属线路层外围区域采用塑封料进行塑封；
    步骤十五、载体蚀刻开窗
    在金属载体背面进行蚀刻开窗，使金属外引脚背面露出；
    步骤十六、电镀抗氧化金属层
    在露出的金属外引脚背面通过电镀形成抗氧化金属层；
    步骤十七、切割成品
    将步骤十六完成电镀抗氧化金属层的半成品进行切割作业，使原本以阵列式集合体方式集成在一起的塑封体模块一颗颗切割独立开来，制得具有低电阻损耗三维封装结构成品。
  2. 一种具有低电阻损耗三维封装结构，其特征在于：它包括第一金属线路层(7)，所述第一金属线路层(7)正面设置有第一导电金属柱(9)和第一功率器件(11)，所述第一金属线路层(7)背面设置有金属外引脚(4)，所述金属外引脚(4)外围区域包封有预包封料(5)，所述第一金属线路层(7)、第一导电金属柱(9)和第一功率器件(11)外围区域包封有第一塑封料(10)，所述第一导电金属柱(9)顶端和第一功率器件(11)背面露出第一塑封料(10)，所述第一塑封料(10)表面设置有第二金属线路层(12)，所述第一导电金属柱(9)顶端和第一功率器件(11)背面之间通过第二金属线路层(12)相连接，所述第二金属线路层(12)上设置有第二导电金属柱(15)和第二功率器件(14)，所述第二金属线路层(12)、第二导电金属柱(15)和第二功率器件(14)外围包封有第二塑封料(16)，所述第二塑封料(16)表面设置有第三金属线路层(17)，所述第三金属线路层(17)外围包封有第三塑封料(18)。
PCT/CN2017/116046 2016-12-21 2017-12-14 一种具有低电阻损耗三维封装结构及其工艺方法 WO2018113573A1 (zh)

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