CN102299082A - 半导体承载元件的制造方法及应用其的封装件的制造方法 - Google Patents

半导体承载元件的制造方法及应用其的封装件的制造方法 Download PDF

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Publication number
CN102299082A
CN102299082A CN2011102559149A CN201110255914A CN102299082A CN 102299082 A CN102299082 A CN 102299082A CN 2011102559149 A CN2011102559149 A CN 2011102559149A CN 201110255914 A CN201110255914 A CN 201110255914A CN 102299082 A CN102299082 A CN 102299082A
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layer
manufacture method
guide pillar
packaging body
support plate
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CN102299082B (zh
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周辉星
林建福
欧菲索
林少雄
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Advanpack Solutions Pte Ltd
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Advanpack Solutions Pte Ltd
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Abstract

本发明公开一种半导体承载元件的制造方法及应用其的封装件的制造方法。半导体承载元件的制造方法包括以下步骤。首先，提供电性载板，电性载板具有相对的第一面与第二面。然后，形成导线层于电性载板的第二面。然后，形成导柱层于导线层上。然后，形成封装体包覆导线层及导柱层。然后，露出导柱层的一端。然后，形成电镀导电层完全地包覆电性载板、封装体及导柱层的该端。然后，形成缺口于电性载板，其中导线层及封装体从缺口露出。然后，形成表面处理层于露出的导柱层的至少一部分上。然后，移除电镀导电层。

Description

半导体承载元件的制造方法及应用其的封装件的制造方法
技术领域
本发明涉及一种半导体承载元件的制造方法及应用其的半导体封装件的制造方法，且特别是涉及一种具有缺口的半导体承载元件的制造方法及应用其的半导体封装件的制造方法。 
背景技术
传统的半导体结构包括基板、芯片及焊线。基板例如是塑胶或陶瓷基板，其用以承载芯片。基板具有相对的第一面与第二面且包括接垫及导通贯孔。芯片设于基板的第一面上，焊线连接芯片与位于基板的第一面上的接垫。基板的接垫通过导通贯孔电连接于基板的第二面。 
然而，由于导通贯孔贯穿基板，因此降低基板的结构强度。且，由于导通贯孔降低基板的结构强度，为了不使基板的结构强度过低，导通贯孔相距基板的外侧面一较大距离，用于提升基板的结构强度至一正常范围，但如此将导致半导体封装件的尺寸无法缩小。此外，基板的厚度一般也较厚，使半导体封装件的厚度无法缩小。 
发明内容
本发明的目的在于提供一种半导体承载元件的制造方法及应用其的半导体封装件的制造方法，半导体承载元件的封装体包覆导柱层，导柱层电连接半导体承载元件的相对两侧，由于封装体的厚度较薄，可有效缩小半导体封装件的尺寸。 
为达上述目的，根据本发明的第一方面，提出一种半导体承载元件的制造方法。半导体承载元件的制造方法包括以下步骤。提供一电性载板，电性载板具有相对的一第一面与一第二面；形成一导线层于电性载板的第二面；形成一导柱层于导线层上；形成一第一封装体包覆导线层及导柱层；露出导柱层的一端；形成一电镀导电层完全地包覆电性载板、第一封装体及露出的 导柱层的该端；形成一缺口于电性载板，其中导线层及第一封装体从缺口露出；形成一第一表面处理层于露出的导线层的至少一部分上；以及，移除电镀导电层。 
根据本发明的第二方面，提出一种半导体承载元件的制造方法。半导体承载元件的制造方法包括以下步骤。提供一封装体，封装体具有一第一封装表面与一第二封装表面，封装体包覆多个导线层，导线层从第一封装表面延伸至第二封装表面且包括多个走线，该些走线相互隔离；形成一电镀导电层于第二封装表面及露出于第二封装表面的走线上，电镀导电层电连接走线；使用电镀方法，一次形成一表面处理层于露出于第一封装表面的走线的至少一部分上；以及，完全移除电镀导电层，露出第二封装表面。 
根据本发明的第三方面，提出一种半导体封装件的制造方法。半导体封装件的制造方法包括以下步骤。供一电性载板，电性载板具有相对的一第一面与一第二面；形成一导线层于电性载板的第二面；形成一导柱层于导线层上；形成一第一封装体包覆导线层及导柱层；露出导柱层的一端；形成一电镀导电层完全地包覆电性载板、第一封装体及露出的导柱层的该端；形成一缺口于电性载板，其中导线层及第一封装体从缺口露出；形成一第一表面处理层于露出的导线层的至少一部分上；移除电镀导电层；邻近导线层设置至少一半导体元件；形成一第二封装体包覆半导体元件；以及，切割第二封装体及第一封装体。 
为了对本发明的上述及其他方面有更佳的了解，下文特举实施例，并配合所附附图，作详细说明如下： 
附图说明
图1为本发明一实施例的半导体封装件的制造方法流程图； 
图2A至图2M为本发明一实施例的半导体封装件的制造示意图； 
图3A至图3B为本发明另一实施例的半导体承载元件的制造过程图； 
图4为图2J中半导体承载元件的上视图； 
图5A为本发明另一实施例的半导体承载元件的剖视图； 
图5B为图5A中半导体承载元件的上视图。 
主要元件符号说明 
100：半导体封装件 
102：电性载板 
102a：第一面 
102b：第二面 
102c：侧面 
104、304：导线层 
104a：导线表面 
106、306：走线 
106a：走线表面 
108、308：芯片座 
108a：芯片座表面 
110：导电柱 
110a：一端 
110b：端面 
112：第一封装体 
112a：第一封装表面 
112b：封装侧面 
112c：第二封装表面 
114：电镀导电层 
114a：余留部 
116：缺口 
118a：第一表面处理层 
118b：第二表面处理层 
120、220、320：半导体承载元件 
132：电性接点 
134、334：电镀固环 
122、130：半导体元件 
122a：主动表面 
124：焊线 
126：第二封装体 
128：粘胶 
S102-S126：步骤 
具体实施方式
请参照图1及图2A至图2M，图1绘示依照本发明一实施例的半导体封装件的制造方法流程图，图2A至图2M绘示依照本发明一实施例的半导体封装件的制造示意图。 
在步骤S102中，如图2A所示，提供一电性载板102。其中，电性载板102具有相对的第一面102a与第二面102b。电性载板102可以是金属板(plate)，例如是铜、铁或钢板。 
在步骤S104中，如图2B所示，应用例如是光刻制作工艺(photolithography)技术及电镀技术(electrolytic plating)，形成一导线层104于电性载板102的第二面102b。其中，导线层104例如是图案化导线层，其包括至少一走线106及至少一芯片座108。导线层104的材质可以是金属，例如是铜。
在步骤S106中，如图2C所示，应用例如是光刻制作工艺(photolithography)技术及电镀方法(electrolytic plating)，形成一导柱层于导线层104上。其中，导柱层包括至少一导电柱110，其形成于对应的走线106及芯片座108上。导电柱110的材质可以是金属，例如是铜。 
在步骤S108中，如图2D所示，应用例如是转注成型(transfer molding)的封装技术，形成一第一封装体112包覆导线层104及导柱层且覆盖第二面102b。本实施例中，第一封装体112以导线层104及导柱层做为封装对像。第一封装体112的材质可包括酚醛基树脂(novolac-based resin)、环氧基树脂(epoxy-based resin)、硅基树脂(silicone-based resin)或其他适当的包覆剂，在高温和高压下，以液体状态包覆导线层104及导柱层，其固化后形成第一封装体112。第一封装体112也可包括适当的填充剂，例如是粉状的二氧化硅。 
形成第一封装体112的步骤大致如下：提供一包覆剂，其中包覆剂包括树脂及粉状的二氧化硅；然后，加热包覆剂至液体状态；注入包覆剂于电性载板102的第二面102b上，包覆剂在高温和高压下包覆导线层104及导柱层(包括至少一导电柱110)；然后，固化包覆剂形成第一封装体112。 
在其他实施态样中，也可应用注射成型(injection molding)或压缩成型 (compression molding)形成第一封装体112。 
较佳但非限定地，在形成第一封装体112前，可形成一粘附层(未绘示)于导线层104的表面及导柱层的表面，加强与第一封装体112的黏力，提高可靠性。 
在步骤S110中，如图2E所示，应用例如是磨削(grinding)方式，移除第一封装体112的一部分，以露出导电柱110的一端110a的端面110b。第一封装体112被磨削后露出一第一封装表面112a，导电柱110被磨削后露出端面110b，较佳但非限定地，导电柱110的端面110b与第一封装表面112a实质上对齐，例如是共面。在其他实施态样中，可在形成第一封装体112的同时，露出导电柱110的一端110a的端面110b，而无需移除第一封装体112的任何部分。 
在步骤S112中，如图2F所示，形成一电镀导电层114完全地包覆电性载板102、第一封装体112及露出的导电柱110的该端110a。例如，应用例如是无电镀法(electroless plating)，形成电镀导电层114完全地包覆电性载板102的整个第一面102a、整个侧面102c及露出的第二面102b、第一封装体112的第一封装表面112a及封装侧面112b以及露出的导电柱110的该端110a。在本步骤S112中，电镀导电层114的厚度大约介于6μm至10μm之间。此外，电镀导电层114例如是单层的铜(Cu)层或其他种类的金属层。 
此外，电镀导电层114也可为多层金属层。例如，在另一实施态样中，步骤S112还包括以下两个步骤：首先，应用无电镀法(electroless plating)，形成一籽晶层(seed layer也称种子层)(未绘示)完全地包覆电性载板102、第一封装体112及露出的导电柱110的该端110a。该籽晶层的包覆范围相似于上述电镀导电层114的包覆范围；然后，应用电镀方法(electrolytic plating)，形成一子导电层完全地包覆该籽晶层。其中，该子导电层例如是铜层或其他种类的金属层。上述籽晶层的厚度例如是介于约1μm至2μm之间，而上述子导电层的厚度例如是介于约5μm至8μm之间。 
在步骤S114中，如图2G所示，形成至少一缺口116，其中，导线层104及第一封装体112从缺口116露出。例如，应用光刻制作工艺或蚀刻技术，移除电性载板102的一部分，以形成缺口116贯穿电镀导电层114的一部分及电性载板102的一部分。导线层104的导线表面104a及第一封装体112的第二封装表面112c从缺口116露出，其中，导线表面104a及第二封装表 面112c相对于第一封装表面112a。芯片座108具有芯片座表面108a，走线106具有走线表面106a，芯片座表面108a与走线表面106a定义上述导线表面104a。较佳但非限定地，如以蚀刻技术移除部分电性载板102，则导线层104更可包括一蚀刻阻挡层(未绘示)，其介于电性载板102与导线层104之间。蚀刻阻挡层的材质例如是镍(Ni)与金(Au)中至少一者。 
在部分的电性载板102后，电性载板102的余留部可形成一电镀固环134，其环绕第一封装体112的周边。电镀固环134通过电镀导电层114电连接于导电柱110和导线层104。 
在步骤S116中，如图2H所示，形成第一表面处理层(first surface finishing)118a于露出的导线层104上。例如，应用电镀技术形成第一表面处理层118a于导线层104中从缺口116露出的整个导线表面104a。 
其他实施态样中，可应用例如是光刻制作工艺，形成第一表面处理层118a于导线层104中从缺口116露出的部分导线表面104a上。例如，第一表面处理层118a仅形成于走线106的走线表面106a上，而不形成于芯片座108的芯片座表面108a上。又例如，第一表面处理层118a可仅形成于走线106的部分走线表面106a上。 
第一表面处理层118a的材质例如是镍(Ni)、钯(Pa)与金(Au)中至少一者，其可应用例如是电镀技术形成。 
由于步骤S114的电镀导电层114电性接触于导电柱110，使导线层104可通过导电柱110电连接于电镀导电层114。最外围的电镀固环134可与电镀设备的电极电连接，让电流通过电镀导电层114以电镀方法形成第一表面处理层118a于导线层104上。进一步地说，如图2H所示，虽然走线106与芯片座108被第一封装体112隔离(包括相邻两个走线之间)，然通过电镀导电层114电连接全部的导线层104，可在相同制作工艺中以电镀法一次形成第一表面处理层118a于全部的导线层104上。 
在步骤S118中，如图2I所示，应用例如是化学蚀刻(chemical etching)方法，移除全部的电镀导电层114，以露出导电柱110的一端110a的端面110b与第一封装表面112a。移除电镀导电层114后，导线层104的每一走线106及每一芯片座108相互隔离。 
在步骤S120中，如图2J所示，应用例如是无电镀法(electroless plating)，形成第二表面处理层(second surface finishing)118b于露出的导电柱110的 一端110a的端面110b上。至此，形成本实施例的半导体承载元件120。 
请参照图4，其绘示图2J中半导体承载元件的上视图。由图4可知，导线层104与电镀固环134被第一封装体112隔离，然此非用以限制本发明。在其他实施态样中，请参照图5A及图5B，图5A绘示依照本发明另一实施例的半导体承载元件的剖视图，图5B绘示图5A中半导体承载元件的上视图。半导体承载元件320的导线层304电连接于半导体承载元件320的电镀固环334，其中，每一走线306及每一芯片座308更相互连接并电性接触于电镀固环334。 
如图2J所示，电镀导电层114全部被移除，然此非用以限制本发明，以下举例说明。 
请参照图3A至图3B，其绘示依照本发明另一实施例的半导体承载元件的制造过程图。 
如图3A所示，电镀导电层114的一部分被移除而保留一余留部(remaining portion)114a，电镀导电层114的余留部114a至少覆盖导电柱110。在本实施例中，电镀导电层114的余留部114a覆盖导电柱110的整个端面110b及露出的第一封装体112的第一封装表面112a的一部分。进一步地说，电镀导电层114的余留部114a的面积大于导电柱110的端面110b的面积，以此较大面积的余留部114a作为电性接垫(bond pad)，有助于提升电性品质。在其他实施态样中，电镀导电层114的余留部114a可仅覆盖导电柱110的端面110b而不覆盖第一封装表面112a。 
如图3B所示，可应用例如是无电镀法(electroless plating)，形成第二表面处理层(second surface finishing)118b于电镀导电层114的余留部114a上。 
如图3B所示，余留部114a可于移除电镀导电层114的过程中同时形成。进一步地说，本实施例可不需额外制作工艺于导电柱110的端面110b上形成第二表面处理层118b，电镀导电层114的一部分被移除后，第二表面处理层118b即形成。至此，形成半导体承载元件220。另一实施例中，可对半导体承载元件220执行后续步骤S122至S126的制作工艺，以形成半导体封装件。 
在步骤S122中，如图2K所示，邻近导线层104设置至少一半导体元件122。例如，半导体元件122具有相对的背面与主动表面122a，半导体元件 122的背面设于粘胶128上，半导体元件122的主动表面122a朝上(face-up)并通过焊线124电性接触于走线106上的第一表面处理层118a，以电连接于走线106。此外，半导体元件130的主动面可朝下(face-down)设置且具有数个电性接点132，电性接点132电性接触于芯片座108与走线106中至少一者上的第一表面处理层118a。半导体元件130的种类例如是覆晶(flip-chip)。其他实施态样中，若没有第一表面处理层118a，则半导体元件130的电性接点132可直接电性接触于芯片座108与走线106中至少一者。 
在步骤S124中，如图2L所示，应用封装技术，形成第二封装体126包覆半导体元件122及焊线124。 
在步骤S126中，如图2M所示，以切割刀具或激光，切割第二封装体126及第一封装体112，以分离封装之后的半导体承载元件120。至此，形成半导体封装件100。 
本发明上述实施例的半导体承载元件的制造方法及应用其的半导体封装件的制造方法，半导体承载元件的封装体包覆导电柱，导电柱电连接半导体承载元件的相对两侧，由于封装体的厚度较薄，可有效缩小半导体封装件的尺寸。此外，此制造方法可用以形成电镀表面处理层于相互隔离的走线与芯片座，有助于提升产品的稳定性与可靠性。 
综上所述，虽然已结合以上实施例揭露了本发明，然而其并非用以限定本发明。本发明所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作各种的更动与润饰。因此，本发明的保护范围应以附上的权利要求所界定的为准。 

Claims (31)

1.一种半导体承载元件的制造方法，该制造方法包括：
提供一电性载板，该电性载板具有相对的一第一面与一第二面；
形成一导线层于该电性载板的该第二面；
形成一导柱层于该导线层上；
形成一第一封装体包覆该导线层及该导柱层；
露出该导柱层的一端；
形成一电镀导电层完全地包覆该电性载板、该第一封装体及露出的该导柱层的该端；
形成一缺口于该电性载板，其中该导线层及该第一封装体从该缺口露出；
形成一第一表面处理层于露出的该导线层的至少一部分上；以及
移除该电镀导电层。
2.如权利要求1所述的制造方法，其中在形成导线层于该电性载板的该第二面的该步骤中，该导线层包括一走线及一芯片座。
3.如权利要求2所述的制造方法，其中在形成导柱层于该导线层上的该步骤中，该导柱层包括：
导电柱，形成于对应的走线及对应的该芯片座上。
4.如权利要求2所述的制造方法，其中在移除该电镀导电层的该步骤之后，该走线及该芯片座相互隔离。
5.如权利要求1所述的制造方法，其中形成该第一封装体的该步骤包括：
提供一包覆剂，其中该包覆剂包括树脂及粉状的二氧化硅；
加热该包覆剂至液体状态；
注入呈液态的该包覆剂于该电性载板的该第二面上，该包覆剂在高温和高压下包覆该导线层及该导柱层；以及
固化该包覆剂，使该包覆剂形成该第一封装体。
6.如权利要求1所述的制造方法，其中在形成该第一封装体之前，该制造方法还包括：
形成一粘附层于该导线层及该导柱层上。
7.如权利要求1所述的制造方法，其中在露出该导柱层的该端的该步骤中包括：
以磨削方法移除该第一封装体的至少一部分。
8.如权利要求1所述的制造方法，其中在露出该导柱层的该端的该步骤中，该导柱层具有一端面，该第一封装体具有一封装表面，该导柱层的该端面与该封装表面露出且实质上对齐。
9.如权利要求1所述的制造方法，其中在形成该电镀导电层的该步骤中包括：
形成一籽晶层完全地包覆该电性载板、该第一封装体及露出的该导柱层的该端；以及
形成一子导电层完全地包覆该籽晶层。
10.如权利要求1所述的制造方法，其中形成该缺口于该电性载板的该步骤中包括：
移除该电性载板的一部分，其中，该电性载板的一余留部形成一电镀固环，该电镀固环环绕该第一封装体的周边。
11.如权利要求10所述的制造方法，其中于形成该电镀固环的该步骤中，该电镀固环通过该电镀导电层与该导柱层电性连于该导线层。
12.如权利要求1所述的制造方法，其中于形成该第一表面处理层的该步骤中包括：
使用电镀方法，通过该电镀导电层形成该第一表面处理层于露出的该导线层的至少一部分上。
13.如权利要求1所述的制造方法，其中于移除该电镀导电层的该步骤中，该导柱层的该端露出于该封装体的一封装表面。
14.如权利要求13所述的制造方法，其中于移除该电镀导电层的该步骤之后，该制造方法还包括：
形成一第二表面处理层于露出的该导柱层的该端的至少一部分上。
15.如权利要求1所述的制造方法，其中于移除该电镀导电层的该步骤中，该电镀导电层的一部分被移除，该电镀导电层的一余留部至少覆盖该导柱层的该端。
16.一种半导体承载元件的制造方法，该制造方法包括：
提供一封装体，该封装体具有一第一封装表面与一第二封装表面，该封装体包覆多个导线层，各该导线层从该第一封装表面延伸至该第二封装表面且包括多个走线，该些走线相互隔离；
形成一电镀导电层于该第二封装表面及露出于该第二封装表面的该些走线上，该电镀导电层电连接各该走线；
使用电镀方法，一次形成一表面处理层于露出于该第一封装表面的各该走线的至少一部分上；以及
完全移除该电镀导电层，露出该第二封装表面。
17.一种封装件的制造方法，包括：
提供一电性载板，该电性载板具有相对的一第一面与一第二面；
形成一导线层于该电性载板的该第二面；
形成一导柱层于该导线层上；
形成一第一封装体包覆该导线层及该导柱层；
露出该导柱层的一端；
形成一电镀导电层完全地包覆该电性载板、该第一封装体及露出的该导柱层的该端；
形成一缺口于该电性载板，其中该导线层及该第一封装体从该缺口露出；
形成一第一表面处理层于露出的该导线层的至少一部分上；
移除该电镀导电层；
邻近该导线层设置至少一半导体元件；
形成一第二封装体包覆该至少一半导体元件；以及
切割该第二封装体及该第一封装体。
18.如权利要求17所述的制造方法，其中于形成导线层于该电性载板的该第二面的该步骤中，该导线层包括一走线及一芯片座。
19.如权利要求18所述的制造方法，其中于形成导柱层于该导线层上的该步骤中，该导柱层包括：
导电柱，形成于对应的该走线及对应的该芯片座上。
20.如权利要求18所述的制造方法，其中于移除该电镀导电层的该步骤之后，该走线及该芯片座相互隔离。
21.如权利要求17所述的制造方法，其中形成该第一封装体的该步骤包括：
提供一包覆剂，其中该包覆剂包括树脂及粉状的二氧化硅；
加热该包覆剂至液体状态；
注入呈液态的该包覆剂于该电性载板的该第二面上，该包覆剂在高温和高压下包覆该导线层及该导柱层；以及
固化该包覆剂，使该包覆剂形成该第一封装体。
22.如权利要求17所述的制造方法，其中于形成该第一封装体之前，该制造方法还包括：
形成一粘附层于该导线层及该导柱层上。
23.如权利要求17所述的制造方法，其中于露出该导柱层的该端的该步骤中包括：
以磨削方法移除该第一封装体的至少一部分。
24.如权利要求17所述的制造方法，其中于露出该导柱层的该端的该步骤中，该导柱层具有一端面，该第一封装体具有一封装表面，该导柱层的该端面与该封装表面露出且实质上对齐。
25.如权利要求17所述的制造方法，其中于形成该电镀导电层的该步骤中包括：
形成一籽晶层完全地包覆该电性载板、该第一封装体及露出的该导柱层的该端；以及
形成一子导电层完全地包覆该籽晶层。
26.如权利要求17所述的制造方法，其中形成该缺口于该电性载板的该步骤中包括：
移除该电性载板的一部分，其中，该电性载板的一余留部形成一电镀固环，该电镀固环环绕该第一封装体的周边。
27.如权利要求26所述的制造方法，其中在形成该电镀固环的该步骤中，该电镀固环通过该电镀导电层与该导柱层电性连于该导线层。
28.如权利要求17所述的制造方法，其中在形成该第一表面处理层的该步骤中包括：
使用电镀方法，通过该电镀导电层形成该第一表面处理层于露出的该导线层的至少一部分上。
29.如权利要求17所述的制造方法，其中于移除该电镀导电层的该步骤中，该导柱层的该端露出于该封装体的一封装表面。
30.如权利要求29所述的制造方法，其中在移除该电镀导电层的该步骤之后，该制造方法还包括：
形成一第二表面处理层于露出的该导柱层的该端的至少一部分上。
31.如权利要求17所述的制造方法，其中在移除该电镀导电层的该步骤中，该电镀导电层的一部分被移除，该电镀导电层的一余留部至少覆盖该导柱层的该端。
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CN103187314B (zh) * 2011-12-30 2016-02-17 旭德科技股份有限公司 封装载板及其制作方法
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US9583449B2 (en) 2017-02-28
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