CN102569099B - 一种倒装芯片的封装方法 - Google Patents

一种倒装芯片的封装方法 Download PDF

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Publication number
CN102569099B
CN102569099B CN201010622813.6A CN201010622813A CN102569099B CN 102569099 B CN102569099 B CN 102569099B CN 201010622813 A CN201010622813 A CN 201010622813A CN 102569099 B CN102569099 B CN 102569099B
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Prior art keywords
chip
oxide semiconductor
field effect
semiconductor field
metal oxide
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CN201010622813.6A
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CN102569099A (zh
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石磊
薛彦迅
龚玉平
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Chongqing Wanguo Semiconductor Technology Co ltd
Alpha and Omega Semiconductor Ltd
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NATIONS SEMICONDUCTOR (CAYMAN) Ltd
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Priority to CN201010622813.6A priority Critical patent/CN102569099B/zh
Priority to US13/045,407 priority patent/US8338232B2/en
Publication of CN102569099A publication Critical patent/CN102569099A/zh
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Abstract

本发明一般涉及一种形成半导体器件封装体的制备方法，更确切的说，本发明涉及一种功率器件的倒装芯片的封装方法。本发明先对芯片进行封装，再整体性对芯片及塑封料实施减薄，使得芯片完成封装后所获得的封装体具备较佳的尺寸，并具备良好的散热及电气参数性能。同时，芯片与外部连接的接触端子是通过蚀刻与芯片焊接的引线框架而获得的，保证了接触端子的绝对共面性，接触端子的凸块状的引脚设计，使得利用锡膏将接触端子与电路板焊接时更简单、更牢固，以保障其与PCB的良好结合能力。

Description

一种倒装芯片的封装方法
技术领域
本发明一般涉及一种形成半导体器件封装体的制备方法，更确切的说，本发明涉及一种功率器件的倒装芯片的封装方法。
背景技术
在先进芯片封装方式中，晶圆级封装WLCSP(Wafer Level Chip Scale Packaging)是先行在整片晶圆上进行封装和测试，并利用聚酰亚胺材料覆盖晶圆的一面，然后才将其切割成一个个的IC封装体颗粒，因此封装体的体积即几乎等同于裸芯片的原尺寸，该封装体具备良好的散热及电气参数性能。
通常，在晶圆级封装的复杂工艺流程中，极其重要的步骤之一就是减薄芯片至一定的厚度。而芯片愈薄愈容易碎裂，这就要求在任何工艺步骤中要极力避免对芯片造成任何形态的损伤，例如，晶圆的切割就很容易导致芯片的边缘处有所崩裂，其后果之一就是所获得的不良芯片是缺角的。
另一方面，当前一种称之为平面凸点式封装(FBP，Flat Bump Package)的封装体，以附图1A-1I的工艺流程完成附图1J中封装体150的制备。
图1A示出的是引线框架100，其包括接触端子101和焊盘102，如图1B-1C所示，将芯片110通过导电材料103焊接在焊盘102上，并通过键合线104将连接芯片110内部电路的电极电性连接到接触端子101上，如图1D所示。之后进行塑封，利用塑封料120塑封芯片110及键合线104，并蚀刻引线框架100，使得获得的接触端子101、焊盘102外露于塑封料120，如图1E-1F所示。再对接触端子101、焊盘102的外表面镀一层金，形成镀金层105，如图1G所示；最后与塑封体的顶面粘合一层薄膜130，并切割塑封料120，完成以塑封体120′塑封包覆芯片110及键合线104的封装体150，如图1H-1J所示。
其中，焊盘102作为散热或是电极所用，接触端子101、焊盘102均用于焊接至印刷电路板PCB之类的基板上，并与外部电路连接。焊盘102因为要承载芯片110，其体积一般较大；而键合线104之类的键合引线则容易带来负面效应的离散电感，并且键合线104要保障一定的弧高，这也不利于缩减塑封体120′的厚度。图1J示出的封装体150的尺寸大小、电气性能并不理想。
如此一来，本申请是基于以下考量：先对芯片进行封装再实施减薄，使得芯片完成封装后所获得的封装体具备较佳的尺寸，并具备良好的散热及电气参数性能；在封装工艺过程中，竭力降低芯片的缺角风险并获得更薄的芯片厚度。
发明内容
鉴于上述问题，本发明提出了一种倒装芯片的封装方法，包括以下步骤：
提供一引线框架，在引线框架上设置有多个凸出于引线框架顶面的互连导杆；
将正面设置有键合衬垫的芯片倒装焊接至所述引线框架上，其中，所述键合衬垫与所述互连导杆焊接；
于引线框架的顶面进行塑封，以塑封料塑封包覆所述芯片及互连导杆；
于引线框架的底面蚀刻引线框架，形成与互连导杆连接并凸出于塑封料底面的接触端子；
于所述接触端子的表面设置一层金属保护层；
粘贴一层薄膜至减薄后的塑封料的顶面；
切割塑封料并移除薄膜形成多颗以塑封体塑封包覆所述芯片的封装体。
上述的方法，其中，通过涂覆在互连导杆上的导电材料，将所述键合衬垫与所述互连导杆焊接。
上述的方法，其中，通过镀于互连导杆上的导电材料及镀于键合衬垫上的金属镀层，将所述键合衬垫与所述互连导杆共晶焊接。
上述的方法，其中，还包括在芯片塑封后研磨减薄塑封料及芯片，并将减薄后的芯片的背面于减薄后的塑封料的顶面中予以外露的步骤。
上述的方法，其中，还包括沉积一层背面金属层至减薄后的芯片的背面的步骤。
上述的方法，其中，在沉积一层背面金属层至减薄后的芯片的背面之前，还在减薄后的芯片的背面进行以下工艺步骤：
进行蚀刻；
并且进行离子注入及激光退火。
上述的方法，其中，所述接触端子凸出至塑封体的底面之外，并且所述背面金属层外露于塑封体的顶面。
上述的方法，在一种实施例中，所述芯片为金属氧化物半导体场效应管，所述键合衬垫至少包括构成芯片栅极电极的栅极键合衬垫、构成芯片源极电极的源极键合衬垫，并且所述背面金属层构成芯片的漏极电极。
并且进一步将所述封装体黏接至一基座上，其中，背面金属层通过导电材料与基座黏接，连接栅极键合衬垫的接触端子通过一金属导体电性连接至设置在基座周围的栅极焊盘上，连接源极键合衬垫的接触端子通过另一金属导体电性连接至设置在基座周围的源极焊盘上；以及
基座周围还设置有电性连接至基座的漏极焊盘。
上述的方法，在一个可选实施例中，所述芯片为共漏极双金属氧化物半导体场效应管，其中，所述背面金属层构成共漏极双金属氧化物半导体场效应管所包含的第一、第二金属氧化物半导体场效应管各自的漏极电极；以及
第一、第二金属氧化物半导体场效应管各自漏极电极通过背面金属层彼此相互电性连接。
并且，键合衬垫至少包括构成第一金属氧化物半导体场效应管栅极电极的第一栅极键合衬垫、构成第一金属氧化物半导体场效应管源极电极的第一源极键合衬垫；以及
键合衬垫还包括构成第二金属氧化物半导体场效应管栅极电极的第二栅极键合衬垫、构成第二金属氧化物半导体场效应管源极电极的第二源极键合衬垫。
上述的方法，在一个可选实施例中，所述芯片为高端金属氧化物半导体场效应管和低端金属氧化物半导体场效应管集成的双金属氧化物半导体场效应管，其中，所述背面金属层构成高端金属氧化物半导体场效应管的源极电极和低端金属氧化物半导体场效应管的漏极电极；以及
高端金属氧化物半导体场效应管的源极电极和低端金属氧化物半导体场效应管的漏极电极通过背面金属层彼此相互电性连接。
并且，键合衬垫至少包括构成高端金属氧化物半导体场效应管栅极电极的第一栅极键合衬垫、构成高端金属氧化物半导体场效应管漏极电极的第一漏极键合衬垫；以及
键合衬垫还包括构成低端金属氧化物半导体场效应管栅极电极的第二栅极键合衬垫、构成低端金属氧化物半导体场效应管源极电极的第二源极键合衬垫。
上述的方法，在一个可选实施例中，所述芯片为共漏极双金属氧化物半导体场效应管，其中，所述芯片的背面构成共漏极双金属氧化物半导体场效应管所包含的第一、第二金属氧化物半导体场效应管各自的漏极；
并且还可以选择在所述芯片的背面设置一层背面金属层，所述第一、第二金属氧化物半导体场效应管各自漏极电极通过背面金属层彼此相互电性连接。
上述的方法，在一个可选实施例中，所述芯片为高端金属氧化物半导体场效应管和低端金属氧化物半导体场效应管集成的双金属氧化物半导体场效应管，其中，所述芯片的背面构成高端金属氧化物半导体场效应管的源极电极和低端金属氧化物半导体场效应管的漏极电极；
并且还可以选择在所述芯片的背面设置一层背面金属层，所述高端金属氧化物半导体场效应管的源极电极和低端金属氧化物半导体场效应管的漏极电极通过背面金属层彼此相互电性连接。
本领域的技术人员阅读以下较佳实施例的详细说明，并参照附图之后，本发明的这些和其他方面的优势无疑将显而易见。
附图说明
参考所附附图，以更加充分的描述本发明的实施例。然而，所附附图仅用于说明和阐述，并不构成对本发明范围的限制。
图1A-1J是背景技术中平面凸点式封装的制备流程示意图。
图2A-2K是本申请的封装体的制备流程示意图。
图3A-3D是本申请的封装体的另一实施方式的制备流程示意图。
图4是本申请MOSFET未封装前的俯视结构示意图。
图5是本申请MOSFET完成封装后封装体的俯视结构示意图。
图6是将封装体黏接至一基座上的俯视结构示意图。
图7是通过弯折的金属片分别将栅极键合衬垫、源极键合衬垫电性连接至栅极焊盘、源极焊盘上的俯视结构示意图。
图8A-8F是本申请的另一种芯片封装体的制备流程示意图。
图9是本申请双MOSFET未封装前的俯视结构示意图。
图10本申请双MOSFET完成封装后的俯视结构示意图。
具体实施方式
参见图2A所示，引线框架200的顶面200a设置有多个互连导杆201，其中，互连导杆201凸出于引线框架200顶面200a，引线框架200、互连导杆201的可采用金属铜。如图2A-2C所示，先设置一层导电材料203在互连导杆201上，通过导电材料203将芯片210倒装(Flip Chip)焊接至引线框架200上。
芯片210的正面210a通常设有与外界进行电性连接的键合衬垫(Bonding Pad)，键合衬垫一般作为芯片210内部电路的输入/输出接触端子(I/O Pad)，可作为信号的输入/输出、或是Power和Ground的接口。以图4展示的一种金属氧化物半导体场效应管的芯片结构为例，在芯片210的正面210a设置的键合衬垫至少包括构成芯片210栅极电极的栅极键合衬垫213、构成芯片210源极电极的源极键合衬垫212；其中，栅极键合衬垫213接触芯片210未示出的栅区，源极键合衬垫212接触芯片210未示出的源区。在一种实施方式中，芯片210的背面210b设置有未示出的漏区，在此实施例中，芯片210为一种垂直式功率器件。
参见图2C所示，将正面210a设置有键合衬垫(未示出)的芯片210倒装焊接至引线框架200上，其中，键合衬垫与互连导杆201焊接。例如将图4中源极键合衬垫212、栅极键合衬垫213与互连导杆201焊接。有多种焊接工艺可供选择，一种实施方式是通过涂覆在互连导杆201上的导电材料203，将键合衬垫与互连导杆201焊接，此时导电材料203可选择焊锡膏、导电银浆或是导电薄膜中任意之一。另一实施方式是通过镀于互连导杆201上的导电材料203及镀于源极键合衬垫212、栅极键合衬垫213上的金属镀层(未示出)，将键合衬垫(源极键合衬垫212、栅极键合衬垫213)与互连导杆201共晶焊接，此时导电材料203可选择镀金或银，镀于源极键合衬垫212、栅极键合衬垫213上的金属镀层可采用纯锡(Sn)或金锡(AuSn)、金硅(AuSi)、金锗(AuGe)等合金材料作接触面镀层，当引线框架200、互连导杆201被加热至适合的共晶温度时，金或银元素渗透到金属镀层，熔点的改变与金属镀层的合金层成份相关，令金属镀层的共晶层固化后将源极键合衬垫212、栅极键合衬垫213与互连导杆201紧固的焊接。
参见图2D所示，于引线框架200的顶面200a进行塑封，以塑封料220塑封包覆芯片210及互连导杆201，芯片210周围的空隙均被塑封料220填充，此时，塑封料220的底面220b与引线框架200的顶面200a黏结，而塑封料220通常为环氧塑封料。
参见图2E所示，于图2D中完成塑封工艺后，对塑封料220的顶面220a进行研磨，直至在塑封料220中曝露出芯片210。在研磨工艺过程中，其优点之一就是由于芯片210被塑封料220包围支撑住而不易在减薄过程中碎裂，以致芯片210可以获得6密耳(Mil)、4密耳、2密耳甚至更薄的厚度。此时，塑封料220及芯片210均被研磨减薄，以获得将减薄后的芯片210的背面210c于减薄后的塑封料220的顶面220c中予以外露；同时芯片210的漏区部分被研磨掉，其厚度亦有所减薄。图2E中，一种可选择的步骤是在减薄后的芯片210的背面210c进行蚀刻，如湿法蚀刻，以除去研磨后芯片210的背面210c上所残留的应力层，修复研磨过程中对减薄后的芯片210的背面210c所造成的晶格损伤；之后进行在减薄后的芯片210的背面210c进行离子注入，并在离子注入后用以低温退火或激光退火来消除在减薄后的芯片210的背面210c中产生的一些晶格缺陷。图2F中，沉积一层背面金属层211(如Ti/Ni/Ag的合金)至减薄后的芯片210的背面210c上，在如图4的实施方式中，芯片210为MOSFET，则背面金属层211电性接触芯片210的漏区并构成芯片210的漏极电极。
参见图2F-2G所示，于引线框架200的底面200b蚀刻引线框架200，可利用图中未示出的硬掩膜对引线框架200进行蚀刻，仅保留位于图2F中与互连导杆201连接的接触端子200′，其中，接触端子200′原本是引线框架200的一部分。从而形成与互连导杆201连接并凸出于塑封料220底面220b的接触端子200′，如图2G所示。之后，参见图2H所示，于接触端子200′的表面设置一层金属保护层205，如镀上一层金属保护层205，金属保护层205的材料有多种选择方式，如Ti/Ni/Au的合金。
参见图2I-2J所示，粘贴一层薄膜230至减薄后的塑封料220的顶面220c，薄膜230起到切割膜的作用，可采用紫外线照射胶带(UV tape)或蓝膜(Blue tape)；然后对塑料封220进行切割，如图2J中示出的切割槽220d即是切割刀切割塑料封220所留下的痕迹，用于将完成上述所有封装工艺制程的芯片210从塑封料220上脱离下来。此过程中，薄膜230可以选择在纵向上部分被切割但未完全被切割断。切割塑封料220完成后，塑封料220被切割成多个如图2K所示的塑封体220′，于塑封体220′的顶面220′c移除薄膜230，则形成多颗以塑封体220′塑封包覆芯片210的封装体250。在封装体250中，背面金属层211外露于塑封体220′的顶面220′c，表面设置有金属保护层205的接触端子200′凸出于塑封体220′的底面220′b。
依上述内容，在一种实施方式中，可包括以下步骤：
步骤1：提供一引线框架，在引线框架上设置有多个凸出于引线框架顶面的互连导杆；
步骤2：将正面设置有键合衬垫的芯片倒装焊接至所述引线框架上，其中，所述键合衬垫与所述互连导杆焊接；
步骤3：于引线框架的顶面进行塑封，以塑封料塑封包覆所述芯片及互连导杆；
步骤4：研磨减薄塑封料及芯片，并将减薄后的芯片的背面于减薄后的塑封料的顶面中予以外露；
步骤5：沉积一层背面金属层至减薄后的芯片的背面；
步骤6：于引线框架的底面蚀刻引线框架，形成与互连导杆连接并凸出于塑封料底面的接触端子；
步骤7：于所述接触端子的表面设置一层金属保护层；
步骤8：粘贴一层薄膜至减薄后的塑封料的顶面；
步骤9：切割塑封料并移除薄膜形成多颗以塑封体塑封包覆所述芯片的封装体。
其中所述的芯片可以是如图4所示的单晶体管芯片，也可以是如图9所示的双晶体管芯片。
为了获得图2K所示的封装体250，还有其他实施方式可以实现。例如当已经完成图2D所示的工艺制备流程后，再实施图3A-3D的工艺制备流程，亦可以得到封装体250。在图3A中，先对图2D中刻引线框架200进行蚀刻，于引线框架200的底面200b蚀刻引线框架200，仅保留位于图3A中与互连导杆201连接的接触端子200′，其中，接触端子200′原本是引线框架200的一部分，从而形成与互连导杆201连接并凸出于塑封料220底面220b的接触端子200′，如图3B所示。然后对塑封料220的顶面220a进行研磨，直至在塑封料220中露出芯片210。此时，塑封料220及芯片210均被研磨减薄，并将减薄后的芯片210的背面210c于减薄后的塑封料220的顶面220c中予以外露，同时芯片210的漏区的厚度亦有所减薄。图3C中，一种可选择的步骤是在减薄后的芯片210的背面210c进行蚀刻，如湿法蚀刻，以除去研磨后芯片210.的背面210c上所残留的应力层，修复研磨过程中对芯片210的背面210c所造成的晶格损伤；之后进行在芯片210的背面210c进行离子注入，并在离子注入后用以低温退火或激光退火来消除在芯片210的背面210c中产生的一些晶格缺陷。之后，在图3D中，沉积一层背面金属层211(如Ti/Ni/Ag的合金)至减薄后的芯片210的背面210c上，在如图4的实施方式中，芯片210为MOSFET，则背面金属层211电性接触芯片210的漏区并构成芯片210的漏极电极。对比3D与2G，二者结构并无不同，只是制作流程步骤有所不同。完成图3D的制备流程后再采取2H-2K的制备流程，同样也能得到封装体250。
依上述内容，在一种实施方式中，可包括以下步骤：
步骤1：提供一引线框架，在引线框架上设置有多个凸出于引线框架顶面的互连导杆；
步骤2：将正面设置有键合衬垫的芯片倒装焊接至所述引线框架上，其中，所述键合衬垫与所述互连导杆焊接；
步骤3：于引线框架的顶面进行塑封，以塑封料塑封包覆所述芯片及互连导杆；
步骤4：于引线框架的底面蚀刻引线框架，形成与互连导杆连接并凸出于塑封料底面的接触端子；
步骤5：研磨减薄塑封料及芯片，并将减薄后的芯片的背面于减薄后的塑封料的顶面中予以外露；
步骤6：沉积一层背面金属层至减薄后的芯片的背面；
步骤7：于所述接触端子的表面设置一层金属保护层；
步骤8：粘贴一层薄膜至减薄后的塑封料的顶面；
步骤9：切割塑封料并移除薄膜形成多颗以塑封体塑封包覆所述芯片的封装体。
其中所述的芯片可以是如图4所示的单晶体管芯片，也可以是如图9所示的双晶体管芯片。
图4中芯片210是原始芯片的俯视示意图，图5是将图4中芯片210进行图2A-2K或3A-3D的工艺流程获得的封装体250的俯视示意图。对比图2K封装体250的截面图和图5封装体250的俯视图，外露于塑封体220′的顶面220′c的背面金属层211在图5中并未示出，并且，图2K中设置有金属保护层205的接触端子200′至少包括图5中的源极接触端子200′a、栅极接触端子200′b，其中，金属保护层205在图5中未加标注。在图5中，虚线框212A范围内的接触端子200′均为源极接触端子200′a，虚线框213A范围内的接触端子200′均为栅极接触端子200′b；图4中源极键合衬垫212、栅极键合衬垫213在被图5中塑封料体220′覆盖后并未示出，虚线框212A的位置处于源极键合衬垫212的正上方，而虚线框213A的位置处于栅极键合衬垫213的正上方，所以源极接触端子200′a均通过互连导杆201与源极键合衬垫212电性连接，栅极接触端子200′b均通过互连导杆201与栅极键合衬垫213电性连接(参考图2K)。
封装体250的用途之一就是作为芯片210的载体进行二次封装。如图6所示，将图5中封装体250通过导电材料(如焊锡膏、导电银浆)黏接到基座240上，背面金属层210(未示出)通过导电材料与基座240黏接，也即芯片210的漏极电极电性连接至基座240上，基座240周围还设置有电性连接至基座240的漏极焊盘240c。为了获得如图7所示的二次封装体250′，进一步将栅极接触端子200′b通过一弯折的金属片252电性连接至设置在基座240周围的栅极焊盘240b上，其中金属片252的弯折部分252a与栅极焊盘240b焊接，也即，连接栅极键合衬垫213的接触端子200′通过金属片252电性连接至栅极焊盘240b上；并将源极接触端子200′a通过另一弯折的金属片251电性连接至设置在基座240周围的源极焊盘240a上，也即，连接源极键合衬垫212的接触端子200′通过金属片251电性连接至源极焊盘240a上，其中金属片251的弯折部分251a与源极焊盘240a焊接。源极焊盘240a、栅极焊盘240b、漏极焊盘240c共面，则二次封装体250′可再次进行塑封，源极焊盘240a、栅极焊盘240b、漏极焊盘240c作为引脚分别与外界电路进行连接，分别体现为芯片210的源极、栅极、漏极。其中金属片251和252可以用金属引线，金属带或其它用以半导体封装的金属导体替代。
在另一个实施例中，塑封料和芯片均不需要研磨减薄。参见图8A-8F示出的制备流程，需要指出的是，图2A-2D的制备方式即可获得图8A所展示的结构。所用的芯片可以是如图9所示的双MOSFET结构芯片或是任何底部不带电极、或是任何底部电极不须外露的芯片。以图9展示的芯片310对图8A-8F的制备流程进行说明，芯片310的一种可选择芯片类型是高端金属氧化物半导体场效应管和低端金属氧化物半导体场效应管集成的双金属氧化物半导体场效应管器件，例如图9中第一金属氧化物半导体场效应管为高端金属氧化物半导体场效应管、第二金属氧化物半导体场效应管为低端金属氧化物半导体场效应管。图9中芯片310的背面310b原本就具有一层背面金属层311。在一可选个实施例中，芯片310的背面310b不具有背面金属层311。芯片310的正面310a设置有键合衬垫，如图9，键合衬垫至少包括构成第一金属氧化物半导体场效应管栅极电极的第一栅极键合衬垫313、构成第一金属氧化物半导体场效应管漏极电极的第一漏极键合衬垫312，其中，第一栅极键合衬垫313电接触第一金属氧化物半导体场效应管的栅区，第一漏极键合衬垫312电接触第一金属氧化物半导体场效应管的漏区；以及键合衬垫还包括构成第二金属氧化物半导体场效应管栅极电极的第二栅极键合衬垫315、构成第二金属氧化物半导体场效应管源极电极的第二源极键合衬垫314，其中，第二栅极键合衬垫315电接触第二金属氧化物半导体场效应管的栅区，第二源极键合衬垫314电接触第二金属氧化物半导体场效应管的源区。由于第一、第二金属氧化物半导体场效应管集成在芯片310上，因此图9并未将第一、第二金属氧化物很明显的进行单独标注。其中，第一金属氧化物半导体场效应管的源区位于芯片310的背面310b一侧并与背面金属层311电接触，第二金属氧化物半导体场效应管的漏区位于芯片310的背面310b一侧并与背面金属层311电接触，则背面金属层311构成芯片310所包含的第一金属氧化物半导体场效应管的源极电极、第二金属氧化物半导体场效应管的漏极电极；以及第一金属氧化物半导体场效应管的源极电极、第二金属氧化物半导体场效应管的漏极电极通过背面金属层311彼此相互电性连接。当芯片310的背面310b不具有背面金属层311时，第一金属氧化物半导体场效应管的源区、第二金属氧化物半导体场效应管的漏区通过芯片背面的底部半导体衬底彼此相互电性连接。
上述结构的芯片310，其第一MOSFET为高端或高侧MOSFET(High SideMOSFET)，其第二MOSFET为低端或低侧MOSFET(Low Side MOSFET)。
以图2A-2D的制备方法，利用塑封料320将芯片310塑封，如图8A所示，芯片310的背面金属层311也被完全塑封。然后于引线框架300的底面300b蚀刻引线框架300，可利用图中未示出的硬掩膜对引线框架300进行蚀刻，仅保留位于图8A中与互连导杆301连接的接触端子300′，接触端子300′原本是引线框架300的一部分。从而形成与互连导杆301连接并凸出于塑封料320底面320b的接触端子300′。之后，参见图8C所示，于接触端子300′的表面设置一层金属保护层305，如镀上一层金属保护层305，金属保护层305的材料有多种选择方式，如Ti/Ni/Au的合金。此过程中，不需要对塑封料320的顶面320a进行研磨，也不需要减薄芯片310的厚度。然后如图8D所示的直接粘贴一层薄膜330至塑封料320的顶面320a，并对塑料封320进行切割，如图8E中所示出的切割槽320d即是切割所留下的痕迹，用于将完成上述所有封装工艺制程的芯片310从塑封料320上脱离下来。
完成切割塑封料320后，塑封料320被切割成多个如图8F所示的塑封体320′，于塑封体320′的顶面320′a移除薄膜330，则形成多颗以塑封体320′塑封包覆芯片310的封装体350。在封装体350中，表面设置有金属保护层305的接触端子300′凸出于塑封体320′的底面320′b。图10是图9的芯片310完成上述封装工艺制程后，所获得的图8F中封装体350的俯视示意结构图。图8F中设置有金属保护层305的接触端子300′至少包括图10中的第一漏极接触端子300′a、第一栅极接触端子300′b以及第二源极接触端子300′c、第二栅极接触端子300′d，其中，金属保护层305在图10中未加标注。在图10中，虚线框312A范围内的接触端子300′均为第一漏极接触端子300′a，虚线框313A范围内的接触端子300′均为第一栅极接触端子300′b，虚线框314A范围内的接触端子300′均为第二源极接触端子300′c，虚线框315A范围内的接触端子300′均为第二栅极接触端子300′d。图9中第一漏极键合衬垫312、第一栅极键合衬垫313、第二源极键合衬垫314、第二栅极键合衬垫315在被图10中塑封料体320′覆盖后并未示出，虚线框312A的位置处于第一漏极键合衬垫312的正上方，而虚线框313A的位置处于第一栅极键合衬垫313的正上方，虚线框314A的位置处于第二源极键合衬垫314的正上方，而虚线框315A的位置处于第二栅极键合衬垫315的正上方。所以第一漏极接触端子300′a均通过互连导杆301与第一漏极键合衬垫312电性连接，第一栅极接触端子300′b均通过互连导杆301与第一栅极键合衬垫313电性连接(参考图8F)，第二源极接触端子300′c均通过互连导杆301与第二源极键合衬垫314电性连接，第二栅极接触端子300′d均通过互连导杆301与第二栅极键合衬垫315电性连接。
图9中芯片310的另一种可选择芯片类型是共漏极双金属氧化物半导体场效应管(Common drain dual MOSFET)器件。其中，第一、第二金属氧化物半导体场效应管的栅区和源区都位于芯片310的正面310a的一侧，第一、第二金属氧化物半导体场效应管的漏区都位于芯片310的背面310b一侧并与背面金属层311电接触。这样正面设置的键合衬垫至少包括构成第一金属氧化物半导体场效应管栅极电极的第一栅极键合衬垫、构成第一金属氧化物半导体场效应管源极电极的第一源极键合衬垫；以及构成第二金属氧化物半导体场效应管栅极电极的第二栅极键合衬垫、构成第二金属氧化物半导体场效应管源极电极的第二源极键合衬垫。背面金属层311则构成芯片310所包含的第一、第二金属氧化物半导体场效应管的漏极电极；而第一、第二金属氧化物半导体场效应管的漏极电极通过背面金属层311彼此相互电性连接。当芯片310的背面310b不具有背面金属层311时，第一、第二金属氧化物半导体场效应管的漏区通过芯片背面的半导体衬底彼此相互电性连接。换言之，图9中，在上述提及的芯片310为高端MOSFET和低端MOSFET集成的双MOSFET的实施方式中：
其第一栅极键合衬垫313在芯片310为共漏极双MOSFET的实施方式中转换成共漏极MOSFET的第一栅极键合衬垫；其第一漏极键合衬垫312在芯片310为共漏极双MOSFET的实施方式中转换成共漏极双MOSFET的第一源极键合衬垫；其第二源极键合衬垫314在芯片310为共漏极双MOSFET的实施方式中转换成共漏极双MOSFET的第二源极键合衬垫；其第二栅极键合衬垫315在芯片310为共漏极双MOSFET的实施方式中转换成共漏极双MOSFET的第二栅极键合衬垫。
图10中封装体350与图5中封装体250有所不同，封装体350并不需要额外添加类似图7中金属片251、252将输入/输出接触端子设计在芯片的一侧，封装体350的接触端子300′可直接安装在其他如PCB之类的基板上。所以，如图9所示，如果芯片310内部电路的输入/输出的键合衬垫均在芯片310正面310a的一侧，即使芯片310并非双MOSFET，也可以利用图8A-8F的方法制备类似封装体350的封装结构。
依上述内容，在一种实施方式中，可包括以下步骤：
步骤1：提供一引线框架，在引线框架上设置有多个凸出于引线框架顶面的互连导杆；
步骤2：将正面设置有键合衬垫的芯片倒装焊接至所述引线框架上，其中，所述键合衬垫与所述互连导杆焊接；
步骤3：于引线框架的顶面进行塑封，以塑封料塑封包覆所述芯片及互连导杆；
步骤4：于引线框架的底面蚀刻引线框架，形成与互连导杆连接并凸出于塑封料底面的接触端子；
步骤5：于所述接触端子的表面设置一层金属保护层；
步骤6：粘贴一层薄膜至塑封料的顶面；
步骤7：切割塑封料并移除薄膜形成多颗以塑封体塑封包覆所述芯片的封装体。
上述工艺流程，芯片的背面减薄是基于将芯片固定在塑封料中进行的，因而芯片即使维持在2mil甚至更薄的状态下也不容易崩裂缺角，所以完成封装的最终芯片保持了一个较高水平的良率，这在通常的晶圆级封装中是很难做到的。
上述工艺流程，接触端子是通过引线框架的背面蚀刻而制成的，其有益效果之一就是保证了接触端子的绝对共面性，接触端子的凸块状的引脚设计，使得利用锡膏将接触端子与电路板焊接时更简单、更牢固，以保障其与PCB的良好结合能力。接触端子除了高纯度铜材质本身散热能力好的优势外，其与键合衬垫连接的特殊结构决定了此类封装体还可以透过接触端子间隙来间接散热，整体散热效果很好。另一方面，在背景技术中，图1C示出的焊盘102必须要保持与芯片110近似的尺寸，这样一来，使得芯片110在焊盘102上进行共晶焊时，导致芯片110存在崩裂的潜在危险，而本发明是以多个分散的接触端子来替代焊盘102，则能有效避免该缺陷。
通过说明和附图，给出了具体实施方式的特定结构的典型实施例，例如，本案是以MOSFET、双MOSFET进行阐述，基于本发明精神，芯片还可作其他类型的转换。尽管上述发明提出了现有的较佳实施例，然而，这些内容并不作为局限。
对于本领域的技术人员而言，阅读上述说明后，各种变化和修正无疑将显而易见。因此，所附的权利要求书应看作是涵盖本发明的真实意图和范围的全部变化和修正。在权利要求书范围内任何和所有等价的范围与内容，都应认为仍属本发明的意图和范围内。

Claims (15)

1.一种倒装芯片的封装方法，其特征在于，包括以下步骤：
提供一引线框架，在引线框架上设置有多个凸出于引线框架顶面的互连导杆；
将正面设置有键合衬垫的芯片倒装焊接至所述引线框架上，其中，所述键合衬垫与所述互连导杆焊接；
于引线框架的顶面进行塑封，以塑封料塑封包覆所述芯片及互连导杆；
于引线框架的底面蚀刻引线框架，形成与互连导杆连接并凸出于塑封料底面的接触端子；
于所述接触端子的表面设置一层金属保护层；
粘贴一层薄膜至减薄后的塑封料的顶面；
切割塑封料并移除薄膜形成多颗以塑封体塑封包覆所述芯片的封装体；
在芯片塑封后但在刻蚀引线框架前，研磨减薄塑封料及芯片，将减薄后的芯片的背面于减薄后的塑封料的顶面中予以外露并沉积一层背面金属层至减薄后的芯片的背面；或者
在刻蚀引线框架形成接触端子后，研磨减薄塑封料及芯片，将减薄后的芯片的背面于减薄后的塑封料的顶面中予以外露并沉积一层背面金属层至减薄后的芯片的背面。
2.如权利要求1所述的方法，其特征在于，通过涂覆在互连导杆上的导电材料，将所述键合衬垫与所述互连导杆焊接。
3.如权利要求1所述的方法，其特征在于，通过镀于互连导杆上的导电材料及镀于键合衬垫上的金属镀层，将所述键合衬垫与所述互连导杆共晶焊接。
4.如权利要求1所述的方法，其特征在于，在沉积一层背面金属层至减薄后的芯片的背面之前，还在减薄后的芯片的背面进行以下工艺步骤：
进行蚀刻；
并且进行离子注入及激光退火。
5.如权利要求1所述的方法，其特征在于，所述接触端子凸出至塑封体的底面之外，并且所述背面金属层外露于塑封体的顶面。
6.如权利要求5所述的方法，其特征在于，所述芯片为金属氧化物半导体场效应管，所述键合衬垫至少包括构成芯片栅极电极的栅极键合衬垫、构成芯片源极电极的源极键合衬垫，并且所述背面金属层构成芯片的漏极电极。
7.如权利要求6所述的方法，其特征在于，进一步将所述封装体黏接至一基座上，其中，背面金属层通过导电材料与基座黏接，连接栅极键合衬垫的接触端子通过一金属导体电性连接至设置在基座周围的栅极焊盘上，连接源极键合衬垫的接触端子通过另一金属导体电性连接至设置在基座周围的源极焊盘上；以及
基座周围还设置有电性连接至基座的漏极焊盘。
8.如权利要求5所述的方法，其特征在于，所述芯片为共漏极双金属氧化物半导体场效应管，其中，所述背面金属层构成共漏极双金属氧化物半导体场效应管所包含的第一、第二金属氧化物半导体场效应管各自的漏极电极；以及
第一、第二金属氧化物半导体场效应管各自的漏极电极通过背面金属层彼此相互电性连接。
9.如权利要求8所述的方法，其特征在于，键合衬垫至少包括构成第一金属氧化物半导体场效应管栅极电极的第一栅极键合衬垫、构成第一金属氧化物半导体场效应管源极电极的第一源极键合衬垫；以及
键合衬垫还包括构成第二金属氧化物半导体场效应管栅极电极的第二栅极键合衬垫、构成第二金属氧化物半导体场效应管源极电极的第二源极键合衬垫。
10.如权利要求5所述的方法，其特征在于，所述芯片为高端金属氧化物半导体场效应管和低端金属氧化物半导体场效应管集成的双金属氧化物半导体场效应管，其中，所述背面金属层构成高端金属氧化物半导体场效应管的源极电极和低端金属氧化物半导体场效应管的漏极电极；以及
高端金属氧化物半导体场效应管的源极电极和低端金属氧化物半导体场效应管的漏极电极通过背面金属层彼此相互电性连接。
11.如权利要求10所述的方法，其特征在于，键合衬垫至少包括构成高端金属氧化物半导体场效应管栅极电极的第一栅极键合衬垫、构成高端金属氧化物半导体场效应管漏极电极的第一漏极键合衬垫；以及
键合衬垫还包括构成低端金属氧化物半导体场效应管栅极电极的第二栅极键合衬垫、构成低端金属氧化物半导体场效应管源极电极的第二源极键合衬垫。
12.如权利要求1所述的方法，其特征在于，所述芯片为共漏极双金属氧化物半导体场效应管，其中，所述芯片的背面构成共漏极双金属氧化物半导体场效应管所包含的第一、第二金属氧化物半导体场效应管各自的漏极。
13.如权利要求12所述的方法，其特征在于，所述芯片的背面设置有一层背面金属层，所述第一、第二金属氧化物半导体场效应管各自的漏极电极通过背面金属层彼此相互电性连接。
14.如权利要求1所述的方法，其特征在于，所述芯片为高端金属氧化物半导体场效应管和低端金属氧化物半导体场效应管集成的双金属氧化物半导体场效应管，其中，所述芯片的背面构成高端金属氧化物半导体场效应管的源极电极和低端金属氧化物半导体场效应管的漏极电极。
15.如权利要求14所述的方法，其特征在于，所述芯片的背面设置有一层背面金属层，所述高端金属氧化物半导体场效应管的源极电极和低端金属氧化物半导体场效应管的漏极电极通过背面金属层彼此相互电性连接。
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