CN111508908A - 极薄封装 - Google Patents

极薄封装 Download PDF

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CN111508908A
CN111508908A CN202010073670.1A CN202010073670A CN111508908A CN 111508908 A CN111508908 A CN 111508908A CN 202010073670 A CN202010073670 A CN 202010073670A CN 111508908 A CN111508908 A CN 111508908A
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integrated circuit
backside
grinding
substrate
emc
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金龙宝
林伊国
陈嘉川
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Silego Technology Inc
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Abstract

公开用于实现极薄封装结构的技术。在某些实施例中，器件包含：集成电路，经由连接而连接到引线框或衬底；以及EMC（环氧树脂模制化合物），除了在集成电路的背侧和连接区域之外包围所述集成电路，所述集成电路经由所述连接区域连接到引线框或衬底。

Description

极薄封装
本申请是申请号为2013800480426、发明名称为“极薄封装”的专利申请的分案申请。
背景技术
典型的芯片制造装配工艺包括：应用EMC（环氧树脂模制化合物）来覆盖器件的整个区域，使器件经受在引线上电镀，以及然后经由锯片分离器件。EMC填充剂保护集成电路免于发光诱导的泄露和湿气渗透，但是也促成总体封装厚度。图1说明了由先前提到的装配工艺产生的典型的器件结构。如所描绘的，包围集成电路（即芯片）的EMC大大地促成产生的器件尺寸。
附图说明
在下面的详细描述和附图中公开了本发明的各种实施例。
图1说明了由典型的装配工艺产生的现有技术的器件结构。
图2A说明了由包括研磨工艺的装配工艺产生的封装结构的实施例。
图2B说明了由包括研磨工艺的装配工艺产生的封装结构的实施例。
图3A-3Q说明了用于生成极薄封装结构的装配工艺的实施例。
图3R说明了由公开的装配工艺产生的器件的示例尺寸。
具体实施方式
本发明能够以多种方式实现，包括工艺、装置、系统、物质成分、体现在计算机可读存储介质上的计算机程序产品、和/或处理器，比如配置成执行指令的处理器，所述指令存储在与处理器耦合的存储器上并且/或者由该存储器提供。在这个说明书中，这些实现、或者本发明可以采用的任何其他的形式，可以被称为技术。一般而言，公开的工艺的步骤顺序可以在发明的范围内更改。除非另有阐述，部件比如描述为被配置成执行任务的处理器或存储器可以被实现为在给定时间内被临时配置成执行任务的通用部件或者被实现为被制造成执行任务的特定部件。在本文中使用的术语‘处理器’指代一个或者更多的器件、电路和/或被配置成处理数据比如计算机程序指令的处理核心。
下面连同说明发明的原理的附图一起提供对发明的一个或多个实施例的详细描述。发明被与这样的实施例结合地描述，但是发明并不限制于任何的实施例。发明的范围仅受权利要求所限制，并且发明涵盖许多的替代、修改和等价方案。在下面的描述中提出了许多的具体细节以便提供对发明的透彻的理解。这些细节被提供用于示例的目的，并且本发明可以根据权利要求来实行而没有这些具体细节中的一些或所有。为了清晰的目的，没有详细描述在与本发明相关的技术领域中所已知的技术材料，以便发明不被不必要地模糊。
在本文中公开了用于实现更薄封装厚度的各种技术。如进一步描述的，公开的装配工艺包括用于降低总器件厚度的研磨工艺。研磨工艺促进多种类型的更薄封装结构。在一些实施例中，采用研磨工艺使集成电路（即芯片）的背侧暴露，这可以对不敏感的发光器件是可接受的。替代地，粘附带可以例如被施加在研磨面上以保护集成电路免于发光诱导的泄露和湿气渗透。
图2A说明了由包括研磨工艺的装配工艺产生的封装结构的实施例。如所描绘的，封装结构200包括集成电路（即芯片）202，它部分地被EMC（环氧树脂模制化合物）204包围并且经由突起208连接到引线框（L/F）或者衬底206。在某些实施例中，封装结构200由如下步骤产生：在EMC注入之后使整个引线框或衬底经受顶侧研磨，直到至少芯片的背侧暴露和/或实现期望的厚度。在给定的示例中，封装结构200包括粘附带（即层压膜）210，它被施加在器件的顶部（即倒装芯片202的背侧）上以保护芯片。封装结构200可以包括例如极薄DFN（双扁平无引线）封装或者QFN（方形扁平无引线）封装。
图2B说明了由包括研磨工艺的装配工艺产生的封装结构的实施例。如所描绘的，封装结构220包括集成电路（即芯片）222，它部分地被EMC224包围并且经由突起228连接到引线框（L/F）或者衬底226。在某些实施例中，封装结构220由如下步骤产生：在EMC注入之后使整个引线框或衬底经受顶侧研磨，直到至少芯片的背侧暴露和/或实现期望的厚度。在这个示例中，使集成电路222的背侧暴露，即没有如在图2的实施例中那样施加粘附带。封装结构220可以包括例如暴露的硅极薄DFN或者QFN封装。
图3A-3Q说明用于生成极薄封装结构（诸如关于图2A-2B所描述的那些）的装配工艺的实施例。图3A说明切割晶圆300以分离在晶圆300中的每个芯片302。如在图3A中进一步描绘的，每个芯片302随后经历倒装、助焊剂浸渍以及安装到引线框或者衬底304上。图3B说明倒装芯片安装到引线框或者衬底304上。图3C说明回流步骤以连接芯片302和引线框或衬底304之间的突起。回流温度轮廓取决于突起成分和特性。图3D说明模制步骤，该模制步骤例如由注塑工具执行。如所描绘的，在这个步骤期间芯片302被EMC306所包围。
图3A-3D也说明背侧粘附带305，其可应用于其中芯片302被安装到引线框304的实施例。图3E说明用于移除背侧粘附带305的步骤。图3F说明在其中芯片302被安装到引线框304的实施例中用于提供引线修整307的引线电镀步骤。在其中芯片302被安装到衬底304的实施例中，衬底的端子/引线已经进行预电镀修整。图3G说明引线框/衬底安装（即背侧层压）步骤。如所描绘的，施加背侧安装带308以准备随后的顶侧研磨。
图3H说明使用研磨轮310执行顶侧研磨所经的研磨步骤。这个顶侧研磨工艺被专门引入到装配工艺中以实现期望的封装厚度，并且未被使用在其他现存的DFN/QFN工艺中。图3I说明继续的顶侧研磨直到实现期望的芯片和/或总器件厚度。在某些实施例中，一旦芯片302的背侧暴露就停止研磨。替代地，如在图3I中所描绘的，一旦实现期望的芯片厚度就停止研磨。一旦研磨完成，研磨表面例如被抛光以释放在研磨期间引入的剪应力和/或增加在研磨表面和顶粘附膜（其被用于极薄DFN/QFN封装，比如在图2A中描绘的封装结构200）之间的粘附。
图3J说明剥带步骤，在该剥带步骤中背侧安装带308被移除。图3K说明层压步骤，在该层压步骤中放置顶侧粘附膜312以保护器件免于发光诱导的泄露（对于对发光敏感的器件而言）和湿气渗透。图3L说明层压物固化313步骤，其中顶侧粘附膜312被处理以确保与下面的EMC和芯片背侧的粘附。图3M说明其中出于器件识别和可追踪性目的而对顶侧进行标记的标记步骤，并且说明在标记之后的顶视图314。
图3N说明安装步骤，在该安装步骤中引线框/衬底304被倒装并且安装带316被施加用于在随后的封装锯切步骤期间把器件保持在合适的位置。锯切工艺在引线框/衬底304上执行。图3O说明锯切步骤，其中经由锯片318分离每个器件。图3P说明封装锯切分割步骤的完成。图3Q说明其中手动擦洗安装带316并且/或者为了批量封装、（电气）测试和/或缠带/封装320而采用拾放操纵器以从带316移除器件的步骤。
虽然在图3A-3Q中描绘的装配工艺中说明特定的步骤顺序，但是在其他的实施例中可以更改步骤的顺序。例如，图3H-3I的研磨工艺可以在装配工艺的任何合适的阶段执行。此外，顶侧粘附膜312的包括是可选的。也就是，在暴露的硅封装结构比如在图2B中描绘的封装结构220中不包括顶侧粘附膜312。
图3R说明由图3A-3Q的装配工艺产生的器件的示例尺寸。给定的表格提供针对极薄DFN（ETDFN）和极薄QFN（ETQFN）封装以及暴露的硅极薄DFN（ESETDFN）和暴露的硅极薄QFN（ESETQFN）封装的示例尺寸。总的来说，由于包括的研磨工艺可实现更薄封装。
虽然出于清晰理解的目的，已相当详细地描述了前述的实施例，但是本发明并不限制于提供的细节。存在很多实现发明的替代方式。公开的实施例是说明性的而不是限制性的。

Claims (10)

1.一种器件，包含：
集成电路，经由连接而连接到引线框或衬底；以及
EMC（环氧树脂模制化合物），除了在集成电路的背侧和连接区域之外包围所述集成电路，所述集成电路经由所述连接区域连接到引线框或衬底。
2.权利要求1的器件，其中在器件装配期间集成电路的背侧和器件的顶侧之间的EMC被移除。
3.权利要求1的器件，其中在器件装配期间研磨被用来从器件的顶侧移除EMC并且暴露集成电路的背侧。
4.权利要求3的器件，其中研磨包括使引线框或衬底经受顶侧研磨，直至暴露集成电路的背侧。
5.权利要求3的器件，其中研磨包括使引线框或衬底经受顶侧研磨，直至实现期望的封装厚度。
6.权利要求1的器件，其中集成电路的背侧包含暴露的硅。
7.权利要求1的器件，进一步包含：粘附膜，被施加到器件的顶侧以保护暴露的集成电路的背侧。
8.权利要求7的器件，其中粘附膜被固化以改进与下面的EMC和集成电路背侧的粘附。
9.权利要求1的器件，其中器件包含极薄DFN（双扁平无引线）或者QFN（方形扁平无引线）封装。
10.权利要求1的器件，其中器件包含暴露的硅极薄DFN（双扁平无引线）或者QFN（方形扁平无引线）封装。
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