JP4207696B2 - 半導体パッケージの製造方法 - Google Patents
半導体パッケージの製造方法 Download PDFInfo
- Publication number
- JP4207696B2 JP4207696B2 JP2003270910A JP2003270910A JP4207696B2 JP 4207696 B2 JP4207696 B2 JP 4207696B2 JP 2003270910 A JP2003270910 A JP 2003270910A JP 2003270910 A JP2003270910 A JP 2003270910A JP 4207696 B2 JP4207696 B2 JP 4207696B2
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- JP
- Japan
- Prior art keywords
- wafer
- chip
- resin
- diameter
- small
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
Landscapes
- Wire Bonding (AREA)
Description
Claims (5)
- ウェハ上に半導体チップをフェイスダウン実装する工程と、
前記半導体チップを埋め込む状態で前記ウェハ上を樹脂で覆い、当該樹脂上にフィルム材を貼り合わせる工程と、
前記樹脂で覆われた前記ウェハを当該樹脂が設けられている実装面の裏面側から薄型化する工程と、
前記ウェハを薄型化した後、前記フィルム材と共に前記樹脂を当該ウェハ上から剥がし取る工程とを行う
半導体パッケージの製造方法。 - 前記ウェハ上に樹脂を塗布した後、当該樹脂上に板状材を載置し、当該板状材と当該ウェハとの間隔を保つことで当該樹脂を均等な膜厚に保持した状態で硬化させる
請求項1記載の半導体パッケージの製造方法。 - 前記ウェハは、前記半導体チップの実装面側に複数の半導体チップが配列形成されたものである
請求項1または2記載の半導体パッケージの製造方法。 - 前記ウェハ上に半導体チップを実装した後、前記ウェハを薄型化する前に、当該半導体チップと前記ウェハとの実装状態の検査を行う
請求項1〜3の何れか1項に記載の半導体パッケージの製造方法。 - 前記ウェハ上にフェイスダウン実装された前記半導体チップを裏面側から薄型化する工程を行う
請求項1〜4の何れか1項に記載の半導体パッケージの製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003270910A JP4207696B2 (ja) | 2003-07-04 | 2003-07-04 | 半導体パッケージの製造方法 |
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Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003270910A JP4207696B2 (ja) | 2003-07-04 | 2003-07-04 | 半導体パッケージの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005026633A JP2005026633A (ja) | 2005-01-27 |
JP4207696B2 true JP4207696B2 (ja) | 2009-01-14 |
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003270910A Expired - Fee Related JP4207696B2 (ja) | 2003-07-04 | 2003-07-04 | 半導体パッケージの製造方法 |
Country Status (1)
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JP (1) | JP4207696B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4774999B2 (ja) * | 2006-01-18 | 2011-09-21 | ソニー株式会社 | 半導体装置の製造方法 |
JP5198887B2 (ja) * | 2008-01-24 | 2013-05-15 | 株式会社ディスコ | 積層型半導体装置の製造方法 |
JP6116437B2 (ja) | 2013-08-13 | 2017-04-19 | オリンパス株式会社 | 固体撮像装置およびその製造方法、ならびに撮像装置 |
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2003
- 2003-07-04 JP JP2003270910A patent/JP4207696B2/ja not_active Expired - Fee Related
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JP2005026633A (ja) | 2005-01-27 |
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