TWI277184B - Flip-chip leadframe type package and fabrication method thereof - Google Patents

Flip-chip leadframe type package and fabrication method thereof Download PDF

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Publication number
TWI277184B
TWI277184B TW094142390A TW94142390A TWI277184B TW I277184 B TWI277184 B TW I277184B TW 094142390 A TW094142390 A TW 094142390A TW 94142390 A TW94142390 A TW 94142390A TW I277184 B TWI277184 B TW I277184B
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Taiwan
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conductive pads
lead frame
flip
conductive
wafer
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TW094142390A
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Chinese (zh)
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TW200723459A (en
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Chien Liu
Meng-Jen Wang
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Advanced Semiconductor Eng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A conductive plate is provided on which a plurality of leadframe cells are defined. Each of the leadframe cells has a die-located region and a peripheral region. A plurality of dies is electrically connected with the conductive plate by bumps in the die-located region. A cutting process is performed on each leadframe cell to form a plurality of die-located region conductive pads and a plurality of peripheral region conductive pads electrically connected with the bumps.

Description

1277184 九、發明說明： 【發明所屬之技術領域】 導線架型封裝構造及其製造方 晶片於-導電基材後始進行切 本發明係提供一種覆晶 法，特別指一種於覆晶黏接 割導線架單元之方法。 【先前技術】 • 請參考第1圖與第2圖。第1圖與第2 _為習 線架型封裝構造之方法示意圖，其中第i圖為—上一、· 而第2圖則為第1圖中—單一導線架單元封裝結構=面 不意圖。如第1圖與第2圖所示，提供一導線7 (leadframe)i〇,其包含複數個導線架單元1〇〇，各導線架= 元100包含有一晶片承座11〇，複數個支撐肋條（= bar)120，用以支撐晶片承座11〇並使之連接於導線架單元 1〇〇,複數個接腳130設置於晶片承座11〇四周，用以電性 ❿連接至一外部電路（圖未示）。晶片140則係藉銀膠15〇黏 著固定於導線架單元1〇〇之晶片承座110上，同時晶片14〇 之上表面周圍相對於各接腳130之部位設置有複數個銲墊 142 ’且各銲墊142藉由複數條連接線144電性連接至接腳 130。另外，晶片140、晶片承座u〇、接腳13〇及連接線 144等係包覆於一封膠材料16〇内後進行一單體化分離 (singulation)製程，以形成複數個封裝結構。 1277184 崎著電子I置更輕薄短小之強烈需求及趨勢發展，Ic _ 封衣技，方面’為配合高⑻數、高散熱以及封裝尺寸縮 小化的4準要求下，使得覆晶㈣p啊，fc)方式之封 裝型態需求持續升高，一躍而成為目前封裝之主流。針對 I/O數已相對提间許多之覆晶製程，目前其接腳最小間距雖 可達lOG/zm，但若欲獲得更高腳數，則必須再減少接腳之 間距。然而不論是傳統導線架或是覆晶，都只能減少周圍 鲁部分接腳之間距以增加腳數，亦即，各導線架單元僅有晶 片承座周圍欲形成接腳的部分具有增加腳數之功能，而晶 片承座則無此空間。 【發明内容】 因此，本發明之目的係提供一製作覆晶導線架型封裝 結構封裝結構之方法’以有效提升1/〇數。 根據本發明提供之製作覆晶導線架型封裝結構之方 法’百錄供-導電純，純之 數個導線架單元’該等導線架單元各包 =稷 一外圍區環繞於該置晶區週園θ卜 Β曰區以及 晶片分別包含有複數個凸提供魏個晶丨，且該等 利用覆晶結合，將各該晶片1又於戎片之主動表面。 別銲接於該導電基材上。^杨表面之該等凸塊接點分 基材之下表面切割該導電義如于則製程’由該導電 ，以於各該置晶區形成複數 6 1277184 個分別與該等凸塊接點電性連接之置晶區導電墊，以及於 各該外圍區形成複數個外圍區導電墊，各置晶區導電墊與 外圍區導電墊之間未互相電性連接，且此時該導電基材與 該等晶片仍維持一完整結構而並未分離。之後進行一封合 製程，將一封膠材料覆蓋於該導電基材之上表面與該等晶 片上，並且該封合製程可於該切割製程之前或之後進行。 最後進行一單體化分離製程，以形成複數個封裝結構。 由於本發明提供之方法係於黏接晶片後始進行導線架 圖案切割，因此不僅可於該外圍區内切割出複數個外圍區 導電墊，更可於該置晶區内切割出複數個置晶區導電墊， 更增加晶片I/O之腳數。 為讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉較佳實施方式，並配合所附圖式，作詳細說明如 • 下。然而如下之較佳實施方式與圖式僅供參考與說明用， 並非用來對本發明加以限制者。 【實施方式】 請參閱第3圖至第6圖。第3圖至第6圖為本發明一 較佳實施例製作覆晶導線架型封裝結構之方法之示意圖， '其中第3圖與第5圖係為上示圖，第4圖與第6圖則為剖 -面示意圖，且為彰顯本發明之特點第4圖與第6圖僅繪示 1277184 出單一導線架單元。如第3圖與第4圖所示，提供一導電 基材30，其中於本實施例中導電基材30之材質係為銅， 但並不侷限於此。導電基材30之上表面定義有複數個導線 架單元300，各導線架單元300包含有一置晶區310，以及 一位於置晶區310周圍之外圍區320。再提供複數個晶片 330，且晶片330之一主動表面設置有複數個凸塊接點 332。接著進行一迴銲製程，利用晶片330主動表面之凸塊 _ 接點332，將晶片330覆晶接合於各導線架單元300上之 置晶區310以及部分外圍區320内，並藉由凸塊接點332 電性連接晶片330與導電基材30。導電基材30之下表面 另具有複數個定位記號（圖未示），用於後續切割製程中標 示置晶區310及切割位置。 如第5圖所示，隨後進行一切割製程，由導電基材30 之下表面切割導電基材30，以於各置晶區310内形成複數 • 個分別與凸塊接點332電性連接之置晶區導電墊312 ;以 及於各外圍區320形成複數個外圍區導電墊322，其中切 割製程可為雷射切割製程、各式蝕刻製程或其他可應用於 切割導電基材30之技術，另外各置晶區導電墊312之間、 各外圍區導電墊322之間，以及置晶區導電墊312與外圍 區導電墊322相互之間均係利用切割製程所形成之溝槽 302隔離而未互相電性連接，且此時導電基材30與晶片330 '仍藉由凸塊接點332連接以維持一完整結構而並未分離。 8 1277184 如第6圖所示，接下來進行一封合製程，填入一封膠 材料340，並使封膠材料340包覆晶片330、置晶區導電墊 312與心外圍區導電墊奶。封膠材料權係填入置晶 j電墊312與外圍區導電塾間322之間隙且暴露出置晶 區^Γ電墊312之下表面，使置晶區導電墊312、外圍區導 ，墊322與封膠材料34〇具有一切齊之平面，並使置晶區 、電，Ί園區導電墊322可與其他外部電路電性連 最後進行單體化製程，以分離各導線架單元300形 成各覆晶封裝結構。 本&月於此再提供—第二較佳實施例，係於將晶片330 ^晶接合於置晶區31M4，即進行封合製程。由於本較佳 —較佳實施例不同之處僅在於第5至第6圖中 子口製私進仃時序之不同，因此為了方便說明起見，以下 僅針:如第：圖與第4圖所示之覆晶接合後各步驟詳加敘 述:月多閱第7圖，第7圖為本發明第二較佳實施例製作 ，曰曰導線木=封裝結構之方法之示意圖。如第7圖所示， 阳片33G係藉其主動表面之凸塊接點332以覆晶接合於導 電基材30上之置晶區训以及外圍區32〇内。之後進行一 ί 口衣私填入封膠材料340，包覆晶片_及其凸塊接 έ 332與導電基材3G，並暴露出導電基材30之下表面。 而導電基材3G之下表面另具有複數個定位記號（圖未示）， 1277184 用於後續切割製程中標示置晶區3ig及切割位置。接下來 利用料定位記號進行—切鄕程，由導電基材30之下表 ==基材3〇，以於各置晶區310内形成複數個分別 ?日日 之凸塊接點332電性連接之置晶區導電墊312; 以及於各外圍區畑形成複數個外圍區導電塾1中 各置晶區導電墊312之間、各外圍區導電墊322之間了以 二=〇, 312與外_電塾322相互之間均係利 曰^ ^ 離而未互相電性連接，且此時導電基材30與 了 G仍轉—完整結構而並未分離。另外值得說明的 ^於本第二較佳實施㈣於封合製純始進行切割， 3〇2 二 =12與各外圍區導電墊322溝槽之溝槽 3禾真入封膠材料340。 上述覆晶導線架㈣裝結構料本發明之二較佳實 。而本么明之實際應用並不限於此。舉例來說，導電 :由八他銲墊如導熱墊(thermal pad)取代，而導熱墊可與 ^個凸塊接點電性連接，而不為於上述實施例所限 制，藉以達到較佳之功效。 "、过本發明所提供之方法不同於習知技術之處 糸為於晶片接合於導電基材後始進行切割製程，故不僅可 ;卜圍區切副出複數個外圍區導電墊，更可於置晶區下方 ㈣出複數個導電墊，作為電性連接其他外部電路之接 1277184 腳。而習知技術則受制於導線架僅能提供周圍區域之導電 墊，而置晶區下方無法切割出互相分離之導電墊。故本發 明係可藉由外圍區導電墊與置晶區導電墊達到增加I/O接 腳數之功效。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖與第2圖為習知製作導線架單元示意圖。 第3圖至第5圖為本發明一較佳實施例製作覆晶導線架型 封裝結構之方法之示意圖。 第6圖為本發明第二較佳實施例之剖面圖。 第7圖為本發明第二較佳實施例製作覆晶導線架型封裝結 構之方法之示意圖。 【主要元件符號說明】 10 導電架 100 導線架單元 110 晶片承座 120 支撐肋條 130 接腳 140 晶片 150 銀膠 142 銲墊 144 連接線 160 封膠材料 30 導電基材 300 導線架單元 1277184 302 溝槽 310 312 置晶區導電墊 320 322 外圍區導電墊 330 332 凸塊接點 340 置晶區 外圍區 晶片 封膠材料1277184 IX. Description of the invention: [Technical field of the invention] The lead frame type package structure and the wafer for the same are manufactured after the conductive substrate is cut. The present invention provides a flip chip method, in particular, a flip chip bonding test. The method of the lead frame unit. [Prior Art] • Please refer to Figures 1 and 2. Fig. 1 and Fig. 2 are schematic diagrams showing the method of the conventional frame type package structure, wherein the ith picture is - the first one, and the second picture is the first picture - the single lead frame unit package structure = face not intended. As shown in FIG. 1 and FIG. 2, a lead frame 7 is provided, which includes a plurality of lead frame units 1 , each lead frame = 100 includes a wafer holder 11 〇, a plurality of support ribs (= bar) 120 for supporting the wafer holder 11 〇 and connecting it to the lead frame unit 1 , and a plurality of pins 130 are disposed around the wafer holder 11 for electrically connecting to an external portion Circuit (not shown). The wafer 140 is adhered to the wafer holder 110 of the lead frame unit 1 by the silver paste 15 , and a plurality of pads 142 ′ are disposed around the upper surface of the wafer 14 relative to the pins 130 . Each of the pads 142 is electrically connected to the pins 130 by a plurality of connecting wires 144. In addition, the wafer 140, the wafer holder u, the pins 13 and the connecting wires 144 are coated in a 16-inch adhesive material and then subjected to a singulation process to form a plurality of package structures. 1277184 Saki Electric I set a strong demand for lighter and shorter, and the trend of development, Ic _ sealing technology, in terms of high (8) number, high heat dissipation and package size reduction under the four requirements, so that the flip chip (four) p ah, fc The demand for package type continues to rise, and it has become the mainstream of current packaging. For the I/O number, there is a relatively large number of flip-chip processes. At present, the minimum pitch of the pins can reach lOG/zm, but if you want to obtain a higher number of pins, you must reduce the pitch of the pins. However, whether it is a traditional lead frame or flip chip, the distance between the surrounding lugs can only be reduced to increase the number of pins. That is, each lead frame unit has only the number of pins to be formed around the wafer holder. The function, while the wafer holder does not have this space. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of fabricating a flip-chip leadframe package structure to effectively increase the number of turns. The method for fabricating a flip-chip lead frame type package structure according to the present invention is provided by a plurality of lead frame units, such as a plurality of lead frame units, and each of the lead frame units is surrounded by a peripheral region. The θ Β曰 Β曰 region and the wafer respectively comprise a plurality of protrusions providing Wei granules, and the wafers are bonded to each other, and the wafers 1 are again on the active surface of the ruthenium. Do not solder to the conductive substrate. The bumps of the Yang surface are sub-substrate and the lower surface of the substrate is cut. The conductive meaning is as follows: the process is performed by the conductive, so that each of the crystallized regions forms a plurality of 6 1277184 contacts with the bumps respectively. The conductive pad of the crystal region is connected, and a plurality of peripheral conductive pads are formed in each of the peripheral regions, and the conductive pads of the respective crystal regions are not electrically connected to each other, and the conductive substrate is The wafers still maintain a complete structure without separation. Thereafter, a bonding process is performed to cover a surface of the conductive substrate on the surface of the conductive substrate and the wafer, and the sealing process can be performed before or after the cutting process. Finally, a singulation process is performed to form a plurality of package structures. Since the method provided by the present invention is to cut the lead frame pattern after bonding the wafer, not only a plurality of peripheral conductive pads can be cut in the peripheral region, but also a plurality of crystals can be cut in the crystal region. The area conductive pad increases the number of pins of the chip I/O. The above described objects, features, and advantages of the invention will be apparent from the description and appended claims However, the following preferred embodiments and drawings are for illustrative purposes only and are not intended to limit the invention. [Embodiment] Please refer to Figures 3 to 6. 3 to 6 are schematic views showing a method of fabricating a flip-chip lead frame type package structure according to a preferred embodiment of the present invention, wherein 'Fig. 3 and Fig. 5 are upper diagrams, Figs. 4 and 6 The figure is a cross-sectional view, and in order to highlight the characteristics of the present invention, Figures 4 and 6 show only 1277184 out of a single lead frame unit. As shown in Figs. 3 and 4, a conductive substrate 30 is provided, wherein the material of the conductive substrate 30 in the present embodiment is copper, but is not limited thereto. A plurality of lead frame units 300 are defined on the upper surface of the conductive substrate 30. Each of the lead frame units 300 includes a crystal region 310 and a peripheral region 320 around the crystal region 310. A plurality of wafers 330 are further provided, and one of the active surfaces of the wafer 330 is provided with a plurality of bump contacts 332. Then, a reflow process is performed, and the wafer 330 is flip-chip bonded to the crystal region 310 and the partial peripheral region 320 of each lead frame unit 300 by using the bumps 332 of the active surface of the wafer 330, and by the bumps. The contact 332 electrically connects the wafer 330 and the conductive substrate 30. The lower surface of the conductive substrate 30 has a plurality of positioning marks (not shown) for indicating the seeding area 310 and the cutting position in the subsequent cutting process. As shown in FIG. 5, a cutting process is subsequently performed, and the conductive substrate 30 is cut from the lower surface of the conductive substrate 30 to form a plurality of the respective crystal regions 310 and electrically connected to the bump contacts 332. a plurality of peripheral conductive pads 322 are formed in each of the peripheral regions 320, wherein the cutting process can be a laser cutting process, various etching processes, or other techniques applicable to cutting the conductive substrate 30, and The conductive pads 312 between the respective crystal regions, the conductive pads 322 between the peripheral regions, and the conductive pads 312 and the peripheral conductive pads 322 of the respective crystal regions are separated from each other by the trench 302 formed by the cutting process without mutual Electrically connected, and at this point conductive substrate 30 and wafer 330' are still connected by bump contacts 332 to maintain a complete structure without separation. 8 1277184 As shown in Fig. 6, a bonding process is followed by filling a glue material 340 and encapsulating the sealing material 340 with the wafer 330, the crystal zone conductive pad 312 and the conductive padding of the peripheral region of the heart. The encapsulating material is filled in the gap between the interstitial j pad 312 and the peripheral conductive pad 322 and exposes the lower surface of the crystal pad 312, so that the padding area 312, the peripheral area guide, the pad 322 and the sealing material 34〇 have all the planes, and the crystal zone, the electricity, the conductive pad 322 of the park can be electrically connected with other external circuits, and finally the singulation process is performed to separate the lead frame units 300 to form each Flip chip package structure. This & month is again provided - the second preferred embodiment is to bond the wafer 330 to the crystallizing region 31M4, that is, to perform a sealing process. Since the preferred embodiment of the present invention differs only in the timing of the sub-ports in the fifth to sixth figures, for the sake of convenience of explanation, the following only pin: as shown in the figure: Figure 4 and Figure 4 The steps after the flip chip bonding shown are described in detail: FIG. 7 is a more detailed view of the second preferred embodiment of the present invention. As shown in Fig. 7, the positive film 33G is bonded to the crystallographic region of the conductive substrate 30 and the peripheral region 32 by the bump contact 332 of the active surface. Thereafter, a cover material is filled in the encapsulant 340, the wafer _ and its bump 332 and the conductive substrate 3G are covered, and the lower surface of the conductive substrate 30 is exposed. The surface of the conductive substrate 3G has a plurality of positioning marks (not shown), and 1277184 is used for marking the crystallographic area 3ig and the cutting position in the subsequent cutting process. Next, the material positioning mark is used to perform a cutting process, and the conductive substrate 30 is under the surface == substrate 3 〇, so as to form a plurality of respective bump contacts 332 in each of the crystallizing regions 310. Connected to the crystal region conductive pad 312; and in each of the peripheral regions 畑 formed in a plurality of peripheral regions of the conductive 塾 1 between each of the crystal region conductive pads 312, between the peripheral regions of the conductive pads 322 between two = 〇, 312 and The external _ 塾 322 are mutually connected and not electrically connected to each other, and at this time, the conductive substrate 30 and G still rotate - the complete structure is not separated. In addition, it is worthy of explanation. In the second preferred embodiment (4), the sealing is performed at the beginning of the sealing process, and the trenches of the trenches 3 and 12 of each peripheral region are filled with the sealing material 340. The above-mentioned flip-chip lead frame (four) mounting structure material is preferably the second embodiment of the present invention. The actual application of this is not limited to this. For example, the conductive: replaced by a solder pad, such as a thermal pad, and the thermal pad can be electrically connected to the bump contacts, instead of limiting the above embodiments, thereby achieving better performance. . ", the method provided by the present invention is different from the conventional technology, that is, after the wafer is bonded to the conductive substrate, the cutting process is started, so that not only the surrounding area can be cut out, but also a plurality of peripheral conductive pads, A plurality of conductive pads may be formed under the crystallographic region (4) to electrically connect other external circuits to the 1277184 pin. Conventional techniques are subject to the fact that the lead frame can only provide conductive pads in the surrounding area, and the conductive pads that are separated from each other cannot be cut under the crystallizing area. Therefore, the present invention can achieve the effect of increasing the number of I/O pins by using the conductive pads in the peripheral region and the conductive pads in the crystal region. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention. [Simple description of the drawings] Figs. 1 and 2 are schematic views of a conventional lead frame unit. 3 to 5 are schematic views showing a method of fabricating a flip-chip lead frame type package structure according to a preferred embodiment of the present invention. Figure 6 is a cross-sectional view showing a second preferred embodiment of the present invention. Figure 7 is a schematic view showing a method of fabricating a flip-chip lead frame type package structure in accordance with a second preferred embodiment of the present invention. [Main component symbol description] 10 Conductor frame 100 Lead frame unit 110 Wafer holder 120 Support rib 130 Pin 140 Wafer 150 Silver glue 142 Pad 144 Connection line 160 Sealing material 30 Conductive substrate 300 Lead frame unit 1277184 302 Groove 310 312 crystal area conductive pad 320 322 peripheral area conductive pad 330 332 bump contact 340 crystal area peripheral area wafer sealing material

1212

Claims (1)

1277184 十、申請專利範圍： 1. 一種製作覆晶導線架型封裝結構之方法，包含： 提供一導電基材； 於該導電基材上定義出至少一置晶區，以及至少一外圍 區環繞該置晶區， 提供至少一晶片，該晶片包含有複數個凸塊接點設置於 _ 該等晶片之一主動表面； 覆晶接合該晶片至該置晶區上，並使該等凸塊接點固定 於該導電基材上， 進行一切割製程，將該導電基材切割成複數個導電墊， 且該等導電墊分別對應於該等凸塊接點；以及 進行一單體化分離(singulation)製程，以形成複數個覆晶 導線架型封裝結構。 • 2.如申請專利範圍第1項所述之方法，另包含有於該切割 製程之後進行一封合製程，利用一封膠材料包覆該晶片 及部分該等導電墊。 3.如申請專利範圍第1項所述之方法，另包含有於該切割 製程之前進行一封合製程，利用一封膠材料包覆該晶片 及部分該導電基材。 13 1277184 4. 如申請專利範圍第1項所述之方法，其中該切割製程係 為一雷射切割製程。 5. 如申請專利範圍第1項所述之方法，其中該切割製程係 為一蝕刻製程。 6. 如申請專利範圍第1項所述之方法，其中該切割製程係 施加於該置晶區内以及該外圍區内，以形成該等導電墊。 7. 如申請專利範圍第6項所述之方法，其中該等導電墊包 含有複數個置晶區導電墊，以及複數個外圍區導電墊。 8. —種覆晶導線架型封裝結構，包含有： 一導線架單元，該導線架單元包含有： 一置晶區，位於該導線架之一上表面，該置晶區包 含有複數個置晶區導電墊，且該等置晶區導電 整係利用複數個溝槽互相電性隔離； 至少一晶片，位於該導線架單元之該置晶區内； 複數個凸塊接點設置於該晶片之一主動表面，且該晶片 藉由該等凸塊接點並利用覆晶方式與該導線架單元 接合；以及 一封膠材料，包覆該晶片與部分該導線架單元。 14 1277184 9. 如申請專利範圍第8項所述之覆晶導線架型封裝結構， 其中該導線架早元之材質係為銅。 10. 如申請專利範圍第8項所述之覆晶導線架型封裝結構， 其中該導線架單元另包含有複數個外圍區導電墊位於該 置晶區之週圍，且該等外圍區導電墊係利用複數個溝槽 隔離而未互相電性連接。 _ 11.如申請專利範圍第10項所述之覆晶導線架型封裝結 構，其中該外圍區導電墊與該置晶區導電墊係利用複數 個溝槽隔離而未互相電性連接。 12. 如申請專利範圍第11項所述之覆晶導線架型封裝結 構，其中該封膠材料未填入該等置晶區導電墊間與該等 外圍區導電墊間之該等溝槽内。 13. 如申請專利範圍第11項所述之覆晶導線架型封裝結 構，其中該封膠材料係填入該等置晶區導電墊間與該等 外圍區導電墊間之該等溝槽内，使該等置晶區導電墊、 該外圍區導電墊與該封膠材料具有一切齊之平面。 十一、圖式： 151277184 X. Patent Application Range: 1. A method for fabricating a flip-chip lead frame type package structure, comprising: providing a conductive substrate; defining at least one crystal region on the conductive substrate, and surrounding at least one peripheral region a seeding region, providing at least one wafer, the wafer comprising a plurality of bump contacts disposed on one of the active surfaces of the wafers; flip chip bonding the wafers to the crystallographic regions, and bonding the bumps Fixing on the conductive substrate, performing a cutting process, cutting the conductive substrate into a plurality of conductive pads, wherein the conductive pads respectively correspond to the bump contacts; and performing a singulation singulation The process is to form a plurality of flip-chip lead frame type package structures. 2. The method of claim 1, further comprising performing a bonding process after the cutting process, coating the wafer and a portion of the conductive pads with a glue material. 3. The method of claim 1, further comprising performing a bonding process prior to the cutting process, coating the wafer and a portion of the conductive substrate with a glue material. The method of claim 1, wherein the cutting process is a laser cutting process. 5. The method of claim 1, wherein the cutting process is an etching process. 6. The method of claim 1, wherein the cutting process is applied to the crystallographic region and the peripheral region to form the conductive pads. 7. The method of claim 6, wherein the conductive pads comprise a plurality of patterned pad conductive pads and a plurality of peripheral conductive pads. 8. A flip-chip leadframe type package structure comprising: a leadframe unit, the leadframe unit comprising: a crystallographic region on an upper surface of the leadframe, the crystallographic region comprising a plurality of a conductive pad of the crystal region, and the conductive regions are electrically isolated from each other by a plurality of trenches; at least one wafer is located in the crystallographic region of the leadframe unit; and a plurality of bump contacts are disposed on the wafer An active surface, and the wafer is bonded to the lead frame unit by the bump contacts and by flip chip bonding; and an adhesive material covering the wafer and a portion of the lead frame unit. 14 1277184 9. The flip-chip lead frame type package structure according to claim 8, wherein the lead frame of the lead frame is made of copper. 10. The flip-chip lead frame type package structure of claim 8, wherein the lead frame unit further comprises a plurality of peripheral area conductive pads located around the crystallized area, and the peripheral area conductive pads are A plurality of trench isolations are used without being electrically connected to each other. 11. The flip-chip leadframe package structure of claim 10, wherein the peripheral region conductive pads and the crystal region conductive pads are separated from each other by a plurality of trenches without being electrically connected to each other. 12. The flip-chip lead frame type package structure of claim 11, wherein the sealant material is not filled in the trenches between the conductive pads of the crystallographic regions and the conductive pads of the peripheral regions . 13. The flip-chip lead frame type package structure of claim 11, wherein the encapsulant material is filled in the trenches between the conductive pads of the crystallographic regions and the conductive pads of the peripheral regions The conductive pads of the crystallographic regions, the conductive pads of the peripheral region and the sealing material have a uniform plane. XI. Schema: 15
TW094142390A 2005-12-02 2005-12-02 Flip-chip leadframe type package and fabrication method thereof TWI277184B (en)

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Publication number Priority date Publication date Assignee Title
TWI419241B (en) * 2009-04-10 2013-12-11 Advanced Semiconductor Eng Lead frame and manufacturing method thereof and manufacturing method of advanced quad flat non-leaded package

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JP7182374B2 (en) * 2017-05-15 2022-12-02 新光電気工業株式会社 Lead frame and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI419241B (en) * 2009-04-10 2013-12-11 Advanced Semiconductor Eng Lead frame and manufacturing method thereof and manufacturing method of advanced quad flat non-leaded package

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