CN102832190B - 一种倒装芯片的半导体器件及制造方法 - Google Patents

一种倒装芯片的半导体器件及制造方法 Download PDF

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CN102832190B
CN102832190B CN201110170016.3A CN201110170016A CN102832190B CN 102832190 B CN102832190 B CN 102832190B CN 201110170016 A CN201110170016 A CN 201110170016A CN 102832190 B CN102832190 B CN 102832190B
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chip
pedestal
electrode
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CN102832190A (zh
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薛彦迅
何约瑟
哈姆扎·耶尔马兹
鲁军
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Alpha and Omega Semiconductor Cayman Ltd
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Abstract

本发明一般涉及一种倒装芯片的半导体器件及方法，更确切的说，本发明涉及一种利用倒装芯片的封装方式所制备的包含金属氧化物半导体场效应晶体管的半导体器件及其制造方法。在芯片安装单元上，通过在第一基座、第二基座各自的顶面上进行半刻蚀或模压来获得横向或纵向的凹槽，以将第一基座的顶面分割成包含多个第一类粘贴区的多个区域，将第二基座的顶面分割成至少包含一个第二类粘贴区的多个区域，其中，芯片顶面的电极与第一类粘贴区、第二类粘贴区与进行接触并粘贴。

Description

一种倒装芯片的半导体器件及制造方法
技术领域
本发明一般涉及一种倒装芯片的半导体器件及方法，更确切的说，本发明涉及一种利用倒装芯片的封装方式所制备的包含金属氧化物半导体场效应晶体管的半导体器件及其制造方法。
背景技术
随着集成电路相关制造工艺的发展以及芯片按照比例尺寸缩小的趋势，器件热传导工程在半导体工艺和器件性能改善方面所起的作用越来越明显。尤其是在一些特殊的芯片类型上，如一些应用于功率芯片上的金属氧化物半导体器件。
通常，在半导体器件的复杂制备工艺流程中，尤其是封装过程中，芯片存在各种各样的热传导设计方式，由于器件尺寸的逐步缩小，很多散热方式相对较佳的封装形式对器件的性能是有改善的。专利号为US20070108564的美国专利申请公开了一种利用倒装芯片制程制造的半导体器件，图1是该发明中由功率芯片102构成的半导体封装器件100，该半导体封装器件100包括应用于芯片102上方的金属架110的电性连接及散热途径，及通过互连结构104等将芯片102电性连接至引脚106、108上。在该半导体封装器件100中，金属架110及引脚106、108与芯片102的布局未能达到最佳的散热效果，因为芯片102是通过焊锡球类或焊接凸块类的互连结构104电性连接至引脚106、108，而并非直接与引脚106、108接触。
实际上，如果针对类似如应用于功率器件的双扩散金属氧化物半导体场效应晶体管DMOSFET(Double-diffusion metal-oxide-semiconductor FET)等芯片类型而言，芯片的表面一般只有栅极和源极，若是再利用焊锡球(Solder ball)或焊接凸块(Bump)来将栅极、源极连接至引脚，则会较为明显的影响到器件热性能。正是鉴于以上情况，基于芯片封装工艺中的倒装芯片(Flip Chip)技术，提出了本发明所提供的各种实施例。
发明内容
鉴于上述所提及的问题，本发明提供一种倒装芯片的半导体器件，包括：一芯片安装单元，至少包含第一基座以及设置在第一基座附近并与第一基座分离开的第二基座和引线座，并且在所述第一基座的顶面、第二基座的顶面均形成有多条包括横向及纵向的凹槽，其中，位于第一基座的顶面的凹槽将第一基座的顶面分割成包含多个第一类粘贴区的多个区域，位于第二基座的顶面的凹槽将第二基座的顶面分割成至少包含一个第二类粘贴区的多个区域；以及
倒装粘贴至第一基座、第二基座上的芯片，其中，所述芯片包括位于芯片正面的第一电极和第二电极，所述芯片的第一电极与所述多个第一类粘贴区接触并粘贴在一起，芯片的第二电极与第二类粘贴区接触并粘贴在一起。
上述的倒装芯片的半导体器件，位于第一基座顶面边缘处的一横向凹槽对应与位于第二基座顶面边缘处的一横向凹槽处于同一直线上，并且位于第一基座顶面边缘处的一纵向凹槽对应与位于第二基座顶面边缘处的一纵向凹槽处于同一直线上。
上述的倒装芯片的半导体器件，处于同一直线上的第一基座顶面边缘处的横向凹槽和第二基座顶面边缘处的横向凹槽，以及处于同一直线上的第一基座顶面边缘处的纵向凹槽和第二基座顶面边缘处的纵向凹槽，与第一基座顶面边缘处的另一横向凹槽和另一纵向凹槽围绕构成一矩形的周边槽。
上述的倒装芯片的半导体器件，所述芯片为一金属氧化物半导体场效应管，并且所述第一电极为芯片的源极，第二电极为芯片的栅极，位于芯片背面的第三电极为芯片的漏极。上述的倒装芯片的半导体器件，其中，所述芯片的第三电极通过键合线进一步电性连接至引线座上。
上述的倒装芯片的半导体器件，芯片边缘四周的切割区位于所述周边槽的正上方。
此外，本发明还提供一种倒装芯片的半导体器件的制造方法，包括以下步骤：提供包含多个由第一基座、第二基座及引线座构成的芯片安装单元的引线框架，其中，第一基座的顶面包含多个第一类粘贴区，第二基座的顶面至少包含一个第二类粘贴区；
在第一类粘贴区、第二类粘贴区涂覆导电材料，将一芯片倒装粘贴至第一基座、第二基座上，芯片的第一电极与第一类粘贴区接触并粘贴在一起，芯片的第二电极与第二类粘贴区接触并粘贴在一起；
利用键合线将位于芯片背面的第三电极电性连接至引线座上；
利用塑封料封装所述引线框架、芯片及键合线，然后对所述引线框架及塑封料进行切割用于将以塑封体塑封芯片、键合线、芯片安装单元的封装体分离出来；
其中，第二基座及引线座设置在第一基座附近并均与第一基座分离开，在第一基座的顶面、第二基座的顶面均形成有多条包括横向及纵向的凹槽，位于第一基座的顶面的凹槽将第一基座的顶面分割成包含多个第一类粘贴区的多个区域，位于第二基座的顶面的凹槽将第二基座的顶面分割成至少包含一个第二类粘贴区的多个区域。
上述的方法，所述横向及纵向的凹槽是在第一基座、第二基座及引线座各自的顶面上进行半刻蚀或模压实现的。
上述的方法，位于第一基座顶面边缘处的一横向凹槽对应与位于第二基座顶面边缘处的一横向凹槽处于同一直线上，并且位于第一基座顶面边缘处的一纵向凹槽对应与位于第二基座顶面边缘处的一纵向凹槽处于同一直线上。上述的方法，处于同一直线上的第一基座顶面边缘处的横向凹槽和第二基座顶面边缘处的横向凹槽，以及处于同一直线上的第一基座顶面边缘处的纵向凹槽和第二基座顶面边缘处的纵向凹槽，与第一基座顶面边缘处的另一横向凹槽和另一纵向凹槽围绕构成一矩形的周边槽。
上述的方法，将所述芯片倒装粘贴至第一基座、第二基座上时，所述芯片边缘四周的切割区位于所述周边槽的正上方。
上述的方法，所述芯片为一金属氧化物半导体场效应管，并且所述第一电极为芯片的源极，第二电极为芯片的栅极，位于芯片背面的第三电极为芯片的漏极。
本领域的技术人员阅读以下较佳实施例的详细说明，并参照附图之后，本发明的这些和其他方面的优势无疑将显而易见。
附图说明
参考所附附图，以更加充分的描述本发明的实施例。然而，所附附图仅用于说明和阐述，并不构成对本发明范围的限制。
图1是背景技术中公开了的利用倒装芯片制程制造的半导体器件。
图2A是本发明第一基座附近的第二基座、引线座组合在一起的立体结构示意图。
图2B是本发明第一基座附近的第二基座、引线座组合在一起的俯视示意图。
图2C是第一基座、第二基座各自的表面未经刻蚀或模压前的结构示意图。
图3是在本发明中芯片的结构示意图。
图4是芯片焊接在第一基座、第二基座、引线座上的立体结构示意图。
图5是芯片焊接在第一基座、第二基座、引线座上的截面示意图。
图6是第一基座、第二基座各自表面进行刻蚀或模压的另外一种实施方式的示意图。
图7A-7G是本发明的半导体器件的制备流程示意图。
具体实施方式
图2A所示出的包含第一基座201、第二基座202、引线座203的芯片安装单元200与图3所示出的芯片300封装在一起就构成了图4所示出的半导体器件400。在图2A的芯片安装单元200中，第二基座202、引线座203设置在第一基座201附近并与第一基座201分离断开，图2B是图2A的平面俯视图，在第一基座201的顶面形成有多条包括横向及纵向的凹槽，如纵向凹槽204、204a、204b及横向凹槽205、205a、205b；同样在第二基座202的顶面形成有多条包括横向及纵向的凹槽，如纵向凹槽206a、206b及横向凹槽207a、207b。其中，图2B所描述的凹槽只是为了便于叙述说明，其数量并不受限制。图2B中，位于第一基座201的顶面包括横向及纵向的凹槽(如凹槽204、204a、204b及凹槽205、205a、205b)将第一基座201的顶面分割成包含多个第一类粘贴区201b的多个区域，位于第二基座202的顶面包括横向及纵向的凹槽(如凹槽206a、206b及凹槽207a、207b)将第二基座202的顶面分割成至少包含一个第二类粘贴区202b的多个区域。
参见图2A及2B，第一基座201还连接有多个引脚201a，第二基座202还连接有一个或多个引脚202a，引线座203还连接有多个引脚203a。为了便于理解图2A所示的在第一基座201的顶面、第二基座202的顶面所形成的多条包括横向及纵向的凹槽，图2C的芯片安装单元200′是图2A中芯片安装单元200未形成凹槽的结构形式。在芯片安装单元200′中，有多种方式可以形成如图2A及2B那样的横向或纵向的凹槽，一种优选方式是在第一基座201′、第二基座202′、引线座203′各自的顶面进行半刻蚀(Halfetch)或进行模压(Punch)，半刻蚀是指在厚度上部分刻蚀第一基座201′、第二基座202′、引线座203′。
参见图3所示，芯片300为垂直式的功率器件，例如顶源底漏式的金属氧化物半导体场效应晶体管，则芯片300的第一电极301为源极、第二电极302为栅极，为芯片300漏极的第三电极303位于芯片300的背面(未示出)。参见图4所示，即是将芯片300以倒装芯片的封装方式安置在图2A所示出的芯片安装单元200上。在图4中，芯片300焊接至第一基座201、第二基座202上，其中，芯片300的第一电极301与第一类粘贴区201b接触并焊接在一起，芯片300的第二电极302与第二类粘贴区202b接触并焊接在一起，并且位于芯片300背面的第三电极303通过键合线401进一步电性连接至引线座203上。键合线401还可以用其他的导体替代，例如金属带、金属片等。芯片300也有其他的可选类型，例如底源顶漏的垂直金属氧化物半导体场效应晶体管，则第一电极301为漏极、第二电极302为栅极，位于芯片300的背面的第三电极303为源极。
图5是图4的截面示意图，在半导体器件400的截面结构中，参考图2A、2B，位于第一基座201顶面边缘处的一横向凹槽205b对应与位于第二基座202顶面边缘处的一横向凹槽207b处于同一直线上，位于第一基座201顶面边缘处的一纵向凹槽204b对应与位于第二基座202顶面边缘处的一纵向凹槽206b处于同一直线上。进而，处于同一直线上的第一基座202顶面边缘处的横向凹槽205b和第二基座202顶面边缘处的横向凹槽207b，以及处于同一直线上的第一基座201顶面边缘处的纵向凹槽204b和第二基座202顶面边缘处的纵向凹槽206b，与第一基座201顶面边缘处的另一纵向凹槽204a和另一横向凹槽205a围绕构成一矩形的以虚线示出的周边槽(Surrounding Groove)208。而位于第二基座202顶面边缘处的另一纵向凹槽206a和另一横向凹槽207a与纵向凹槽206b、横向凹槽207b围绕构成另一以虚线示出的矩形槽209，以将第二类粘贴区202b围绕在内。
如图5及图4所示，在粘贴芯片300至第一基座201、第二基座202上的过程中，要保障芯片300边缘四周的切割区304位于周边槽208的正上方，也就是说在垂直方向上芯片300边缘四周的切割区304位于周边槽208内，以防止芯片300与芯片安装单元200的其他部位发生电气接触而短路。切割区304原本是芯片300在同一晶圆上与其他芯片铸造连接在一起的部分，而芯片300被从晶圆上切割下来后，切割区(Scribe line)304被部分切割掉但还有部分遗留在芯片300的边缘四周。切割区304位于周边槽208的正上方也即是意味着切割区304的垂直投影落在周边槽208内。所以，基于芯片300的尺寸大小而要对周边槽208的尺寸进行调整，以使得周边槽208的尺寸比芯片300的尺寸稍大。在图2B及图5中，如果纵向凹槽204a、横向凹槽205a、纵向凹槽204b、纵向凹槽206b、横向凹槽207b、横向凹槽205b中最小的凹槽宽度为W，则芯片300边缘四周的切割区304在垂直方向上位于这个W的宽度范围内。
图2B所示的芯片安装单元200还可以利用图6所示的芯片安装单元500代替。芯片安装单元200与芯片安装单元500的结构并无较大的差异，只是芯片安装单元500中第一基座501的顶面被更多的横向及纵向凹槽分割成更多的包含多个第一类粘贴区501b的多个区域。但是位于第二基座502的顶面的凹槽仅仅为一横向凹槽和一纵向凹槽，将第二基座502的顶面分割成包含一个第二类粘贴区502b的多个区域。上述差异可以在第一基座501、第二基座502各自表面进行半刻蚀或模压的流程中，以不同的刻蚀图案或模压图案实现。
为了获得图4示出的半导体器件400并将其塑封，图7A-7E展示了本发明的半导体器件的制备流程示意图。图7A是引线框架605的平面俯视示意图，引线框架605包含多个芯片安装单元600(与图2A或图6所示的芯片安装单元相同)，进一步而言，引线框架605包含多个由第一基座601、第二基座602及引线座603(与图2A或图6所示的芯片安装单元相同)构成的芯片安装单元600，其中，第一基座601的顶面包含多个第一类粘贴区(未示出，参考图2A或图6)，第二基座602的顶面至少包含一个第二类粘贴区(未示出，参考图2A或图6)。
图7B是芯片安装单元600的截面示意图，在图7B-7D中，通过在第一类粘贴区、第二类粘贴区涂覆导电材料802，将芯片700(与图3所示的芯片300相同)倒装焊接至第一基座601、第二基座602上。芯片700的第一电极701与第一类粘贴区接触并焊接在一起，芯片700的第二电极702与第二类粘贴区接触并焊接在一起，其中导电材料802可以为焊接剂(如焊锡膏)或导电粘合剂(如导电银浆)；将芯片700倒装焊接至第一基座601、第二基座602上还可以用共晶焊的方式进行，芯片700的第一电极701、第二电极702可以采用纯锡(Sn)或金锡(Au-Sn)合金作接触面镀层，第一电极701、第二电极702可共晶焊接于镀有金或银的第一类粘贴区、第二类粘贴区上，芯片安装单元600被加热至适合的共晶温度时，令共晶层固化并将芯片700紧固的焊于第一基座601、第二基座602上。其中，由于有横向或纵向的凹槽的存在，使得导电材料802不易从芯片安装单元600溢出，并且多个第一类粘贴区及第二类粘贴区的存在加强了芯片700与第一基座601、第二基座602之间的连接强度。
如图7E所示，利用键合线801将位于芯片700背面的第三电极电性连接至引线座603上，并利用塑封料803封装引线框架605、芯片700及键合线801，如图7F完成以塑封料803塑封引线框架605后的塑封料803、引线框架605的截面示意图。然后对引线框架605及塑封料803进行切割用于将以塑封体803′塑封芯片700、键合线801、芯片安装单元600的封装体900从引线框架605及塑封料803′中分离出来，以形成单独的器件，如图7G所示。在芯片安装单元600中，其引脚(未示出，类同如图2A所示的引脚201a、202a、203a)可作为芯片安装单元600与引线框架605连接的连筋，引脚在对引线框架605及塑封料803的切割过程中被切断，并且塑封体803′源于对塑封料803的切割。而且在上述步骤中，将芯片700倒装焊接至第一基座601、第二基座602上时，要保障芯片700边缘四周的切割区804位于芯片安装单元600的周边槽808(参考图7E及图5)的正上方。在本申请的一种优选实施方式中，芯片700为一金属氧化物半导体场效应管，第一电极701为芯片700的源极，第二电极702为芯片的栅极，第三电极为芯片700的漏极。而在另一种可选的实施方式中，芯片700为一金属氧化物半导体场效应管，第一电极701为芯片700的漏极，第二电极702为芯片的栅极，并且第三电极为芯片700的源极。
通过说明和附图，给出了具体实施方式的特定结构的典型实施例，例如，本案是以金属氧化物半导体晶体管器件进行阐述，基于本发明精神，芯片还可作其他类型的转换。尽管上述发明提出了现有的较佳实施例，然而，这些内容并不作为局限。
对于本领域的技术人员而言，阅读上述说明后，各种变化和修正无疑将显而易见。因此，所附的权利要求书应看作是涵盖本发明的真实意图和范围的全部变化和修正。在权利要求书范围内任何和所有等价的范围与内容，都应认为仍属本发明的意图和范围内。

Claims (9)

1.一种倒装芯片的半导体器件，其特征在于，包括：
一芯片安装单元，至少包含第一基座以及设置在第一基座附近并与第一基座分离开的第二基座和引线座，并且在所述第一基座的顶面、第二基座的顶面均形成有多条包括横向及纵向的凹槽，其中，位于第一基座的顶面的凹槽将第一基座的顶面分割成包含多个第一类粘贴区的多个区域，位于第二基座的顶面的凹槽将第二基座的顶面分割成至少包含一个第二类粘贴区的多个区域；以及
倒装粘贴至第一基座、第二基座上的芯片，其中，所述芯片包括位于芯片正面的第一电极和第二电极，所述芯片的第一电极与所述多个第一类粘贴区接触并粘贴在一起，所述芯片的第二电极与第二类粘贴区接触并粘贴在一起；
处于同一直线上的第一基座顶面边缘处的横向凹槽和第二基座顶面边缘处的横向凹槽，以及处于同一直线上的第一基座顶面边缘处的纵向凹槽和第二基座顶面边缘处的纵向凹槽，与第一基座顶面边缘处的另一横向凹槽和另一纵向凹槽围绕构成一矩形的周边槽。
2.如权利要求1所述的倒装芯片的半导体器件，其特征在于，所述芯片边缘四周的切割区位于所述周边槽的正上方。
3.如权利要求1所述的倒装芯片的半导体器件，其特征在于，所述芯片还包括位于芯片背面的第三电极，所述第三电极通过键合线进一步电性连接至所述引线座上。
4.如权利要求3所述的倒装芯片的半导体器件，其特征在于，所述芯片为一金属氧化物半导体场效应管，并且所述第一电极为芯片的源极，第二电极为芯片的栅极，位于芯片背面的第三电极为芯片的漏极。
5.一种倒装芯片的半导体器件的制造方法，其特征在于，包括以下步骤：
提供包含多个由第一基座、第二基座及引线座构成的芯片安装单元的引线框架，其中，第一基座的顶面包含多个第一类粘贴区，第二基座的顶面至少包含一个第二类粘贴区；
在第一类粘贴区、第二类粘贴区涂覆导电材料，将一芯片倒装粘贴至第一基座、第二基座上，芯片的第一电极与第一类粘贴区接触并粘贴在一起，芯片的第二电极与第二类粘贴区接触并粘贴在一起；
利用键合线将位于芯片背面的第三电极电性连接至引线座上；
利用塑封料封装所述引线框架、芯片及键合线，然后对所述引线框架及塑封料进行切割用于将以塑封体塑封芯片、键合线、芯片安装单元的封装体分离出来；
其中，第二基座及引线座设置在第一基座附近并均与第一基座分离开，在第一基座的顶面、第二基座的顶面均形成有多条包括横向及纵向的凹槽，位于第一基座的顶面的凹槽将第一基座的顶面分割成包含多个第一类粘贴区的多个区域，位于第二基座的顶面的凹槽将第二基座的顶面分割成至少包含一个第二类粘贴区的多个区域。
6.如权利要求5所述的方法，其特征在于，所述横向及纵向的凹槽是在第一基座、第二基座各自的顶面上进行半刻蚀或模压实现的。
7.如权利要求5所述的方法，其特征在于，处于同一直线上的第一基座顶面边缘处的横向凹槽和第二基座顶面边缘处的横向凹槽，以及处于同一直线上的第一基座顶面边缘处的纵向凹槽和第二基座顶面边缘处的纵向凹槽，与第一基座顶面边缘处的另一横向凹槽和另一纵向凹槽围绕构成一矩形的周边槽。
8.如权利要求7所述的方法，其特征在于，将所述芯片倒装粘贴至第一基座、第二基座上时，所述芯片边缘四周的切割区位于所述周边槽的正上方。
9.如权利要求5所述的方法，其特征在于，所述芯片为一金属氧化物半导体场效应管，并且所述第一电极为芯片的源极，第二电极为芯片的栅极，位于芯片背面的第三电极为芯片的漏极。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6307755B1 (en) * 1999-05-27 2001-10-23 Richard K. Williams Surface mount semiconductor package, die-leadframe combination and leadframe therefor and method of mounting leadframes to surfaces of semiconductor die
US6870254B1 (en) * 2000-04-13 2005-03-22 Fairchild Semiconductor Corporation Flip clip attach and copper clip attach on MOSFET device
CN101473423A (zh) * 2006-05-19 2009-07-01 飞兆半导体公司 双侧冷却集成晶体管模块及制造方法

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Publication number Priority date Publication date Assignee Title
US7598603B2 (en) * 2006-03-15 2009-10-06 Infineon Technologies Ag Electronic component having a power switch with an anode thereof mounted on a die attach region of a heat sink

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6307755B1 (en) * 1999-05-27 2001-10-23 Richard K. Williams Surface mount semiconductor package, die-leadframe combination and leadframe therefor and method of mounting leadframes to surfaces of semiconductor die
US6870254B1 (en) * 2000-04-13 2005-03-22 Fairchild Semiconductor Corporation Flip clip attach and copper clip attach on MOSFET device
CN101473423A (zh) * 2006-05-19 2009-07-01 飞兆半导体公司 双侧冷却集成晶体管模块及制造方法

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