CN101473423A - 双侧冷却集成晶体管模块及制造方法 - Google Patents

双侧冷却集成晶体管模块及制造方法 Download PDF

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CN101473423A
CN101473423A CNA2007800230340A CN200780023034A CN101473423A CN 101473423 A CN101473423 A CN 101473423A CN A2007800230340 A CNA2007800230340 A CN A2007800230340A CN 200780023034 A CN200780023034 A CN 200780023034A CN 101473423 A CN101473423 A CN 101473423A
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transistor
module
intermediate plate
drain
lead frame
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CN101473423B (zh
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乔纳森·A·诺奎尔
鲁宾·P·马德里
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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Priority claimed from US11/740,475 external-priority patent/US7777315B2/en
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    • H01L2924/30107—Inductance

Abstract

一种集成晶体管模块包含引线框，所述引线框具有第一和第二间隔垫、位于所述第一与第二垫之间的一个或一个以上共同源极－漏极引线、以及位于所述第二垫的外侧上的一个或一个以上漏极引线。第一和第二晶体管分别以倒装芯片方式附接到所述第一和第二垫，其中所述第二晶体管的源极电连接到所述一个或一个以上共同源极－漏极引线。第一夹片附接到所述第一晶体管的漏极且电连接到所述一个或一个以上共同源极－漏极引线。第二夹片附接到所述第二晶体管的漏极且电连接到位于所述第二垫的所述外侧上的所述一个或一个以上漏极引线。模制材料囊封所述引线框、所述晶体管和所述夹片以形成所述模块。通过使所述引线框垫和夹片暴露且无模制材料，实现对所述模块的双冷却。

Description

双侧冷却集成晶体管模块及制造方法
本申请案主张2006年5月19日申请的第60/802,181号美国临时专利申请案(所述申请案以引用的方式并入本文中)的权益，并且还主张2007年5月9日申请的第60/916,994号美国临时专利申请案(所述申请案以引用的方式并入本文中)的权益。还参考代理人案号为3021711(17732.62860.00)的题为“倒装芯片MLP折叠散热器(FlipChip MLP Folded Heat Sink)”的相关申请案。
技术领域
本发明大体涉及半导体装置，且更明确地说涉及一种适合用作其它装置(例如，同步降压式转换器)的建置区块的双侧冷却集成晶体管模块及其制造方法。
背景技术
同步降压式转换器用作手机、便携式计算机、数码相机、路由器和其它便携式电子装置的电源。同步降压式转换器使DC电压电平移位以便向可编程栅极阵列集成电路、微处理器、数字信号处理集成电路和其它电路提供功率，同时使电池输出稳定、过滤噪声并减少纹波。这些装置还用于在广范围的数据通信、电信、负载点和计算应用中提供高电流多相功率。
图1展示典型同步降压式转换器的框图。所述转换器具有由PWM IC上的控制器控制的高侧FET Q1和低侧FET Q2。Q1和Q2装置可配置为离散装置，其需要最佳布局以减小由PCB衬底上高侧FET漏极连接到低侧FET源极引起的寄生电感。发明者Joshi等人2005年12月29日公开的第2005/0285238 A1号美国专利申请公开案揭示一种包含界定低侧区和高侧区的引线框的集成晶体管模块。低侧晶体管安装在低侧区，其漏极电连接到低侧区。高侧晶体管安装在高侧区，其源极电连接到高侧区。引线框的阶梯部分电连接低侧区和高侧区，且因此还电连接低侧晶体管的漏极与高侧晶体管的源极。
尽管后一公开的专利申请案的集成晶体管模块可用于其期望的应用，但其某些特征可进行改进。引出脚方面的封装对准在所揭示的设计中很关键，因为两个不同的封装附接到引线框连接器。因为两个不同的封装需要针对所述两个封装以不同的组装工艺进行组装，所以需要更大成本的花费。此外，多个回焊工艺(热偏移)可能影响无引线封装焊接接缝可靠性。其它缺点包含不适当的封装厚度、模块占用面积的商业可接受性，和因为晶体管的一者以倒装芯片方式安装在引线框上而另一者并非如此所以不能连接封装上的共同漏极。
因此，需要一种可用于例如降压式转换器电路等电路中并提供对这些问题的解决方案的改进的集成晶体管模块。
发明内容
根据本发明，提供一种对这些问题的解决方案。
根据本发明的一特征，提供一种集成晶体管模块，其包括：
引线框，其具有第一和第二间隔垫以及位于所述第一与第二垫之间的一个或一个以上共同源极-漏极引线；
第一和第二晶体管，其分别以倒装芯片方式附接到所述第一和第二垫，其中所述第二晶体管的源极电连接到所述一个或一个以上共同源极-漏极引线；以及
第一夹片，其附接到所述第一晶体管的漏极且电连接到所述一个或一个以上共同源极-漏极引线。
根据本发明的另一特征，提供一种集成晶体管模块，其包括：
引线框，其具有第一和第二间隔垫、位于所述第一与第二垫之间的一个或一个以上共同源极-漏极引线，以及位于所述第二垫的外侧上的一个或一个以上漏极引线；
第一和第二晶体管，其分别以倒装芯片方式附接到所述第一和第二垫，其中所述第二晶体管的源极电连接到所述一个或一个以上共同源极-漏极引线；
第一夹片，其附接到所述第一晶体管的漏极且电连接到所述一个或一个以上共同源极-漏极引线；
第二夹片，其附接到所述第二晶体管的漏极且电连接到位于所述第二垫的所述外侧上的所述一个或一个以上漏极引线；以及
模制材料，其囊封所述引线框、所述晶体管和所述夹片以形成所述模块。
根据本发明的又一特征，提供一种制造集成晶体管模块的方法，其包括：
提供引线框，其具有第一和第二间隔垫、位于所述垫之间的一个或一个以上共同源极-漏极引线，以及位于所述第二垫的外侧上的一个或一个以上漏极引线；
将第一和第二晶体管分别以倒装芯片方式附接到所述第一和第二垫，其中所述第二晶体管的源极电连接到所述一个或一个以上共同源极-漏极引线；
将第一夹片附接到所述第一晶体管的漏极且将所述第一夹片电连接到所述一个或一个以上共同源极-漏极引线；
将第二夹片附接到所述第二晶体管的漏极且将所述第二夹片电连接到位于所述第二垫的所述外侧上的所述一个或一个以上漏极引线；以及
用模制材料囊封所述引线框、所述晶体管和所述夹片以形成所述模块。
附图说明
图1是典型降压式转换器电路的示意图。
图2和3是本发明一实施例的俯视平面图和截面立视图。
图4-7是可用于阐释实施例的图1和2的实施例的简图。
图8-10分别是本发明另一实施例的俯视平面图、截面立视图和截面立视简图。
图11和12分别是本发明又一实施例的截面立视简图。
图13和14分别是本发明再一实施例的截面立视简图。
图15-17分别是本发明又一实施例的平面简图。
图18-19分别是本发明中使用的夹片的平面图和立视图。
图20-24是可用于说明本发明的方法实施例的简图。
图25是说明图20-24的方法的修改的简图。
具体实施方式
本发明涉及模块中晶体管的集成，例如将降压式转换器的低侧和高侧功率MOSFET集成到单一模制无引线封装(MLP)中。通过使用功率装置的多倒装，通过使用低侧MOSFET的漏极与高侧MOSFET的源极的电连接的折叠夹片，且通过在MLP中较接近地连接两个MOSFET，实质上减小了电源电阻且使电感寄生效应最小化。通过借助使用特殊漏极夹片暴露两个装置的漏极来改进冷却。通过双侧冷却来进一步改进冷却，因为所述两个装置的源极经由其附接到的引线框而暴露。所述夹片设计还导致焊接接缝可靠性改进。本发明的一实施例通过使用附接的散热器连接两个漏极来提供两个功率装置的隔离以将其转换为具有共同漏极应用的封装。在本发明的另一实施例中，提供专用模块，其中IC(集成电路)(例如，驱动器IC)与两个功率MOSFET集成在具有双冷却的单一MLP中。双侧冷却改进了总体封装热性能，其中包含IC的热性能，因为IC被完全隔离且功率装置具有双侧热耗散。
本发明具有优于现有技术的以下优点。
(1)提供简化的集成晶体管模块，其可将相同的模制工具与当前MLP块模制一起使用，从而不导致显著投资。
(2)晶体管模块引出脚不可变。
(3)工艺简化，因为不存在多个回焊和热暴露。两个晶体管可倒装在一起并用可焊膏附接，且两个漏极夹片联动放置并同时回焊。在组装期间并入漏极和源极连接，从而使工艺缩减。
(4)维持了工艺灵活性，可选择将个别晶体管单一化至功能个别封装中。
(5)使用已知工业占用面积，而不必获得对新占用面积的商业可接受性，从而容易实行市场渗入。
(6)提供顶侧上改进的封装冷却以及双侧冷却。
(7)可在封装本身上连接共同漏极。
现参看图2和3，其展示本发明的一实施例。如图所示，集成晶体管模块10包含经蚀刻的引线框11、低侧晶体管12和高侧晶体管14、夹片16和18；全部均由模制材料20囊封在单一模具中。如图4所示，引线框11经半蚀刻且包含间隔的源极垫22和24、位于源极垫22的外侧上的低侧栅极引线26和低侧源极引线28、位于垫22与24之间的高侧栅极引线30和共同源极-漏极引线32，以及位于源极垫24的外侧上的高侧漏极引线34。在一个实施例中，晶体管12和14是在晶体管电路小片的各自相对侧上具有源极和漏极的功率MOSFET。根据本发明，两个晶体管12和14以倒装芯片方式通过焊球36附接到引线框11。因此，晶体管12的源极附接到源极垫22，晶体管14的栅极附接到低侧栅极引线26，且晶体管14的源极附接到源极垫24，晶体管14的栅极附接到高侧栅极引线30。
如图3-5所示，夹片16具有一平坦部件40和若干向下延伸引线42。夹片18在构造上类似且包含一平坦部件44和若干向下延伸引线46。夹片16和18由例如铜、铝或导电聚合物等导电材料制成。夹片16具有的引线比夹片18少一个，因为夹片16不与高侧栅极引线30形成任何连接。夹片引线42电连接到共同源极-漏极引线32，且夹片引线46与高侧漏极引线34电连接。
图6展示模块10的顶侧以及暴露的夹片16和18。图7展示模块10的底侧以及暴露的源极垫22和24。双暴露实现增加的冷却以及对模块10的较好热管理。
现参看图8-10，展示本发明的另一实施例。所述设计类似于先前实施例，但提供以下选择：通过在线60处切割模块超过低侧夹片16到共同源极-漏极引线32的电连接而将模块分离为两个个别晶体管封装。如图8所示，共同源极-漏极引线分离为低侧漏极引线62和高侧源极引线64。
图11和12展示本发明的另一实施例，其中集成晶体管模块10′具有引线框11′，其引线70从任一侧延伸以适应有引线封装占用面积。图11的有引线封装可通过在线72和74处切割模块的引线部分而转换为无引线封装。
图13和14所示的实施例展示集成晶体管模块，其可将共同漏极连接到模块的两个晶体管。如图所示，模块11＂在区域80处经部分锯切以使一个晶体管的漏极与另一晶体管的源极断开。散热器90附接到模块的顶侧以连接漏极夹片。
现参看图15-17，展示用于特定应用设计的本发明的实施例，其中IC与两个晶体管一起集成到模块中。如图所示，模块100包含与低侧FET104和高侧FET106集成的驱动器IC102。所述FET配置与图1和2的实施例相同，其中源极-漏极连接108相同，且由FET 104和106通过漏极夹片的顶侧暴露以及所有三个装置通过引线框的底侧暴露两者提供的双冷却相同。
图18和19展示封装夹片设计。如图所示，夹片16和18以系杆排列在一起以将夹片固持在一起。夹片接着可被联动切割以与模块的其它组件组装。如图19所示，夹片16、18具有凹槽以改进焊料附接。
图20-24展示本发明的方法的实施例，图20展示提供经半蚀刻的引线框作为工艺中的初始步骤。图21展示下一步骤：通过回焊焊膏将晶体管12和14以倒装芯片方式附接到引线框11。图22展示分别将夹片16和18联动附接到晶体管12和14，并进行回焊。图23展示在模块无引线的情况下进行块模制，且在模块有引线的情况下进行单一化模制。图24展示个别模块10的单一化和测试。
图25展示所述方法的修改，其中个别晶体管模块200从双晶体管模块10单一化。
已具体参考本发明的某些优选实施例详细描述本发明，但将了解，可在本发明的精神和范围内实行变化和修改。

Claims (21)

1.一种集成晶体管模块，其包括：
引线框，其具有第一和第二间隔垫以及位于所述第一与第二垫之间的一个或一个以上共同源极-漏极引线；
第一和第二晶体管，其分别以倒装芯片方式附接到所述第一和第二垫，其中所述第二晶体管的源极电连接到所述一个或一个以上共同源极-漏极引线；以及
第一夹片，其附接到所述第一晶体管的漏极且电连接到所述一个或一个以上共同源极-漏极引线。
2.根据权利要求1所述的模块，其中所述第一和第二晶体管是金属氧化物半导体场效应晶体管(MOSFET)。
3.根据权利要求1所述的模块，其中所述第一和第二晶体管分别是作为降压式转换器的组件的高侧和低侧功率晶体管。
4.根据权利要求1所述的模块，其中所述引线框包含位于所述第二垫的外侧上的一个或一个以上漏极引线，且所述模块包含第二夹片，所述第二夹片附接到所述第二晶体管的漏极且电连接到位于所述第二垫的所述外侧上的所述一个或一个以上漏极引线。
5.根据权利要求1所述的模块，其中所述引线框、所述晶体管和所述夹片囊封在模制材料中，所述引线框的所述垫和所述夹片经暴露以提供对所述模块的双冷却。
6.一种集成晶体管模块，其包括：
引线框，其具有第一和第二间隔垫、位于所述第一与第二垫之间的一个或一个以上共同源极-漏极引线，以及位于所述第二垫的外侧上的一个或一个以上漏极引线；
第一和第二晶体管，其分别以倒装芯片方式附接到所述第一和第二垫，其中所述第二晶体管的源极电连接到所述一个或一个以上共同源极-漏极引线；
第一夹片，其附接到所述第一晶体管的漏极且电连接到所述一个或一个以上共同源极-漏极引线；
第二夹片，其附接到所述第二晶体管的漏极且电连接到位于所述第二垫的所述外侧上的所述一个或一个以上漏极引线；以及
模制材料，其囊封所述引线框、所述晶体管和所述夹片以形成所述模块。
7.根据权利要求6所述的模块，其中使所述引线框的所述垫和所述夹片暴露且无所述模制材料以提供对所述模块的双冷却。
8.根据权利要求6所述的模块，其中所述第一和第二晶体管是金属氧化物半导体场效应晶体管(MOSFET)。
9.根据权利要求6所述的模块，其中所述第一和第二晶体管分别是作为降压式转换器的组件的高侧和低侧功率晶体管。
10.根据权利要求6所述的模块，其中所述一个或一个以上共同源极-漏极引线经配置以被切割使得可形成两个个别单一晶体管封装。
11.根据权利要求6所述的模块，其中所述引线框具有处于所述第一与第二垫之间的栅极引线，且其中所述第一夹片不电附接到所述栅极引线。
12.根据权利要求6所述的模块，其中所述第一夹片具有一平坦部件和若干电连接到所述引线框的所述共同源极-漏极引线的向下延伸引线；且其中所述第二夹片具有一平坦部件和若干电连接到位于所述第二垫的所述外侧上的所述引线框的所述一个或一个以上漏极引线的向下延伸引线。
13.根据权利要求12所述的模块，其中所述引线框具有处于所述第一与第二垫之间的栅极引线，且其中所述第一夹片不具有将电连接到所述栅极引线的向下延伸引线。
14.根据权利要求6所述的模块，其中所述引线框经配置以具有有引线占用面积，所述有引线占用面积可通过切割所述模块的引线部分而转换为无引线模块。
15.根据权利要求6所述的模块，其中所述共同源极-漏极引线经部分切断以断开所述连接，且其中共同散热器附接到所述第一和第二夹片并连接所述第一和第二夹片。
16.根据权利要求6所述的模块，其包含附接到所述引线框并电连接到所述第一和第二晶体管的集成电路，所述集成电路由所述模制材料囊封以形成单一模块。
17.一种制造集成晶体管模块的方法，其包括：
提供引线框，其具有第一和第二间隔垫、位于所述垫之间的一个或一个以上共同源极-漏极引线，以及位于所述第二垫的外侧上的一个或一个以上漏极引线；
将第一和第二晶体管分别以倒装芯片方式附接到所述第一和第二垫，其中所述第二晶体管的源极电连接到所述一个或一个以上共同源极-漏极引线；
将第一夹片附接到所述第一晶体管的漏极且将所述第一夹片电连接到所述一个或一个以上共同源极-漏极引线；
将第二夹片附接到所述第二晶体管的漏极且将所述第二夹片电连接到位于所述第二垫的所述外侧上的所述一个或一个以上漏极引线；以及
用模制材料囊封所述引线框、所述晶体管和所述夹片以形成所述模块。
18.根据权利要求17所述的方法，其中使所述引线框的所述垫和所述夹片暴露且无所述模制材料以提供对所述模块的双冷却。
19.根据权利要求17所述的方法，其中所述第一和第二晶体管是金属氧化物半导体场效应晶体管(MOSFET)。
20.根据权利要求17所述的方法，其中所述第一和第二晶体管分别是作为降压式转换器的组件的高侧和低侧功率晶体管。
21.一种功率方形扁平无引线封装，其具有带有折叠接线柱的暴露的顶部热漏极夹片和暴露的热源极垫。
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