WO2007137221A3 - Dual side cooling integrated transistor module and methods of manufacture - Google Patents

Dual side cooling integrated transistor module and methods of manufacture Download PDF

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Publication number
WO2007137221A3
WO2007137221A3 PCT/US2007/069362 US2007069362W WO2007137221A3 WO 2007137221 A3 WO2007137221 A3 WO 2007137221A3 US 2007069362 W US2007069362 W US 2007069362W WO 2007137221 A3 WO2007137221 A3 WO 2007137221A3
Authority
WO
WIPO (PCT)
Prior art keywords
drain
pads
transistor
manufacture
methods
Prior art date
Application number
PCT/US2007/069362
Other languages
French (fr)
Other versions
WO2007137221A2 (en
Inventor
Jonathan A Noquil
Ruben P Madrid
Original Assignee
Fairchild Semiconductor
Jonathan A Noquil
Ruben P Madrid
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/740,475 external-priority patent/US7777315B2/en
Application filed by Fairchild Semiconductor, Jonathan A Noquil, Ruben P Madrid filed Critical Fairchild Semiconductor
Priority to KR1020087028221A priority Critical patent/KR101157305B1/en
Priority to CN2007800230340A priority patent/CN101473423B/en
Priority to DE112007001240T priority patent/DE112007001240T5/en
Priority to JP2009511260A priority patent/JP2009545862A/en
Publication of WO2007137221A2 publication Critical patent/WO2007137221A2/en
Publication of WO2007137221A3 publication Critical patent/WO2007137221A3/en

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Dc-Dc Converters (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

An integrated transistor module including a lead frame having first and second spaced pads, one or more common source-drain leads located between the first and second pads, and one or more drain leads located on the outside of the second pad. First and second transistors are flip chip attached respectively to the first and second pads, wherein the source of the second transistor is electrically connected to the one or more common source-drain leads. A first clip is attached to the drain of the first transistor and electrically connected to the one or more common source-drain leads. A second clip is attached to the drain of the second transistor and electrically connected to the one or more drain leads located on the outside of the second pad. Molding material encapsulates the lead frame, the transistors, and the clips to form the module. By leaving the lead frame pads and clips exposed and free of molding material, dual cooling of the module is effected.
PCT/US2007/069362 2006-05-19 2007-05-21 Dual side cooling integrated transistor module and methods of manufacture WO2007137221A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020087028221A KR101157305B1 (en) 2006-05-19 2007-05-21 Dual side cooling integrated transistor module and methodes of manufacture
CN2007800230340A CN101473423B (en) 2006-05-19 2007-05-21 Dual side cooling integrated transistor module and methods of manufacture
DE112007001240T DE112007001240T5 (en) 2006-05-19 2007-05-21 Integrated transistor module with double-sided cooling and method of manufacture
JP2009511260A JP2009545862A (en) 2006-05-19 2007-05-21 Two-surface cooling integrated transistor module and manufacturing method thereof

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US80218106P 2006-05-19 2006-05-19
US60/802,181 2006-05-19
US11/740,475 2007-04-26
US11/740,475 US7777315B2 (en) 2006-05-19 2007-04-26 Dual side cooling integrated power device module and methods of manufacture
US91699407P 2007-05-09 2007-05-09
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5822468B2 (en) * 2011-01-11 2015-11-24 ローム株式会社 Semiconductor device
CN102832190B (en) * 2011-06-14 2015-02-04 万国半导体股份有限公司 Semiconductor device with flip chip and manufacturing method of semiconductor device
WO2013157172A1 (en) * 2012-04-20 2013-10-24 パナソニック株式会社 Semiconductor package and method for producing same, semiconductor module, and semiconductor device
US9355942B2 (en) * 2014-05-15 2016-05-31 Texas Instruments Incorporated Gang clips having distributed-function tie bars
US10438900B1 (en) * 2018-03-29 2019-10-08 Alpha And Omega Semiconductor (Cayman) Ltd. HV converter with reduced EMI
US20210082790A1 (en) * 2019-09-18 2021-03-18 Alpha And Omega Semiconductor (Cayman) Ltd. Power semiconductor package having integrated inductor and method of making the same
US11309233B2 (en) * 2019-09-18 2022-04-19 Alpha And Omega Semiconductor (Cayman), Ltd. Power semiconductor package having integrated inductor, resistor and capacitor
CN113410185B (en) * 2021-06-04 2021-12-14 深圳真茂佳半导体有限公司 Power semiconductor device packaging structure and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6849942B2 (en) * 2003-03-11 2005-02-01 Siliconware Precision Industries Co., Ltd. Semiconductor package with heat sink attached to substrate
US20050280163A1 (en) * 2004-06-03 2005-12-22 International Rectifier Corp. Semiconductor device module with flip chip devices on a common lead frame
US20060186551A1 (en) * 2005-02-23 2006-08-24 Texas Instruments Incorporated Flip chip package with advanced electrical and thermal properties for high current designs

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5877555A (en) * 1996-12-20 1999-03-02 Ericsson, Inc. Direct contact die attach
JP4173751B2 (en) * 2003-02-28 2008-10-29 株式会社ルネサステクノロジ Semiconductor device
JP2005217072A (en) * 2004-01-28 2005-08-11 Renesas Technology Corp Semiconductor device
JP2006073655A (en) * 2004-08-31 2006-03-16 Toshiba Corp Semiconductor module
US7504733B2 (en) * 2005-08-17 2009-03-17 Ciclon Semiconductor Device Corp. Semiconductor die package
US20070132073A1 (en) * 2005-12-09 2007-06-14 Tiong Toong T Device and method for assembling a top and bottom exposed packaged semiconductor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6849942B2 (en) * 2003-03-11 2005-02-01 Siliconware Precision Industries Co., Ltd. Semiconductor package with heat sink attached to substrate
US20050280163A1 (en) * 2004-06-03 2005-12-22 International Rectifier Corp. Semiconductor device module with flip chip devices on a common lead frame
US20060186551A1 (en) * 2005-02-23 2006-08-24 Texas Instruments Incorporated Flip chip package with advanced electrical and thermal properties for high current designs

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