TWI452662B - 雙邊冷卻整合電源裝置封裝與模組及製造方法 - Google Patents
雙邊冷卻整合電源裝置封裝與模組及製造方法 Download PDFInfo
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- TWI452662B TWI452662B TW096117812A TW96117812A TWI452662B TW I452662 B TWI452662 B TW I452662B TW 096117812 A TW096117812 A TW 096117812A TW 96117812 A TW96117812 A TW 96117812A TW I452662 B TWI452662 B TW I452662B
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- module
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- transistor
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- lead frame
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- 238000001816 cooling Methods 0.000 title claims description 19
- 238000000034 method Methods 0.000 title claims description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 230000009977 dual effect Effects 0.000 title claims 7
- 239000012778 molding material Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims 3
- 229910044991 metal oxide Inorganic materials 0.000 claims 3
- 150000004706 metal oxides Chemical class 0.000 claims 3
- 238000005538 encapsulation Methods 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 230000001360 synchronised effect Effects 0.000 description 8
- 230000002146 bilateral effect Effects 0.000 description 7
- 239000002184 metal Substances 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
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Description
本發明一般係關於半導體裝置之封裝,且更特定言之係關於雙邊冷卻整合電源裝置模組及其製造方法。
具有共同高電流輸入或輸出終端之兩個電源裝置的配置可在諸如同步降壓轉換器之電路內找到。同步降壓轉換器通常用作行動電話、可攜式電腦、數位相機、刻紋機及其他可攜式電子裝置之電源供應器。同步降壓轉換器偏移直流電壓位準,以便為可程式化格柵陣列積體電路、微處理器、數位信號處理積體電路及其他電路提供電力,同時穩定電池輸出、濾除雜訊並減小紋波(ripple)。該等裝置亦用於在廣泛的資料通信、電信、負載點及計算應用中提供高電流多相電力。
圖1顯示典型同步降壓轉換器10之方塊圖。轉換器具有藉由脈衝寬度調變(pulse width modulation;PWM)IC 16驅動之高邊FET 12及低邊FET 14。可將Q1及Q2裝置12、14組態為離散裝置,其需要最佳佈局以減小因印刷電路板(printed circuit board;PCB)上高邊FET 12之源極與低邊FET 14之汲極的連接引起之寄生電阻18及電感20。
2005年12月29日公開的美國專利申請公開案第2005/0285238 A1號,發明人為Joshi等人,揭示一種整合電晶體模組,其包括界定低邊平台及高邊平台之引線框架。將低邊電晶體黏著於低邊平台上,使該低邊電晶體之汲極電連接至低邊平台。將高邊電晶體黏著於高邊平台上,使該高邊電晶體之源極電連接至高邊平台。引線框架之階梯狀部分電連接低邊及高邊平台,從而亦連接低邊電晶體之汲極與高邊電晶體之源極。
儘管後來公開之專利申請案的整合電晶體模組對期望的應用很有用,但模組腳位(footprint)在業界並不常用。
因此,需要一種改良之整合電源裝置模組,其可用於對此等問題提供解決方案之電路內,例如同步降壓轉換器電路。
依據本發明,為此等問題提供一解決方案。
依據本發明之一特徵,提供一整合電源裝置模組,其包含:一引線框架,其具有間隔的第一及第二墊及位於該第一與該第二墊之間之一或多個共同源極汲極引線;第一及第二電晶體,其係分別採用覆晶方式附著於該第一及該第二墊,其中將該第二電晶體之源極電連接至該一或多個共同源極汲極引線;以及一第一夾具,其係附著於該第一電晶體之汲極,並電連接至該一或多個共同源極汲極引線。
依據本發明之另一特徵,提供一整合電源裝置模組,其包含:一引線框架,其具有間隔的第一及第二墊、位於該第一與該第二墊之間之一或多個共同源極汲極引線以及位於該
第二墊外部的一或多個汲極引線;第一及第二電晶體,其係分別採用覆晶方式附著於該第一及該第二墊,其中將該第二電晶體之源極電連接至該一或多個共同源極汲極引線;一第一夾具,其係附著於該第一電晶體之汲極,並電連接至該一或多個共同源極汲極引線;一第二夾具,其係附著於該第二電晶體之汲極,並電連接至位於該第二墊外部的該一或多個汲極引線;以及模製材料,其囊封該引線框架、該等電晶體及該等夾具,以形成該模組。
依據本發明之另一特徵,提供一種製作整合電源裝置模組之方法,其包含:提供一引線框架,該引線框架具有間隔的第一及第二墊、位於該等墊之間之一或多個共同源極汲極引線以及位於該第二墊外部的一或多個汲極引線;分別採用覆晶方式將第一及第二電晶體附著於該等第一及第二墊,其中將該第二電晶體之源極電連接至該一或多個共同源極汲極引線;將一第一夾具附著於該第一電晶體之汲極,並將該第一夾具電連接至該一或多個共同源極汲極引線;將一第二夾具附著於該第二電晶體之汲極,並將該第二夾具電連接至位於該第二墊外部的該一或多個汲極引線;以及採用模製材料囊封該引線框架、該等電晶體及該等夾具,以形成該模組。
圖2A係依據本發明之一項具體實施例用於形成雙邊冷卻整合電源裝置模組之類型的兩個引線框架32及34之平面圖30。引線框架32、34具有如圖2A至2C內所示之連接桿36,且其係在囊封作業後的單切分離(singulated)程序中予以移除,為了避免混亂,在其他圖式中未顯示。連接桿使引線框架32、34可得以成套放置,並製造成一捲盤。如圖2B所示,將焊錫膏38塗敷於引線框架32、34之引線,其可焊接至兩個夾具40及42,並將兩個電源裝置44及46翻轉及分別放置於引線框架32及34上。在晶片製造期間用焊料塗布電源裝置44、46。圖2C中,將兩個夾具40、42分別放置於引線框架32、34及電源裝置44、46上,並加熱模組以將電源裝置44、46接合至引線框架32、34,以及將焊錫膏分別回焊至引線框架32、34之適當引線上以及電源裝置44、46之後側上。出於簡化說明目的,下文電源裝置44、46將稱為MOSFET 44、46,儘管本發明並不限於或僅限於MOSFET。例如,橫跨FET 12及14之源極及汲極之二極體也可能係電源裝置44及46之部分。
從圖2B可看出,分別將引線48及50連接至MOSFET 44、46之個別閘極,並且在單切分離程序後將此等引線與個別引線框架32、34之剩餘部分電絕緣。未連接至引線48或50的引線框架32、34之部分係分別連接至MOSFET 44、46之源極。MOSFET 44、46之汲極係分別焊接至夾具40、42。
夾具40、42具有平坦部件52及複數個向下延伸引線54,其係在回焊程序期間採用焊錫膏38焊接至引線。因此MOSFET 44之源極係藉由夾具40連接至MOSFET 46之汲極。
圖3A、3B及3C係整合電源裝置模組66之個別俯視平面圖60、斷面側視圖62及仰視平面圖64,該模組66係採用囊封材料68(例如環氧化物)予以部分囊封的圖2C內所示之結構。圖3B之斷面圖係沿圖3A之線3B-3B截取。圖3A中,將平坦部件52曝露於模組66之頂部。如圖3C所示,模組66之底部沿曝露之源極墊78及80(其係引線框架32、34之部分)具有一行引線平台72、74及76。將引線82、84及86連接至MOSFET 44之源極,如同源極墊78。引線88、90及92係MOSFET 44之汲極與MOSFET 46之源極的共同連接,並藉由夾具42將引線94、96、98及100連接至MOSFET 46之射極。
藉由取代兩個離散FET 12及14,模組66適合用於圖1之同步降壓轉換器10,即藉由MOSFET 44取代FET 12且藉由MOSFET 46取代FET 14的模組66。藉由使用模組66,同時夾具40提供低邊MOSFET 44之汲極與高邊MOSFET 46之源極的電連接,兩個MOSFET 44、46實體上更接近在一起,並且實質上減小了寄生電阻18及電感20。此外,藉由頂部表面未囊封的夾具40、42之固有散熱特性改善電源FET之冷卻。藉由雙邊冷卻進一步改善冷卻,此係因為兩個裝置之源極係經由與其附著的引線框架加以曝露。形成模組66
之方法亦產生改良之焊接合可靠性,因為需要單一焊料回焊,而非多重焊料回焊。
圖4A、4B及4C係依據本發明之另一具體實施例的雙邊冷卻整合電源裝置模組102之仰視平面圖及側視斷面圖。圖4A之仰視平面圖顯示四行引線平台106、108、110及112以及源極墊114及116。當製造模組102時,如圖4B及4C所示將行108及110內之引線連接在一起,但設計成可藉由沿圖4B及4C內所示之線118切斷模組102,從而分離行108內之引線與行110內之引線,將模組102分割成兩個分離單一電源裝置模組。圖4B及4C之斷面圖分別係沿圖4A內之線4B-4B及4C-4C截取。圖4C中,引線平台120、122及124係用於MOSFET 36、38之閘極平台。若沿線118分割模組102,引線平台122將變得絕緣。
圖5係依據本發明之另一具體實施例的引線式雙邊冷卻整合電源裝置模組140之斷面側視圖。模組140具有外部引線142,其與模組140之末端的平台墊144整合。如同先前具體實施例,將平台墊144曝露於模組140之底部,但藉由向上步進(stepping)至在模組140之底部平面上方退出模組140之末端的第一水平區段146而從囊封材料延伸出去,然後向下步進至第二水平區段148,以與模組140之底部平面大致對齊。此引線式模組140因此可容納引線式封裝腳位。可藉由在線150及152處切除模組140之末端部分而移除外部引線142,以形成無引線模組。
圖6A及6B係依據本發明之另一具體實施例形成雙邊冷卻整合電源裝置模組164的圖4C內所示之模組的修改之個別斷面側視圖160及162,其中將兩個MOSFET 36及38之汲極連接在一起以形成共同汲極。圖6A中,在引線框架168內完成一切鋸切口166,以將MOSFET 36及38絕緣。圖6B中,將電及熱傳導散熱座170附著於夾具44、46之平坦部件54,以形成共同汲極連接。
圖7A、7B及7C分別係依據本發明之另一具體實施例的雙邊冷卻整合電源裝置模組180之俯視平面圖、部分斷面俯視平面圖及仰視平面圖,該模組包括用於驅動兩個MOSFET 44、46之控制IC 182,該等MOSFET分別具有定製之夾具184及186,以便將MOSFET 44之汲極連接至MOSFET 46之源極,以及為MOSFET 44、46提供冷卻。圖7A係顯示曝露於模組180之頂部內的夾具184、186的個別平坦部件188及190之俯視平面圖。如圖7C所示,模組180具有三行引線平台192、194及196,其末端引線平台延伸超過囊封材料198之末端。圖7B係模組180之部分斷面圖內的俯視平面圖。控制IC 182具有複數個導線接合200,其接合至行192內之某些引線平台以及接合至MOSFET 46之閘極及源極。為說明本發明之靈活性,夾具184、186之形狀及模組180之腳位不同於前述模組之任何一者。
圖8A係金屬板200之俯視圖,其顯示需要使用熟知之作業從用於本發明之具體實施例之一的金屬框架衝孔之四個夾具202的輪廓。因此,可將夾具202成套放置並製造成一捲盤。圖8B係已從圖8A內所示之金屬板衝出並形成為圖3B內所用的夾具之兩個夾具202的側視圖。如圖8B所示,夾具202具有形成於其中之溝渠204,以改善焊料附著。
圖9A係複數個部分囊封模組212之組塊鑄模210的俯視平面圖。在圖5所示之引線式模組140的模製情形中,將模組140形成為已單切分離的鑄模。圖9B係已從組塊鑄模210單切分離圖3A至3C內所示之囊封模組66後的模組之類型的仰視圖。應明白,可在組塊鑄模210內形成無引線模組之任何一者。
已經特別參考特定較佳具體實施例來詳細說明本發明,但應瞭解,可在本發明之精神及範疇內實施變更及修改。
10...同步降壓轉換器
12...高邊FET
14...低邊FET
16...脈衝寬度調變IC
18...寄生電阻
20...電感
32...引線框架
34...引線框架
36...連接桿
38...焊錫膏
40...夾具
42...夾具
44...電源裝置
46...電源裝置
48...引線
50...引線
52...平坦部件
54...向下延伸引線
66...整合電源裝置模組/囊封模組
68...囊封材料
72...引線平台
74...引線平台
76...引線平台
78...源極墊
80...源極墊
82...引線
84...引線
86...引線
88...引線
90...引線
92...引線
94...引線
96...引線
98...引線
100...引線
102...雙邊冷卻整合電源裝置模組
106...引線平台
108...引線平台
110...引線平台
112...引線平台
114...源極墊
116...源極墊
120...引線平台
122...引線平台
124...引線平台
140...引線式雙邊冷卻整合電源裝置模組
142...外部引線
144...平台墊
146...第一水平區段
148...第二水平區段
164...雙邊冷卻整合電源裝置模組
166...切鋸切口
168...引線框架
170...電及熱傳導散熱座
180...雙邊冷卻整合電源裝置模組
182...控制IC
184...夾具
186...夾具
188...平坦部件
190...平坦部件
192...引線平台
194...引線平台
196...引線平台
198...囊封材料
200...導線接合
202...夾具
204...溝渠
210...組塊鑄模
212...部分囊封模組
結合附圖之上述詳細說明,可更佳地瞭解前述及其他特徵、特性、優點及本發明之整體,其中:圖1係一典型同步降壓轉換器電路之示意圖;圖2A係依據本發明之一項具體實施例用於形成雙邊冷卻整合電源裝置模組之類型的兩個引線框架之平面圖;圖2B係圖2A內所示之引線框架依據本發明之一項具體實施例將電晶體晶粒接合至該等引線框架的平面圖;圖2C係圖2A之引線框架依據本發明之一項具體實施例將兩個冷卻晶片附著於圖2A內所示之引線框架及圖2B內所示之電晶體晶粒的平面圖;圖3A、3B及3C分別係已將圖2C內所示之結構部分地裝入囊封材料內後的俯視平面圖、斷面側視圖及仰視平面圖;圖4A係依據本發明之另一具體實施例的雙邊冷卻整合電源裝置模組之仰視平面圖;圖4B係圖4A內所示之模組的一項具體實施例之斷面側視圖;圖4C係圖4A內所示之模組的另一具體實施例之斷面側視圖;圖5係依據本發明之另一具體實施例的引線式雙邊冷卻整合電源裝置模組之斷面側視圖;圖6A及6B係依據本發明之另一具體實施例用於形成雙邊冷卻整合電源裝置模組的圖4C內所示之模組的修改之斷面側視圖;圖7A、7B及7C分別係依據本發明之另一具體實施例具有用於驅動兩個電源裝置之控制IC的雙邊冷卻整合電源裝置模組之俯視平面圖、部分斷面俯視平面圖及仰視平面圖;圖8A係金屬板之俯視圖,其顯示從用於本發明之具體實施例之一的金屬框架衝孔之四個夾具的輪廓;圖8B係已從圖8A內所示之金屬板衝出並形成為圖3B內所用的夾具之兩個夾具的側視圖;圖9A係複數個部分囊封模組之組塊鑄模的俯視平面圖;以及圖9B係圖9A內所示之囊封模組的一類型在予以單切分離後之仰視圖。
應明白,出於清楚目的,且在認為適當處,圖式中重複參考數字以指示對應特徵。同樣,為更清楚地顯示本發明,圖式中各種物件的相對大小在某些情形下係不符實際大小的。
32...引線框架
34...引線框架
36...連接桿
Claims (20)
- 一種整合電晶體模組,其包含:一平坦引線框架,其具有間隔的第一及第二墊及位於該第一與該第二墊間之一或多個共同源極汲極引線;各自具有源極、閘極及汲極電極之第一及第二電晶體,其分別附著於該第一及該第二墊的頂部表面,其中將該第二電晶體之源極電極電連接至該一或多個共同源極汲極引線;以及一第一夾具,其具有一平坦部件及複數個向下延伸引線,其係附著於該第一電晶體之汲極電極,並電連接至該一或多個共同源極汲極引線;其中該引線框架、該等電晶體及該第一夾具係部份囊封於模製材料內,該第一與該第二墊之每一者之底部表面的一部分與該夾具之該平坦部件經暴露以提供該模組之雙重冷卻。
- 如請求項1之模組,其中該第一及該第二電晶體係金屬氧化物半導體場效電晶體(MOSFET)。
- 如請求項1之模組,其中該第一及該第二電晶體分別係高邊及低邊電源電晶體,其係一降壓轉換器之組件。
- 如請求項1之模組,其中該引線框架包括位於該第二墊外部之一或多個汲極引線,並包括一第二夾具,該第二夾具附著於該第二電晶體之汲極且電連接至位於該第二墊外部之該一或多個汲極引線。
- 如請求項1之模組,其中將該引線框架、該等電晶體及 該夾具部份地囊封於模製材料內,曝露該引線框架之該等墊及該夾具以提供該模組之雙重冷卻。
- 一種整合電晶體模組,其包含:一平坦引線框架,其具有間隔的第一及第二墊、位於該第一與該第二墊間之一或多個共同源極汲極引線以及位於該第二墊外部的一或多個汲極引線;第一及第二電晶體,其分別附著於該第一及該第二墊之頂部表面,其中將該第二電晶體之源極電連接至該一或多個共同源極汲極引線;一第一夾具,其具有一平坦部件及複數個向下延伸引線,其係附著於該第一電晶體之汲極,並電連接至該一或多個共同源極汲極引線;一第二夾具,其係附著於該第二電晶體之汲極,並電連接至位於該第二墊外部的該一或多個汲極引線;以及模製材料,其部分地封裝該引線框架、該等電晶體及該等夾具,以形成該模組,該第一與該第二墊之每一者之底部表面的一部分與該夾具之該平坦部件經暴露以提供該模組之雙重冷卻。
- 如請求項6之模組,其中該第一及該第二電晶體係金屬氧化物半導體場效電晶體(MOSFET)。
- 如請求項6之模組,其中該第一及該第二電晶體分別係高邊及低邊電源電晶體,其係一降壓轉換器之組件。
- 如請求項6之模組,其中該一或多個共同源極汲極引線係組態成予以切割,以便可形成兩個個別單一電晶體封 裝。
- 如請求項6之模組,其中該引線框架具有介於該第一與該第二墊間之一閘極引線,並且其中未將該第一夾具電附著於該閘極引線。
- 如請求項6之模組,其中該第二夾具具有一平坦部件及複數個向下延伸引線,其係電連接至位於該第二墊外部之該引線框架的該一或多個汲極引線。
- 如請求項11之模組,其中該引線框架具有介於該第一與該第二墊間之一閘極引線,並且其中該第一夾具不具有電連接至該閘極引線的向下延伸引線。
- 如請求項6之模組,其中該引線框架係組態成具有一引線式腳位,其可藉由切除該模組之引線部分而轉換為一無引線模組。
- 如請求項6之模組,其中部分地切斷該等共同源極汲極引線以斷開連接,並且其中一共同散熱座經附著並連接至該等第一及第二夾具。
- 如請求項6之模組,其包括附著於該引線框架並電連接至該等第一及第二電晶體之一積體電路,該積體電路係藉由該模製材料加以囊封以形成一單一模組。
- 一種整合電晶體模組,其包含:一平坦引線框架,其具有間隔的第一及第二墊、位於該第一與該第二墊間之一或多個共同源極汲極引線以及位於該第二墊外部的一或多個汲極引線;第一及第二電晶體,各自具有一在一表面上之源極電 極與一在另一表面之汲極電極,該第一及該第二源極電極分別附著於該第一及該第二源極墊之表面,其中該第二電晶體之源極係電連接至該一或多個共同源極汲極引線;一第一汲極夾具,其具有附著於該第一電晶體之該汲極電極之一平坦部件,及電連接至該一或多個共同源極汲極引線之複數個向下延伸引線;一第二汲極夾具,其具有附著於該第二電晶體之該汲極電極之一平坦部件,及延伸自該平坦部件並位於該第二墊外部之一或多個汲極引線;以及模製材料,其部分地封裝該引線框架、該等電晶體及該等夾具,以形成該模組,該第一與該第二源極墊之每一者之底部表面的一部分與該等汲極夾具之該等平坦部件經暴露以提供該模組之雙重冷卻。
- 一種製造一整合電晶體模組之方法,其包含:提供一平坦引線框架,該引線框架具有間隔的第一及第二墊、位於該等墊之間之一或多個共同源極汲極引線以及位於該第二墊外部的一或多個汲極引線;分別採用覆晶方式將第一及第二電晶體附著於該第一及該第二墊,每一電晶體具有源極、閘極及汲極電極,其中將該第二電晶體之源極電連接至該一或多個共同源極汲極引線;將一第一夾具附著於該第一電晶體之汲極,並將該第一夾具電連接至該一或多個共同源極汲極引線,該第一 夾具具有一平坦部件;將一第二夾具附著於該第二電晶體之汲極,並將該第二夾具電連接至位於該第二墊外部的該一或多個汲極引線,該第二夾具具有一平坦部件;以及在模製材料中部分地囊封該平坦引線框架、該等電晶體及該等夾具,該第一與該第二墊之每一者之底部表面的一部分與該等夾具之該等平坦部件經暴露以提供該整合電晶體模組之雙重冷卻。
- 如請求項17之方法,其中曝露該引線框架之該等墊及該等夾具且其不含模製材料,以提供該模組之雙重冷卻。
- 如請求項17之方法,其中該第一及該第二電晶體係金屬氧化物半導體場效電晶體(MOSFET)。
- 如請求項17之方法,其中該第一及該第二電晶體分別係高邊及低邊電源電晶體,其係一降壓轉換器之組件。
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WO2013157172A1 (ja) * | 2012-04-20 | 2013-10-24 | パナソニック株式会社 | 半導体パッケージ及びその製造方法、半導体モジュール、並びに半導体装置 |
US9355942B2 (en) * | 2014-05-15 | 2016-05-31 | Texas Instruments Incorporated | Gang clips having distributed-function tie bars |
US10438900B1 (en) * | 2018-03-29 | 2019-10-08 | Alpha And Omega Semiconductor (Cayman) Ltd. | HV converter with reduced EMI |
US20210082790A1 (en) * | 2019-09-18 | 2021-03-18 | Alpha And Omega Semiconductor (Cayman) Ltd. | Power semiconductor package having integrated inductor and method of making the same |
US11309233B2 (en) * | 2019-09-18 | 2022-04-19 | Alpha And Omega Semiconductor (Cayman), Ltd. | Power semiconductor package having integrated inductor, resistor and capacitor |
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US7301235B2 (en) * | 2004-06-03 | 2007-11-27 | International Rectifier Corporation | Semiconductor device module with flip chip devices on a common lead frame |
US7476976B2 (en) * | 2005-02-23 | 2009-01-13 | Texas Instruments Incorporated | Flip chip package with advanced electrical and thermal properties for high current designs |
US20070132073A1 (en) | 2005-12-09 | 2007-06-14 | Tiong Toong T | Device and method for assembling a top and bottom exposed packaged semiconductor |
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