CN101015056B - 集成晶体管模块及其制造方法 - Google Patents

集成晶体管模块及其制造方法 Download PDF

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CN101015056B
CN101015056B CN2005800211001A CN200580021100A CN101015056B CN 101015056 B CN101015056 B CN 101015056B CN 2005800211001 A CN2005800211001 A CN 2005800211001A CN 200580021100 A CN200580021100 A CN 200580021100A CN 101015056 B CN101015056 B CN 101015056B
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拉吉夫·D·乔希
乔纳森·A·诺奎尔
孔苏埃洛·N·汤普兹
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Abstract

一种集成晶体管模块包括一引线框，所述引线框界定至少一个低侧台及至少一个高侧台。所述引线框的一台阶部分机械地且电互连所述低侧及高侧台。一低侧晶体管安装于所述低侧台上，其漏极电连接至所述低侧台。一高侧晶体管安装于所述高侧台上，其源极电连接至所述高侧台。

Description

集成晶体管模块及其制造方法
对相关申请案的交叉参考
本申请案主张2004年6月24日申请的第10/876,248号美国专利申请案的权利。
技术领域
本发明大体上涉及半导体装置。更特定而言，本发明涉及一种集成晶体管模块，其适合于用作其它装置(包括同步降压转换器)的构建块。
背景技术
通常在蜂窝电话、便携式计算机、数码相机、路由器及其它便携式电子系统的电源中使用同步降压转换器，其变换DC电压电平以向可编程球栅阵列集成电路、微处理器、数字信号处理集成电路及其它电路提供电力，同时稳定电池输出、过滤噪声且减少波纹。同步降压转换器还用于在数据通信、电信、载荷点及计算应用的广泛范围内提供高电流多相电力。
图1展示典型同步降压转换器的简化示意图。同步降压转换器(SBC)10包括高侧金属氧化物半导体场效应晶体管(MOSFET)12及低侧MOSFET 14。低侧MOSFET 14的漏极D电连接至高侧MOSFET 12的源极S。大多数以商业为目的生产的MOSFET为垂直装置且被封装，使得连接至栅极、漏极及源极的外部连接点都在所述装置的同一地理平面上。
分别在SBC 10中的所述高侧及低侧MOSFET 12及14的源极S与漏极D之间的连接件必须具有非常低的电感，以使得SBC 10在中等至高操作/切换频率下使用。在MOSFET 12及14被配置为分立装置的情况下，必须使SBC 10的电路板布局的设计最优化以降低寄生电感。或者，SBC 10可配置为单个封装中的完全集成的同步降压转换器，且其经设计及部署以降低分别在高侧及低侧MOSFET 12与14的源极S与漏极D之间的连接件中的寄生电感。然而，所述完全集成的装置倾向于通常不与其它应用及/或设计兼容的相当特殊的应用及/或设计的装置。此外，连接所述MOSFET的印刷电路板迹线/导体通常不能很好地适合于承载中等至高电流电平。
因此，所属领域中需要一种非特殊应用的降压转换器，其在所述高侧MOSFET的源极与所述低侧MOSFET的漏极之间具有降低的电感或较低电感的连接件，且能够承载中等至高电流。
此外，所属领域中需要一种集成晶体管模块或构建块，其在所述模块的高侧晶体管的源极与所述模块的低侧晶体管的漏极之间提供连接，其能够承载中等至高电流且具有降低的或较低的电感，且因此适合于用作供在中等/高频率下使用的降压转换器的设计/构造的构建块。
此外，所属领域中需要一种形成集成晶体管模块或构建块的方法，所述集成晶体管模块或构建块在所述模块的高侧晶体管的源极与所述模块的低侧晶体管的漏极之间提供降低的或较低的电感的连接件，其能够承载中等至高电流，且因此使降压转换器的设计/构造能够在高频率下使用。
另外，所属领域中需要一种形成降压转换器的方法，所述降压转换器适合于通过使用集成晶体管模块或构建块在高频率下使用，所述集成晶体管模块或构建块在所述模块的高侧晶体管的源极与所述模块的低侧晶体管的漏极之间具有降低的或较低的电感的连接件，且能够承载中等至高电流。
发明内容
本发明提供一种集成晶体管模块，其在所述晶体管之间提供低电感、高电流容量连接，且适合作为其它电路(例如，降压转换器)的构建块。
本发明以其一个形式包含一集成晶体管模块，其包括一引线框，所述引线框界定至少一个低侧台(low-side land)及至少一个高侧台(high-side land)。所述引线框的台阶部分机械地且电互连所述低侧及高侧台。低侧晶体管安装于所述低侧台上，其漏极电连接至所述低侧台。高侧晶体管安装于所述高侧台上，其源极电连接至高侧台。
本发明的一个优点在于提供一种集成晶体管模块，其包括在一个晶体管的漏极与另一个晶体管的源极之间的低电感、高电流容量的连接件，且其因此适合作为降压转换器的构建块。
本发明的另一个优点在于所述集成晶体管模块容易且高效地被散热。
本发明的再一优点在于所述集成晶体管模块由使用组合式/标准封装的装置形成，且因此根据一高效的工艺流程而制造。
本发明的再一优点在于所述集成晶体管模块简化印刷电路板的布局及设计。
本发明的又一优点在于所述集成晶体管模块可用于可调整多相DC-DC转换器装置。
此外，本发明的优点还在于所述集成晶体管模块减少了DC/DC转换器装置中的组件数。
附图说明
结合附图参考以下对本发明一个实施例的描述，将明了且更好地理解本发明的上述及其它特征及优点以及实现其的方式，其中：
图1为示范性同步降压转换器的示意图；
图2说明图1的同步降压转换器的功能模块；
图3为本发明的集成FET模块的一个实施例的侧视图；
图4为本发明的集成FET模块的第二实施例的侧视图；
图5A-5C展示用于本发明的集成FET模块及其制造方法的第三实施例的引线框的一个实施例的顶视图；及
图6A-6G说明本发明的集成FET模块的一个实施例的制造方法的一个实施例。
在所述若干图式中，对应的参考符号指示对应的部分。本文所陈述的范例以一个形式说明本发明的一个优选实施例，且所述范例不解释为以任何方式限制本发明的范围。
具体实施方式
现在参看附图且尤其是参看图1，其展示示范性同步降压转换器的示意图。如上文所论述，同步降压转换器(SBC)10包括高侧金属氧化物半导体场效应晶体管(MOSFET)12及低侧MOSFET 14。低侧MOSFET 14的漏极D电连接至高侧MOSFET 12的源极S。进而，MOSFET 12和14的栅极G连接至脉宽调制(PWM)控制器20的对应输出(未参考)。如图2中最清楚地展示，本发明的集成FET模块集成环22内的电路，包括MOSFET 12及14。
现在参看图3及4，其展示在单个化之前(图4)及之后(图3)的本发明的集成晶体管模块的一个实施例的侧视图。集成晶体管模块30包括高侧及低侧晶体管12及14、衬底或引线框32、模制件(molding)34及散热片36。通常，高侧及低侧晶体管12及14(例如，场效应晶体管(FET)或金属氧化物半导体场效应晶体管(MOSFET))设置于衬底或引线框32上并与其耦合，所述衬底或引线框32提供低侧FET 14的漏极D与高侧FET 12的源极S之间的低电感电连接，且因此提供适合于用作其它电路(例如，降压转换器)的构建块的集成晶体管模块30。
高侧及低侧FET 12及14为常规集成电路MOSFET装置，且经选择以适合于集成FET模块30的既定应用。在所示的实施例中，高侧FET 12配置为倒装式装置/封装，且低侧FET 14配置为BGA装置/封装。
衬底或引线框32由导电材料(例如，铜或铝)构成，且厚度为(例如)从约.005至约0.010英寸。通常，衬底32及模制件34界定至少一个高侧台图案42及至少一个低侧台图案44。衬底32的上面界定有台图案42及44的部分通过衬底32的台阶部分46互连。台阶部分46将高侧台图案42及低侧台图案44定向于相应的平面中，所述平面相对于彼此大体上平行。与模制件34结合的台阶部分46以相对于彼此大体上共面的方式设置高侧及低侧FET 12及14。将衬底32半蚀刻以制备高侧台图案42上的图案，高侧MOSFET 12安装至高侧台图案42(包括焊垫48)并在其之上。
高侧FET 12以倒装法安装至相应高侧台图案42，且低侧FET 14使用用于安装BGA封装的常规工艺安装至相应的低侧台图案44。更特定而言，每一低侧FET 14的漏极D附接至相应的低侧台图案44，且每一高侧FET 12的源极S以倒装法附接至高侧台图案42。
模制件34形成于台图案44的侧面上并覆盖所述侧面，所述台图案44的所述侧面与其高侧FET 12的所附接的侧面相对。模制件34的第一或顶表面34A(图3及图6B)形成为与衬底32的第一或上表面32A大体上共面。模制件34电隔离高侧FET 12的漏极及栅极，使其不与散热片36接触，或与散热片36电短路(参见图3及4)。
散热片36以导热方式(例如，导热膏或焊膏)附接至衬底32的第一或上表面32A。散热片36延伸集成FET模块30的整个长度及/或宽度，因为模制件34防止高侧FET 12的漏极及栅极与散热片36短路。散热片36由导热材料(例如，铜条或其它合适的导热材料)构成。
图6A-6G说明本发明的集成FET模块的一个实施例的制造方法的一个实施例。预成型的引线框32以镜像侧或半部配置，如图6A所示，从每一侧或半部形成相应的集成FET模块30。模制部分34形成于衬底32的每一镜像半部上，如图6B所示。模制部分34覆盖台阶部分46及低侧台44的与其上面安装有低侧FET 14的侧面相对的侧面，并形成与衬底32的第一或上表面32A大体上共面的顶表面34A。接着，高侧FET 12以倒装法安装于高侧台图案42上，如图6C所示。焊球56形成于焊垫48上，焊垫48随后经回流以将衬底32且因此将集成FET模块30的高侧FET 12的源极S及低侧FET 14的漏极D电连接至电路板或其它装置，如图6D所示。
接着，低侧FET 14通过常规BGA封装附接而安装至衬底32的低侧台44，如图6E所示，且两个镜像半部(例如)通过冲压(如图6F所示)或通过锯割(如图6G所示)而单个化。
尤其应注意，集成FET模块30在图6D所示的制造阶段的单个化形成两个子组合件60。每一子组合件60包括一个或一个以上高侧FET 12，所述高侧FET 12安装至衬底32的相应高侧台42并由相应的模制件34隔离。衬底32(其一部分从模制件34延伸并界定台44)形成嵌入式连接器条，所述连接器条适合于将高侧FET 12的源极连接至另一封装或装置，例如低侧FET 14。尽管衬底32呈现为将高侧FET 12连接至低侧FET14，但衬底32可替代地配置成将实际上任何其它所要类型的集成电路装置及/或封装连接至高侧FET 12。
图5A-5C所示的衬底32的实施例对应于包括两个高侧FET 12及一个低侧FET 14的集成FET模块30的实施例。因此，在该实施例中，衬底32包括模制件34，所述模制件34围绕由衬底32界定的高侧台图案42的外围设置。相应高侧FET 12的源极S以倒装法安装至高侧台图案42，且低侧FET 14如上所述安装。因此，高侧FET 12的源极S以类似于如上所述的方式经由衬底32电连接至低侧FET 14的漏极D。相对于互连分立组件所需的布局，FET源极的此互连大大简化了印刷电路板的布局。
在使用中，集成FET模块30形成用于例如降压转换器的其它电路或需要两个MOSFET的其它电路的构建块，其中所述两个MOSFET中的一个MOSFET的漏极经由衬底/引线框32连接另一MOSFET的源极，所述衬底/引线框32能够承载较高电流并具有相对较低的电感。集成FET模块30的表面大体上共面，且因此提供用于供散热片36容易地附接及/或集成的装置，且所述装置的表面积大于原本可能的表面积，因为高侧FET 12通过模制件34而与散热片36电隔离，且因此使FET 12与散热片36短路的可能性最小化。
虽然本发明已描述为具有优选设计，但本发明可在本揭示内容的精神及范围内作进一步修改。因此，本申请案旨在涵盖使用本文所揭示的普遍原理的本发明的任何变化、使用或改动。此外，本申请案旨在涵盖那些不在本揭示内容内但在本发明所属的技术领域中已知或惯例的实践内且在所述权利要求书的限制内的改动。

Claims (21)

1.一种集成晶体管模块，其包含：
一导电材料引线框，其界定至少一个低侧台及至少一个高侧台，所述引线框的一台阶部分机械地且电互连所述低侧台及高侧台；
一低侧晶体管，其在所述集成晶体管模块内的球栅阵列封装中，且所述低侧晶体管具有源极端连接；
一高侧晶体管，其具有一漏极端连接；
所述低侧晶体管，其安装于所述低侧台上，所述低侧晶体管的一漏极附着至所述低侧台且电连接至所述低侧台；及
所述高侧晶体管，其安装于所述高侧台上，所述高侧晶体管的一源极电连接至所述高侧台；
其中，所述低侧晶体管与所述高侧晶体管被以相对于彼此大体上共面的方式布置。
2.如权利要求1所述的集成晶体管模块，其中所述低侧晶体管及所述高侧晶体管包括金属氧化物半导体场效应晶体管。
3.如权利要求1所述的集成晶体管模块，其中所述高侧晶体管以倒装法安装至所述高侧台。
4.如权利要求1所述的集成晶体管模块，其中所述低侧晶体管包含在一球栅阵列封装内，所述封装安装至所述低侧台。
5.如权利要求1所述的集成晶体管模块，其进一步包含一模制部分，所述模制部分覆盖所述引线框的与所述高侧台相对的一侧面，所述模制部分具有一上表面，所述上表面相对于所述引线框的与所述低侧台相对的一侧面大体上共面。
6.如权利要求5所述的集成晶体管模块，其进一步包括一散热片，所述散热片热耦合至所述引线框的上表面。
7.如权利要求6所述的集成晶体管模块，其中所述散热片在所述模制部分上延伸。
8.一种同步降压转换器，其包括：
一集成子组合件，其包括一导电材料引线框、至少一个在所述集成子组合件内的球栅阵列封装中的低侧晶体管，及至少一个高侧晶体管，所述引线框界定至少一个低侧台及至少一个高侧台，所述引线框的一台阶部分机械地且电互连所述低侧台及所述高侧台，所述低侧晶体管安装于所述低侧台上，所述低侧晶体管的一漏极附着至所述低侧台且电连接至所述低侧台，所述高侧晶体管安装于所述高侧台上，所述高侧晶体管的一源极电连接至所述高侧台。
9.如权利要求8所述的同步降压转换器，其中所述低侧晶体管及所述高侧晶体管包含金属氧化物半导体场效应晶体管。
10.如权利要求8所述的同步降压转换器，其中所述高侧晶体管以倒装法安装至所述高侧台。
11.如权利要求8所述的同步降压转换器，其中所述低侧晶体管包含于一球栅阵列封装内，所述封装安装至所述低侧台。
12.如权利要求8所述的同步降压转换器，其进一步包含一模制部分，所述模制部分覆盖所述引线框的与所述高侧台相对的一侧面，所述模制部分具有一上表面，所述上表面相对于所述引线框的与所述低侧台相对的一侧面大体上共面。
13.如权利要求12所述的同步降压转换器，其进一步包含一散热片，所述散热片热耦合至所述引线框的上表面。
14.如权利要求13所述的同步降压转换器，其中所述散热片在所述模制部分上延伸。
15.一种集成子组合件，其包含：
一导电材料引线框，其界定至少一个低侧台及至少一个高侧台，所述引线框的一台阶部分机械地且电互连所述低侧台及高侧台；
一低侧晶体管，其安装在所述低侧台上，且所述低侧晶体管在所述集成子组合件内的球栅阵列封装中，所述低侧晶体管的一漏极附着至所述低侧台且电连接至所述低侧台；
一高侧晶体管，其安装于所述高侧台上，所述高侧晶体管的一源极电连接至所述高侧台；及
一模制部分，其覆盖所述引线框的与所述高侧台相对的一侧面，所述模制部分具有一上表面，所述上表面相对于所述引线框的与所述低侧台相对的一侧面大体上共面。
16.如权利要求15所述的集成子组合件，其中所述高侧晶体管包含一金属氧化物半导体场效应晶体管。
17.如权利要求15所述的集成子组合件，其中所述高侧晶体管以倒装法安装至所述高侧台。
18.一种制造一集成晶体管模块的方法，其包含：
形成一导电材料引线框，所述引线框界定至少一个低侧台及至少一个高侧台，所述高侧台垂直地偏移离开所述低侧台；
以一电绝缘材料封闭所述引线框的靠近所述高侧台的一部分，所述引线框的与所述高侧台相对的一侧面上的所述绝缘材料的一上表面相对于所述引线框的与所述低侧台相对的一侧面大体上共面；
将在所述集成晶体管模块内的球栅阵列封装中的低侧晶体管安装于所述低侧台上，所述低侧晶体管的一漏极附着至所述低侧台且电连接至所述低侧台，所述引线框使所述高侧晶体管的所述源极和所述低侧晶体管的所述漏极之间互相电连接；及将一高侧晶体管安装于所述高侧台上，所述高侧晶体管的一源极电连接至所述高侧台。
19.如权利要求18所述的方法，其包含以下其它步骤：将一低侧晶体管安装于所述低侧台上，所述低侧晶体管的一漏极电连接至所述低侧台，所述引线框将所述高侧晶体管的所述源极与所述低侧晶体管的所述漏极电互连。
20.如权利要求19所述的方法，其中所述高侧晶体管以倒装法安装于所述高侧台上。
21.如权利要求19所述的方法，其中所述低侧晶体管包含于一球栅阵列封装内。
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