TWI405315B - 積體電晶體模組及其製造方法 - Google Patents

積體電晶體模組及其製造方法 Download PDF

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TWI405315B
TWI405315B TW094121315A TW94121315A TWI405315B TW I405315 B TWI405315 B TW I405315B TW 094121315 A TW094121315 A TW 094121315A TW 94121315 A TW94121315 A TW 94121315A TW I405315 B TWI405315 B TW I405315B
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Rajeev Dinkar Joshi
Jonathan A Noquil
Consuelo N Tangpuz
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Fairchild Semiconductor
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Description

積體電晶體模組及其製造方法
本發明大體而言係關於半導體元件。更具體言之，本發明係關於一積體電晶體模組，其適用作用於包括同步降壓式轉換器之其它元件的一建置組塊。
通常用於蜂巢式電話、攜帶型電腦、數位相機、路由器及其它攜帶型電子系統之電源中的同步降壓式轉換器變換直流(DC)電壓位準以便給可程式柵格陣列積體電路、微處理器、數位訊號處理積體電路及其它電路提供電力，同時穩定電池輸出，過濾噪聲並減少漣波。同步降壓式轉換器亦用於在資料通訊、電信、負載點及計算應用之廣泛範圍中提供高電流多相功率。
圖1展示一典型同步降壓式轉換器之一簡化示意圖。同步降壓式轉換器(SBC)10包括一高側金氧半場效電晶體(MOSFET)12及一低側MOSFET 14。低側MOSFET 14之汲極D電連接至高側MOSFET 12之源極S上。多數商業生產之MOSFET為垂直元件，且其經封裝以使得連接至閘極、汲極及源極之外部點處於與該元件相同的地理平面上。
SBC 10中之高側MOSFET 12及低側MOSFET 14之分別的源極S與該汲極D之間的連接必須具有一非常低的電感以使SBC 10在中等至高的操作頻率/切換頻率下使用。若MOSFET 12及14經組態為離散元件，則SBC 10之電路板佈局之設計必須經最優化以減少寄生電感。或者，SBC 10可在一單一封裝中組態為一全積體同步降壓式轉換器，且該同步降壓式轉換器經設計及佈局以減少高側MOSFET 12及低側MOSFET 14之分別的源極S與汲極D之間的連接中之寄生電感。然而，該等全積體元件傾向於為常常不會與其它應用及/或設計相兼容的相當特殊應用及/或特殊設計元件。另外，連接MOSFET之印刷電路板跡線/導體通常不會很好地適於載運中等位準至高位準之電流。
因此，此項技術中所需的為一非特殊應用降壓式轉換器，其在高側MOSFET之源極與低側MOSFET之汲極之間具有一經減少的電感連接或低電感連接且該降壓式轉換器可載運中等至高的電流。
此外，此項技術中所需的為一積體電晶體模組或建置組塊，其在模組之一高側電晶體之源極與模組之一低側電晶體之汲極之間提供一連接，該模組可載運中等至高的電流且具有一經減少的或低電感且因此適用作用於一降壓式轉換器之設計/構造的一建置組塊，其中該降壓式轉換器係用於在中等/高頻率之下使用。
此外，此項技術中所需的為一種形成一積體電晶體模組或建置組塊之方法，該積體電晶體模組或建置組塊在模組之一高側電晶體之源極與模組之一低側電晶體之汲極之間提供一經減少的或低的電感連接，該模組可載運中等的至高的電流，且藉此使得可對在高頻率下使用之一降壓式轉換器進行設計/構造。
另外，此項技術中所需的為一種藉由使用一積體電晶體模組或建置組塊來形成一適用於一高頻率的降壓式轉換器之方法，其中該積體電晶體模組或建置組塊在模組之一高側電晶體之源極與模組之一低側電晶體之汲極之間具有經減少的或低的電感連接，且其可載運中等的至高的電流。
本發明提供一種積體電晶體模組，其在電晶體之間提供一低電感高電流容量連接，且其可用作用於其它電路(諸如，降壓式轉換器)之一建置組塊。
本發明在其一形態中包含一積體電晶體模組，其包括一界定至少一低側連接盤及至少一高側連接盤的引線框。該引線框之一階梯狀部分機械性地及電互連該低側連接盤與該高側連接盤。一低側電晶體安裝於該低側連接盤上，其中其汲極電連接至該低側連接盤。一高側電晶體安裝於該高側連接盤上，其中其源極電連接至該高側連接盤。
本發明之一優勢為：一積體電晶體模組提供包含一電晶體之該汲極與另外電晶體之該源極間之低自感應高電流荷載之連接，且因此其可用作一降壓式轉換器之一建置組塊。
本發明之另一優勢為該積體電晶體模組可被容易地且有效地散熱。
本發明之又一優勢為該積體電晶體模組由使用模組化/標準封裝之元件形成，且因此其係根據一有效處理流程製造。
本發明之又一優勢為該積體電晶體模組簡化了印刷電路板之佈局及設計。
本發明之另一優勢為該積體電晶體模組可用於可升級多相DC－DC轉換器元件中。
此外，本發明之一優勢為該積體電晶體模組減少了DC/DC轉換器元件中之組件數目。
現參看圖式且特定參考圖1，其所示為一例示性同步降壓式轉換器之一示意圖。如上所討論，同步降壓式轉換器(SBC)10包括一高側金氧半場效電晶體(MOSFET)12及一低側MOSFET 14。低側MOSFET 14之汲極D 電連接至高側MOSFET 12之源極S 上。另外，MOSFET 12與14之閘極G連接至一脈寬調變(PWM)控制器20之相應輸出(未標記)上。如圖2中最佳所示，本發明之積體FET模組在包括MOSFET 12及14之圈22內整合電路。
現參看圖3及圖4，其展示了本發明之一積體電晶體模組之一實施例在切斷前的側視圖(圖4)及在切斷之後(圖3)的側視圖(圖3)。積體電晶體模組30包括高側電晶體及低側電晶體12及14、基板或引線框32、模製物34及散熱片36。通常，諸如場效電晶體(FET)或金氧半場效電晶體(MOSFET)之高側電晶體及低側電晶體12及14被安置於基板或引線框32上並被耦接至該基板或該引線框32上，該基板或該引線框32在低側FET 14之汲極D與高側FET 12之源極S之間提供一低電感電連接，且從而提供適用作其它電路(諸如一降壓式轉換器)之一建置組塊的一積體電晶體模組30。
高側FET及低側FET 12及14為習知積體電路MOSFET元件且其經選擇以便適用於積體FET模組30所意欲用於之應用。在所示實施例中，高側FET 12組態為一覆晶元件/封裝，且低側FET 14組態為一BGA元件/封裝。
基板或引線框32由一諸如銅或鋁的導電材料構成，且具有自大約.005吋至大約0.010吋的厚度。通常，基板32及模製物34界定至少一高側連接盤圖案42及至少一低側連接盤圖案44。基板32之部分(連接盤圖案42與44被界定於該等部分上)由基板32之一階梯狀部分46互連。階梯狀部分46在大體上相對於彼此平行之個別平面中定向高側連接盤圖案42及低側連接盤圖案44。階梯狀部分46連同模製物34一起以一大體上相對於彼此共平面的方式來安置高側FET及低側FET 12及14。基板32經半蝕刻以在包括焊墊48的高側連接盤圖案42上準備一圖案，其中高側MOSFET 12被安裝至且被安裝於該圖案42上。
高側FET 12覆晶式安裝至相應高側連接盤圖案42上且低側FET 14藉由使用習知的用於安裝BGA封裝之製程安裝至相應低側連接盤圖案44上。更特定言之，每一低側FET 14之汲極D附接於一相應低側連接盤圖案44上，且每一高側FET 12之源極S覆晶式附接於高側連接盤圖案42上。
模製物34形成於連接盤圖案44之與高側FET 12所附接之側相對的側上並覆蓋該側。模製物34之一第一表面或頂面34A(圖3及6B)經形成為與基板32之第一表面或上表面32A大體上共平面。模製物34將高側FET 12之汲極與閘極電絕緣以防與散熱片36相接觸或與其發生電短路(見圖3與4)。
散熱片36係以一導熱方式(例如，一導熱膏或焊錫膏)附接至基板32之第一表面或上表面32A上。由於模製物34防止高側FET 12之汲極及閘極與散熱片36發生短路，因此散熱片36延伸積體FET模組30之整個長度及/或寬度。散熱片36由諸如一銅條或其它適合導熱材料條的導熱材料構成。
圖6A－6G說明一用於製造本發明之一積體FET模組之一實施例的一種方法之實施例。如圖6A中所示，預成型引線框32組態有鏡像側或半邊，個別積體FET模組30自該等側或該等半邊之每一者形成。如圖6B中所示，模製物部分34形成於基板32之鏡像半邊之每一者上。模製物部分34覆蓋階梯狀部分46及低側連接盤44之一側(該側與於其上安裝了低側FET 14之低側連接盤44的另一側相對)，並形成與基板32之第一表面或上表面32A大體上共平面之頂面34A。如圖6C中所示，接著高側FET 12被覆晶式安裝於高側連接盤圖案42上。如圖6D中所示，焊球56形成於焊墊48上，該焊球稍後經回焊以將積體FET模組30之基板32，從而將高側FET 12之源極S與低側FET 14之汲極D電連接至一電路板或其它元件上。
如圖6E中所示，接著低側FET 14由習知BGA封裝附接安裝至基板32之低側連接盤44，且兩個鏡像半邊係(例如)藉由衝壓(如圖6F中所示)或鋸開(如圖6G中所示)而切斷。
應特別注意圖6D中所示的積體FET模組30在製造台處之切斷形成兩個子配件60。每一子配件60包括一或多個安裝至基板32之相應高側連接盤42上並由相應模製物34絕緣的高側FET 12。基板32形成一適用於將高側FET12之源極連接至諸如FET 14的其它封裝或元件上的嵌式連接器條，其中該基板32之一部分自模製物34延伸並界定連接盤44。雖然基板32表示為將高側FET 12連接至低側FET 14上，但是基板32可經另外組態以將幾乎所需任何其它類型之積體電路元件及/或封裝連接至高側FET 12上。
圖5A－5C中所示之基板32之實施例對應於包括兩個高側FET 12及一低側FET 14的積體FET模組30之一實施例。因此，在該實施例中，基板32包括安置於由基板32所界定之高側連接盤圖案42之周邊附近的模製物34。個別高側FET 12之源極S覆晶式安裝至高側連接盤圖案42上且低側FET 14經如上所述安裝。因而，高側FET 12之源極S以類似上述方式之方式經由基板32電連接至低側FET 14之汲極D。相對於用於互連離散組件所需之佈局而言，FET源極之互連顯著地簡化了印刷電路板之佈局。
使用中，積體FET模組30形成一建置組塊以用於其它電路，諸如，降壓式轉換器或其它電路，該其它電路需要兩個MOSFET，其中一MOSFET之汲極經由可載運相對較高電流並具有一相對較低電感之基板/引線框32而連接至另一MOSFET之源極。積體FET模組30之表面大體上共平面並藉此提供一元件(散熱片36會容易地附接及/或整合於其上)，且由於高側FET 12由模製物34而與散熱片36電絕緣，因此該積體FET模組30之表面具有一比另外可能的表面區域更大的表面區域，且從而最小化了FET 12與散熱片36發生短路之可能性。
雖然已描述了本發明具有一較佳設計，但是可在本揭示內容之精神及範疇內進一步對本發明進行修正。因此，本申請案意欲涵蓋使用本文中所揭示之一般原則的本發明之任何變化、使用或修改。另外，本申請案意欲涵蓋本揭示內容之偏離，該等偏離在本發明所相關的技術中之已知或慣用規範內且在附加之申請專利範圍之限制內。
10．．．同步降壓式轉換器/SBC
12．．．高側MOSFET/高側FET/高側金氧半場效電晶體
14．．．低側MOSFET/低側FET
20．．．脈寬調變控制器
22．．．圈
30．．．積體電晶體模組/積體FET模組
32．．．基板/引線框
32A．．．上表面
34．．．模製物
34A．．．頂面
36．．．散熱片
42．．．高側連接盤/高側連接盤圖案
44．．．低側連接盤/低側連接盤圖案
46．．．階梯狀部分
48．．．焊墊
56．．．焊球
60．．．子配件
圖1為一例示性同步降壓式轉換器之一示意圖；圖2說明圖1之同步降壓式轉換器之功能模組；圖3為本發明之一積體場效電晶體(FET)模組之一實施例之一側視圖；圖4為本發明之一積體FET模組之一第二實施例之一側視圖；及圖5A－5C展示用於本發明之一積體FET模組之一第三實施例的一引線框之一實施例之一俯視圖，及該實施例之製造方法；及圖6A－6G說明用於製造本發明之一積體FET模組之一實施例的一種方法的一實施例。
相應參考符號指示若干視圖中的相應部件。本文中所陳述之範例說明了一形態之本發明之一較佳實施例，且此等範例並非解釋為以任何方式限制本發明之範疇。
12．．．高側MOSFET/高側FET/高側金氧半場效電晶體
14．．．低側MOSFET/低側FET
30．．．積體電晶體模組/積體FET模組
32．．．基板/引線框
32A．．．上表面
34．．．模製物
34A．．．頂面
36．．．散熱片
42．．．高側連接盤/高側連接盤圖案
44．．．低側連接盤/低側連接盤圖案
46．．．階梯狀部分
48．．．焊墊
56．．．焊球

Claims (25)

  1. 一種半導體裝置，其包含：一連續金屬引線框，其界定至少一於一第一平面上之低側連接盤及至少一於一實質上平行於且有別於該第一平面之第二平面上之高側連接盤，該引線框之一階梯狀部分機械互連且電互連該低側連接盤與該高側連接盤；一低側電晶體，以球狀柵格陣列封裝安裝於該低側連接盤上，該電晶體之一汲極電連接至該低側連接盤；及一高側電晶體，以覆晶式安裝於該高側連接盤上，該高側電晶體之一源極電連接至該高側連接盤。
  2. 一種同步降壓式轉換器，其包含：一積體子配件，其包括一連續之導電金屬引線框、至少一低側電晶體及至少一高側電晶體，該引線框界定至少一於一第一平面上之低側連接盤及至少一於一實質上平行於且有別於該第一平面之第二平面上之高側連接盤，該引線框之一階梯狀部分機械互連且電互連該低側連接盤與該高側連接盤，該低側電晶體安裝於該低側連接盤上，該低側電晶體之一汲極電連接至該低側連接盤，該高側電晶體安裝於該高側連接盤上，且該高側電晶體之一源極電連接至該高側連接盤。
  3. 如請求項2之同步降壓式轉換器，其中該低側電晶體及該高側電晶體包含金氧半場效電晶體。
  4. 如請求項2之同步降壓式轉換器，其中該等電晶體之一者係覆晶式安裝而另一者係包含於一球狀柵格陣列封裝 內。
  5. 如請求項4之同步降壓式轉換器，其中該高側電晶體係覆晶式安裝至該高側連接盤上。
  6. 如請求項4之同步降壓式轉換器，其中該低側電晶體係包含於一球狀柵格陣列封裝內，該封裝安裝至該低側連接盤上。
  7. 如請求項2之同步降壓式轉換器，其進一步包含一模製物部分，該部分覆蓋該引線框之與該高側連接盤相對的一側，該模製物具有一相對於該引線框之與該低側連接盤相對的一側實質上共平面的上表面。
  8. 如請求項7之同步降壓式轉換器，其進一步包含一散熱片，其熱耦接至該引線框之與該高側連接盤相對之該側且藉此耦接至該低側電晶體及該高側電晶體。
  9. 如請求項8之同步降壓式轉換器，其中該散熱片遍佈該模製物部分。
  10. 一種積體電晶體模組，其包含：一連續之導電金屬引線框，該引線框界定至少一於一第一平面上之低側連接盤，以及至少一於一實質上平行於且有別於該第一平面之第二平面上之高側連接盤，該引線框之一階梯狀部分機械互連且電互連該低側連接盤與該高側連接盤；一低側功率電晶體安裝於該低側連接盤上，該低側電晶體之一汲極電連接至該低側連接盤；及一高側功率電晶體安裝於該高側連接盤，該高側電晶體之一源極電連接至該高側連接盤。
  11. 如請求項10之積體電晶體模組，其中該低側電晶體及該高側電晶體包含金氧半場效電晶體。
  12. 如請求項10之半導體裝置，其中該裝置係一同步降壓式轉換器。
  13. 如請求項10之積體電晶體模組，其中該等電晶體之一者係覆晶式安裝而另一者包含於一球狀柵格陣列封裝內。
  14. 如請求項13之積體電晶體模組，其中該高側電晶體係覆晶式安裝於該高側連接盤上。
  15. 如請求項13之積體電晶體模組，其中該低側電晶體包含於一球狀柵格陣列封裝內，該封裝安裝至該低側連接盤上。
  16. 如請求項10之積體電晶體模組，進一步包含一模製物部分，其覆蓋該引線框之與該高側連接盤相對的一側，該模製物具有一相對於該引線框之與該低側連接盤相對的一側實質上共平面的上表面。
  17. 如請求項16之積體電晶體模組，其進一步包含一散熱片，其熱耦接至該引線框之與該高側連接盤相對之該側且藉此耦接至該低側電晶體及該高側電晶體。
  18. 如請求項17之積體電晶體模組，其中該散熱片遍佈該模製物部分。
  19. 一種製造一積體電晶體模組之方法，其包含：形成一連續之金屬引線框，其界定至少一於第一平面上之低側連接盤及至少一於一實質上平行且有別於該第一平面之第二平面上之高側連接盤，其中該高側連接盤 垂直偏移自該低側連接盤，以及一階梯狀部分機械互連且電互連該低側連接盤與高側連接盤；將靠近該高側連接盤處之該引線框之一部分封入於一電絕緣材料中，在該引線框之與該高側連接盤相對的一側上的該絕緣材料的一上表面係相對於該引線框之與該低側連接盤相對的一側實質上共平面；及將一高側電晶體安裝於該高側連接盤上，該高側電晶體之一源極電連接至該高側連接盤。
  20. 如請求項19之方法，其包含另一步驟：將一低側電晶體安裝於該低側連接盤上，該低側電晶體之一汲極電連接至該低側連接盤，該引線框將該高側電晶體之該源極與該低側電晶體之該汲極電互連。
  21. 如請求項20之方法，其中該高側電晶體係覆晶式安裝於該高側連接盤上。
  22. 如請求項20之方法，其中該低側電晶體係包含於一球狀柵格陣列封裝內。
  23. 如請求項20之方法，其中該低側電晶體及該高側電晶體包含金氧半場效電晶體。
  24. 如請求項19之方法，進一步包含另一步驟：熱耦合一散熱片至該引線框相對於該高側連接盤之該側，且藉此耦接至該低側電晶體及該高側電晶體。
  25. 如請求項24之方法，其中該散熱片遍佈該模製物部分。
TW094121315A 2004-06-24 2005-06-24 積體電晶體模組及其製造方法 TWI405315B (zh)

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DE112005001457T5 (de) 2007-05-16
CN101015056B (zh) 2010-06-09
KR20070020304A (ko) 2007-02-20
JP2008504686A (ja) 2008-02-14
JP4999684B2 (ja) 2012-08-15
CN101015056A (zh) 2007-08-08
WO2006012110A3 (en) 2006-09-08
KR101167742B1 (ko) 2012-07-23
US20090117690A1 (en) 2009-05-07
US7842555B2 (en) 2010-11-30
US20050285238A1 (en) 2005-12-29
TW200614482A (en) 2006-05-01
US7501702B2 (en) 2009-03-10
WO2006012110A2 (en) 2006-02-02

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