CN1166057A - 底部引线半导体芯片堆式封装 - Google Patents

底部引线半导体芯片堆式封装 Download PDF

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CN1166057A
CN1166057A CN97104301A CN97104301A CN1166057A CN 1166057 A CN1166057 A CN 1166057A CN 97104301 A CN97104301 A CN 97104301A CN 97104301 A CN97104301 A CN 97104301A CN 1166057 A CN1166057 A CN 1166057A
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金容灿
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SK Hynix Inc
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Abstract

底部引线半导体芯片堆式封装包括：相对叠放的第一和第二管座，其中每个管座包括引线框、密封镀敷在每个凸点上的焊料、其下表面上的芯片焊盘与相应的一个焊料对准的半导体芯片，引线框具有凸点从其表面向上延伸的第一引线和从第一引线向上延伸的第二引线，芯片下表面上的芯片焊盘附着在相应的每个焊料上；粘结第一和第二管座的第一引线上表面的粘结剂；填充第一和第二管座的内部、密封芯片并封装引线框外部的模制化合物，该封装的第一引线的下部和第二引线的端部暴露于外。

Description

底部引线半导体芯片堆式封装
本发明涉及一种半导体封装，特别涉及一种底部引线半导体芯片堆式封装，该封装把一对分立的芯片结合到一个封装中，而且无需引线键合工艺，便于制造。
作为各种半导体封装中普通一种的SOJ(J形引线小外形)半导体芯片封装中，半导体芯片借助绝缘带或焊膏安装在引线框的垫片上。用金属连线电连接芯片的多个焊盘与引线框的相应内引线，然后进行树脂模制工艺。最后，分别将从封装管壳延伸出的外引线成形为“J”形，从而完成芯片封装。
对于这样构成的常规SOJ半导体芯片封装必须经过对应于其工业应用的电特性测试，为使其按要求工作，要将封装安装在装配基板上或内，例如装于存储器组件中。
然而，上述常规芯片封装存在由于外引线从封装管壳每侧延伸出造成的封装占基板的面积增大使弄弯外引线工艺的成品率下降的问题。
已于1995年6月27日转让给本受让人的美国专利5428248旨在解决上述问题，该专利中的芯片封装称作BLP(底部引线半导体封装)，现已投入批量生产。
参见图1，常规底部引线半导体封装包括：具有用于与基板(未示出)相连的多根基板连接引线2a和从每根相应的基板引线2a向上延伸的芯片连接引线2b的引线框2；借助于粘结剂安装在每根基板连接引线2a上的半导体芯片1；及电连接每个芯片焊盘10a与引线框2的相应一根芯片连接引线2b的多根金属连线4。用模制树脂5模制包括连线4、芯片1、引线框2和引线2a、2b的区域，从而形成封装管壳，每根基板连接引线2a的下表面从管壳的下部露出。
这样构成的常规底部引线半导体封装占基板的面积减小，可以防止外引线受损。
然而，芯片焊盘1a借助于金属连线4与相应的一根芯片连接引线2b电连接，所以由于金属连线造成的管壳高度的增加限制了芯片封装的减薄。
另外，因为芯片封装中只安装一块芯片，所以很难制造多层封装，因而限制了大规模集成。
再者，很难测试引线连接情况。
因此，本发明的目的是提供一种底部半导体芯片堆式封装，能减薄芯片封装，提高封装集成度。
本发明的另一目的是提供一种底部引线半导体芯片堆式封装，即便在封装安装于基板上后，也容易进行引线连接测试。
为了实现上述目的，本发明提供一种底部半导体芯片堆式封装，该封装包括：彼此相对堆叠的第一和第二管座，其中每个管座皆包括引线框、为密封凸点而涂的焊料、其下表面与焊料对准的半导体芯片，引线框具有凸点从其表面向上延伸的第一引线和从第一引线向上延伸的第二引线，芯片下表面上的芯片焊盘附着在焊料上；粘结第一和第二管座的第一引线的上表面的粘结剂；填充第一和第二管座的内部、密封芯片并封装引线框外部的模制化合物，这种封装的第一引线的下部和第二引线的端部暴露于外。
图1是常规底部引线半导体封装的剖面图；
图2A-2D是展示根据本发明第一实施例的底部引线半导体封装的制造步骤的剖面图；
图3是展示根据本发明第二实施例的底部引线半导体封装的剖面图。
下面将参照各附图说明本发明的底部引线半导体封装。
首先，如图2A所示，一种引线框10具有每根皆与基板(未示出)连接的多根第一引线10a和从每根第一引线10a向上延伸的多根第二引线10b。从每根第一引线10a的上表面延伸的是大小和位置与以后将安装于其上的芯片13的芯片焊盘13a相对应的凸点11。焊膏12涂在每个凸点11上，凸点11的上表面上的焊焊12对应于设置于芯片13下表面上的芯片焊盘13a，除芯片焊盘13a外，芯片13下表面上形成有聚酰胺层14。即，使其上包封式地涂敷了焊料12的凸点11与形成于聚酰胺层14上的相应的一个孔对准，以便插入该孔。此后，通过加热熔化焊料，并使之硬化，将芯片13底表面上的芯片焊盘13a贴到相应的一个焊料12上，从而可以把来自每个芯片焊盘13a的电信号传输到相应的一根第一引线10a，或把要输入芯片焊盘13a的电信号从相应的一根第一引线10a输入。这里，在以下的说明中把示于图2a的整个管座称作第一管座20。
与基板(未示出)相连的第一管座20包括：具有第一引线10a和从第一引线10a向上延伸的第二引线10b的引线框10，凸点11从第一引线10a的上表面向上突出；包封式地涂敷于凸点11上的焊料12；其下表面与焊料12对准的半导体芯片13，芯片13下表面上的焊盘13a附着在焊料12上。
如图2B所示，图2a的第一管座20和与其有相同结构的第二管座20’相对堆叠，第一和第二管座20、20’垂直对称。管座20、20’的上表面借助粘结剂30彼此粘接，粘结剂由如用于焊料12的导电粘结剂和如聚亚酰胺之类的绝缘粘结剂构成。用导电粘结剂电连接第一管座20的第二引线10b与相应的第二管座20’的第二引线10b’，而用绝缘粘结剂绝缘各第二引线10b、10b’。
即，用绝缘粘结剂可以使芯片13、13’分别发挥其各自的功能，用导电粘结剂可使芯片13，13’实现相同的功能。
如图2C所示，用模制化合物40填充第一和第二管座20、20’内部，密封芯片13、13’，并封装引线框10、10’的外部，但外露每根第一引线10a、10a’的下部和第二引线10b、10b’的端部。这里，模制化合物40可以由环氧树脂构成。
参见图2D，在第一引线10a、10a’和第二引线10b、10b’的外露部分每个表面上镀敷焊料膜50，并进行修整工艺，把外露的第二引线10b、10b’切到一定长度，从而完成本发明的底部引线半导体芯片堆式封装。
第二引线10b、10b’的端部伸出模制化合物40外，所以，在把其第一引线10a、10a’与芯片13、13’电连接的芯片封装安装到基板上后，仍可以适当地测试之。
图3示出了本发明的第二实施例，该实施例是一对垂直堆叠的底部引线半导体芯片堆式封装100、101。然而本发明的第二实施例并不限于这种两层结构，还可以把封装堆叠成至少有两层的多层堆叠封装。即，封装100的第一引线10a’与有相同结构的另一封装101粘接在一起。然后熔化并硬化镀敷在每个第一引线10a、10a’的外露表面上的每个焊料50，以用于粘接。在焊料50末熔化时，用作为替代粘结剂的焊膏可以加强引线10a、10a’的粘接力。另外，粘结剂材料不限于焊料，可以用能增强粘接力的任何导电粘结剂。
如上所述，本发明的底部引线半导体芯片堆式封装能减薄芯片封装，并能高度集成芯片封装。
另外，本发明的芯片堆式封装便于在将芯片封装安装于基板上后进行引线连接测试。

Claims (8)

1.一种底部引线半导体芯片堆式封装，包括：
彼此相对堆叠的第一和第二管座，其中每个管座包括引线框、密封凸点的焊料、其下表面上的芯片焊盘与相应的一个焊料对准的半导体芯片，引线框具有凸点从其表面向上延伸的第一引线和从第一引线向上延伸的第二引线，芯片下表面上的芯片焊盘附着在相应的焊料上；
粘结第一和第二管座的第一引线的上表面的粘结剂；
填充第一和第二管座的内部、密封芯片并封装引线框外部的模制化合物，该封装的第一引线的下部和第二引线的端部暴露于外。
2.根据权利要求1的封装，其特征在于，粘结剂由导电材料构成。
3.根据权利要求2的封装，其特征在于，导电材料由焊料构成。
4.根据权利要求1的封装，其特征在于，粘结剂由绝缘材料构成。
5.根据权利要求4的封装，其特征在于，绝缘材料由聚酰胺构成。
6.根据权利要求1的封装，其特征在于，用导电膜镀敷第一和第二引线的外露部分的每个表面。
7.根据权利要求1的封装，其特征在于，在每个半导体芯片的下表面上选择地形成聚酰胺层，但该层暴露芯片下表面上的芯片焊盘。
8.根据权利要求1的封装，其特征在于，模制化合物由环氧树脂构成。
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