KR960005042B1 - 반도체 펙케지 - Google Patents

반도체 펙케지 Download PDF

Info

Publication number
KR960005042B1
KR960005042B1 KR1019920020847A KR920020847A KR960005042B1 KR 960005042 B1 KR960005042 B1 KR 960005042B1 KR 1019920020847 A KR1019920020847 A KR 1019920020847A KR 920020847 A KR920020847 A KR 920020847A KR 960005042 B1 KR960005042 B1 KR 960005042B1
Authority
KR
South Korea
Prior art keywords
lead
semiconductor
semiconductor chip
chip
bar
Prior art date
Application number
KR1019920020847A
Other languages
English (en)
Other versions
KR940012549A (ko
Inventor
송치중
Original Assignee
금성일렉트론주식회사
문정환
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론주식회사, 문정환 filed Critical 금성일렉트론주식회사
Priority to KR1019920020847A priority Critical patent/KR960005042B1/ko
Priority to DE19934337675 priority patent/DE4337675B4/de
Priority to JP27660493A priority patent/JP3388609B2/ja
Publication of KR940012549A publication Critical patent/KR940012549A/ko
Priority to US08/409,911 priority patent/US5471088A/en
Application granted granted Critical
Publication of KR960005042B1 publication Critical patent/KR960005042B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

내용 없음.

Description

반도체 펙케지
제 1 도는 종래 반도체 펙케지의 구조도.
제 2 도는 종래 반도체 펙케지의 인쇄회로 기판에 실장한 예시도.
제 3 도는 본 발명에 따른 반도체 펙케지의 구조를 설명하기 위한 단면도.
제 4 도는 본 발명에 따른 반도체 펙케지의 리드가 접착 테이프에 부착된 상태를 보인 예시도.
제 5 도는 본 발명에 따른 반도체 펙케지를 인쇄회로 기판에 적층 실장한 예시도.
* 도면의 주요부분에 대한 부호의 설명
1 : 반도체 칩 2 : 패들
3 : 인너리드 4 : 아웃리드
5 : 금속와이어 6 : 몰딩 컴파운드
7 : 솔더 8 : 인쇄 회로 기판
9, 9' : 리드바 9a, 9a' : 제1단턱
9b, 9b' : 제2단턱 10 : 폴리 이미드계 접착 테이프
본 발명은 반도체 펙케지에 관한 것으로 특히, 반도체 조립 공정을 간소화하고, 반도체 제품을 소형 경박화할 수 있으며, 메모리 펙케지에 적용시 메모리 확장을 손쉽게 할 수 있도록 한 반도체 펙케지에 관한 것이다.
일반적으로 사용되는 반도체의 펙케지 구조는 제1도에 도시된 바와같이 반도체 칩(1)의 내부단자와 연결시켜 주기 위해 인너리드(3) 및 아웃리드(4)로 이루어지는 리드프레임(11)과, 상기 반도체 칩(1)과 리드프레임(11)을 전기적으로 연결시키는 금속와이어(5)와, 상기 반도체 칩(1)이 외부에 물리적인 충격이나 환경에 견디도록 보호막을 형성시켜 주는 몰딩 컴파운드(6)로 구성되어 있다.
상기와 같은 종래의 반도체 펙케지를 제조함에 있어서는 먼지 소잉(SAWING) 공정에 의해 개개로 분리된 반도체 칩(1)을 리드프레임(11)의 패들(2)에 접착제를 이용하여 부착고정하는 다이본딩(DIEBONDING) 공정을 수행하고, 상기 칩(1)의 본드패드와 리드프레임(11)에 인너리드(3)를 금속와이어(5)로 접속하여 전기적으로 연결하는 와이어 본딩(WIRE BONDING) 공정을 수행한 후, 와이어 본딩된 상기 칩(1)과 리드프레임의 인너리드(3)를 포함하는 일정부위를 몰딩컴파운드(6)로 밀폐시키는 몰딩공정을 수행하여 펙케지로 형성한 다음 마지막으로 트림(TRIM) 포밍(FORMING) 공정 및 플레이팅(PLATING) 공정을 진행하게 된다.
즉, 상기 트림 포밍공정은 패들(2)를 지지하고 있는 서포트바(도시되지 않음) 및 각 리드를 연결지지하고 있는 댐바(DAM BAR)(도시되지 않음)를 절단하여 아웃리드(4)를 소정의 형태로 절곡형성하는 공정으로서 이와같은 트림공정 및 포밍공정은 각각 별도로 진행되며 상기 포밍공정에 의한 아웃리드(4)의 절곡형태에 따라 제1도와 같은 표면실장형 반도체 펙케지인 스몰 아웃라인 J-리드 펙케지 및 듀얼 인라인 펙케지등으로 제조되며 이러한 메모리를 실장하려면 제2도에 도시된 바와같이 인쇄회로 기판(8)에 솔더(7)를 사용하여 반도체 펙케지와 연결하여 사용하였다.
이러한 종래의 반도체 펙케지는, 반도체 펙케지의 제조공정이 복잡하여 제조원가가 높고, 제조설비의 설치장소 및 펙케지 제조소요기간 뿐만 아니라 펙케지 내부에 금속성의 패들(2)이 존재하게 되므로 리플로우 솔더(REFLOW SOLDER)시 칩(1)과 패들(2) 및 몰딩컴파운드(6) 간의 열팽창계수차이로 인하여 펙케지 깨짐 불량이 발생되기 싶고, 또한 금속와이어(5)의 길이가 길어 칩의 전기적인 특성이 저하된다.
또한 반도체 펙케지를 인쇄회로 기판에 실장시, 펙케지의 몰딩부위 밖으로 리드프레임의 리드가 많이 돌출되어 실장면적이 많이 필요하고 한 제품이상을 쌓아올려 실장할 수가 없는 문제점이 야기되었다.
본 발명은 상기와 같은 문제점을 해결하기 위하여 반도체 펙케지를 접착 리드바를 사용하여 제작함으로써 실장시 펙케지 외부로 돌출되는 아웃리드가 없으므로 실장면적을 줄 일 수 있고 다이패들(Diepaddle)이 없어 펙케지 깨짐 불량이 적게 발생하며, 인쇄회로 기판에서 칩(Chip) 점유율이 작고 접착리드와 본드패드와의 거리가 짧아지므로 전기적 특성의 향상을 가져오며, 트림(TRIM), 포밍(FORMING)이 없으므로 강제적인 포밍으로 인한 발생될 수 있는 마이크로 갭 (MICRO GAP)이 제거되므로 내습성이 향상되도록 한 것으로서, 이하 첨부된 도면에 의해 상세히 설명하면 다음과 같다.
제 3 도는 본 발명에 따른 반도체 펙케지의 몰딩 후 모습을 나타낸 단면도로서, 리드바(9)(9')가 소정 간격을 두고 대향되게 배치되고, 상기 리드바(9)(9')에는 2개의 제1 및 제2단턱(9a)(9a')(9b)(9b')이 형성되어 있다. 그리고 상기 리드바(9)(9')의 제1단턱(9a)(9a')에는 반도체 칩(1)이 접착제 또는 접착테이프에 의해 부착되어 있고, 제2 단턱(9b)(9b')과 반도체 칩(1)은 금속와이어(5)에 의해 연결되어 있으며, 리드바(9)(9a')의 측면과 리드바 사이사이에는 몰딩 컴파운드(6)로 몰딩되어 있고, 하면에 폴리 이미드계 접착테이프(10)가 부착되어 있다. 폴리 이미드계 접착 테이프(10)는 펙케지 공정진행중 리드들의 위치를 고정시키는 역할을 하는 것으로, 최종적인 펙케지에는 폴리 이미드계 접착테이프(10)가 제거되어 완성된다.
제 4 도는 반도체 다이(칩)와 연결한 본 발명의 리드바가 접착 테이프에 부착된 예시도이며, 제 5 도는 본 발명을 사용하여 인쇄회로 기판에 적층 실장한 반도체 칩의 확장 예시도이다.
상기와 같이 이루어진 본 발명은 폴리 이미드계 접착테이프(10)위에 다수의 리드바(9)(9')를 제 3 도 및 제 4 도에서와 같이 부착한 다음 반도체 칩(1)을 비전도성 접착제 또는 접착테이프를 이용하여 리드바(9)(9')의 제1단턱(9a)(9a')에 접착시킨 후 금속와이어(5)를 사용하여 본드패드(Bond pad)와 리드바(9)(9')의 제2단턱(9b)(9b')에 와이어 본딩(Wire Bonding)을 하여 반도체 칩(1)과 리드바(9)(9')를 전기적으로 연결한다. 이러한 상태에서 에폭시 몰딩컴파운드(6)을 사용하여 몰딩을 한 다음 리드바(9)(9')의 밑면에 부착된 폴리 이미드계 접착테이프(10)를 제거하여 리드바의 밑면이 노출시되게 한다.
한편 본 발명의 반도체 펙케지를 메모리 칩을 적재한 경우에, 제5도에서와 같이 반도체 칩(1)의 용량을 확장시키려면 펙케지를 상하로 적층하고 리드바(9)(9a')의 하부면에 도전성 솔더(7)를 부착하여 솔더링(soldering)한다. 이때, 제5도에서 도시된 바와같이 리드바(9)(9')의 밑면이 윗면보다 넓기 때문에 반도체 제품의 용량을 확장할 경우 솔더(7)부착은 더 여유가 많게되므로 콘택(contact)불량은 거의 없게되는 것이다.
이상에서 상술한 바와같이 본 발명은 접착리드바를 사용하여 펙케지를 제작함으로써 기판에 실장시 펙케지 외부로 돌출되는 아웃리드가 없으므로 실장면적을 줄일 수 있고, 다이패들(Die paddle)이 없음으로 인해 펙케지 깨짐 불량이 적게 발생하고, 칩 점유율이 작으며 접착리드와 본드패드와의 거리가 짧아지므로 전기적 특성의 향상을 가져오고, 제조공정시 트림(TRIM), 포밍(FORMING)이 없게되어 강제적인 포밍(FORMING)으로 인한 마이크로 갭(MICRO GAP)이 제거됨으로써 내습성이 향상되는 것이다. 또한 리드가 펙케지의 상하로 노출되어 펙케지를 상하로 솔더에 의해 적층하여 메모리 확장이 용이하고 인쇄회로 기판 사용시 리드가 돌출되지 않아 고밀도 실장이 가능하며, 인쇄회로 기판, 메모리 카드 등에 양면으로 반도체 칩을 부착할 때도 리드가 펙케지 상하로 노출되어 펙케지의 포워드(FORWARD), 리버스(FEVERSE)의 개념이 필요없게 되어 몰드이후의 공정이 필요치 않음에 따라, 조립에 필요한 인원, 장비설치장소 등의 절감효과를 기대할 수 있는 것이다.

Claims (4)

  1. 다수의 본드 패드가 형성되어 있는 반도체 칩의 측면에, 제1단턱과 제1단턱보다 높은 제2단턱이 형성되어 있는 다수의 리드바가 소정의 간격으로 배열되고, 제1단턱 위에 상기 반도체 칩이 절연되게 위치하고, 다수의 본대 패드와 대응하는 위치에 있는 리드바가 금속와이어로 연결되고, 리드바의 상면과 하면만 노출되게 하고 리드바의 측면과 반도체 칩 및 금속와이어를 몰딩 컴파운드로 둘러싸도록 구성된 반도체 펙케지.
  2. 제 1 항에 있어서, 상기 다수의 리드바 밑면에 솔더를 부착하여 적층시 다수개의 반도체 펙케지가 확장되도록 한 것을 특징으로 하는 반도체 펙케지.
  3. 반도체 칩의 펙케지 방법에 있어서, (1) 접착테이프위에 제1단턱과 제2단턱이 형성된 다수의 리드바를 단턱이 서로 마주보게 배열하여 부착하는 단계, (2) 반도체 칩을 절연성 접착제로 제1단턱을 위에 위치시키는 단계, (3) 반도체 칩의 본드패드와 제2단턱은 도선으로 연결시키는 단계, (4) 리드바와 상하면만 남기고 리드바와 반도체 칩 및 도선을 컴파운드로 몰딩하는 단계로 이루어진 반도체 칩 펙케지방법.
  4. 제 3 항에 있어서, 상기 (4)단계후에 접착테이프를 제거하는 단계를 추가로 구비하는 반도체 칩 펙케지 방법.
KR1019920020847A 1992-11-07 1992-11-07 반도체 펙케지 KR960005042B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019920020847A KR960005042B1 (ko) 1992-11-07 1992-11-07 반도체 펙케지
DE19934337675 DE4337675B4 (de) 1992-11-07 1993-11-04 Verfahren zur Herstellung von stapelbaren Halbleitergehäusen
JP27660493A JP3388609B2 (ja) 1992-11-07 1993-11-05 半導体パッケージおよびその製造方法
US08/409,911 US5471088A (en) 1992-11-07 1995-03-23 Semiconductor package and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920020847A KR960005042B1 (ko) 1992-11-07 1992-11-07 반도체 펙케지

Publications (2)

Publication Number Publication Date
KR940012549A KR940012549A (ko) 1994-06-23
KR960005042B1 true KR960005042B1 (ko) 1996-04-18

Family

ID=19342670

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920020847A KR960005042B1 (ko) 1992-11-07 1992-11-07 반도체 펙케지

Country Status (4)

Country Link
US (1) US5471088A (ko)
JP (1) JP3388609B2 (ko)
KR (1) KR960005042B1 (ko)
DE (1) DE4337675B4 (ko)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3475306B2 (ja) * 1994-10-26 2003-12-08 大日本印刷株式会社 樹脂封止型半導体装置の製造方法
KR100214463B1 (ko) * 1995-12-06 1999-08-02 구본준 클립형 리드프레임과 이를 사용한 패키지의 제조방법
KR0179803B1 (ko) * 1995-12-29 1999-03-20 문정환 리드노출형 반도체 패키지
KR100186309B1 (ko) * 1996-05-17 1999-03-20 문정환 적층형 버텀 리드 패키지
US5817530A (en) * 1996-05-20 1998-10-06 Micron Technology, Inc. Use of conductive lines on the back side of wafers and dice for semiconductor interconnects
US5847458A (en) * 1996-05-21 1998-12-08 Shinko Electric Industries Co., Ltd. Semiconductor package and device having heads coupled with insulating material
KR0179925B1 (ko) * 1996-06-14 1999-03-20 문정환 리드프레임 및 그를 이용한 버텀 리드 반도체 패키지
KR100206910B1 (ko) * 1996-06-14 1999-07-01 구본준 반도체 패키지의 디플래쉬 방법
KR0179924B1 (ko) * 1996-06-14 1999-03-20 문정환 버텀리드 반도체 패키지
KR100232221B1 (ko) * 1996-12-31 1999-12-01 김영환 반도체 패키지 및 그 제조 방법
US5940687A (en) * 1997-06-06 1999-08-17 International Business Machines Corporation Wire mesh insert for thermal adhesives
KR100431315B1 (ko) * 1997-06-26 2004-10-06 주식회사 하이닉스반도체 반도체패키지및그제조방법
US6157074A (en) * 1997-07-16 2000-12-05 Hyundai Electronics Industries Co., Ltd. Lead frame adapted for variable sized devices, semiconductor package with such lead frame and method for using same
KR100271657B1 (ko) * 1998-05-30 2000-11-15 김영환 칼럼 리드형 반도체 패키지 및 그 제조방법
US6831352B1 (en) * 1998-10-22 2004-12-14 Azimuth Industrial Company, Inc. Semiconductor package for high frequency performance
JP3297387B2 (ja) 1998-11-20 2002-07-02 沖電気工業株式会社 半導体装置の製造方法
US6265761B1 (en) * 1999-05-07 2001-07-24 Maxim Integrated Products, Inc. Semiconductor devices with improved lead frame structures
KR100344927B1 (ko) * 1999-09-27 2002-07-19 삼성전자 주식회사 적층 패키지 및 그의 제조 방법
KR100426494B1 (ko) * 1999-12-20 2004-04-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이것의 제조방법
JP4637380B2 (ja) 2001-02-08 2011-02-23 ルネサスエレクトロニクス株式会社 半導体装置
JP4598316B2 (ja) * 2001-07-06 2010-12-15 パナソニック株式会社 樹脂封止型半導体装置およびその製造方法
JP3801121B2 (ja) * 2002-08-30 2006-07-26 松下電器産業株式会社 樹脂封止型半導体装置およびその製造方法
JP3736516B2 (ja) * 2002-11-01 2006-01-18 松下電器産業株式会社 リードフレームおよびその製造方法ならびに樹脂封止型半導体装置およびその製造方法
FR2851374B1 (fr) * 2003-02-18 2005-12-16 St Microelectronics Sa Boitier-semi-conducteur a puce de circuits integres portee par les pattes de connexion electrique
US20060201709A1 (en) * 2003-04-07 2006-09-14 Mciver Chandler H Low profile small outline leadless semiconductor device package
JP3910598B2 (ja) * 2004-03-04 2007-04-25 松下電器産業株式会社 樹脂封止型半導体装置およびその製造方法
US7161232B1 (en) * 2004-09-14 2007-01-09 National Semiconductor Corporation Apparatus and method for miniature semiconductor packages
FR2917236B1 (fr) * 2007-06-07 2009-10-23 Commissariat Energie Atomique Procede de realisation de via dans un substrat reconstitue.
JP2009094118A (ja) * 2007-10-04 2009-04-30 Panasonic Corp リードフレーム、それを備える電子部品及びその製造方法
JP5167963B2 (ja) * 2007-11-02 2013-03-21 大日本印刷株式会社 樹脂封止型半導体装置とそれに用いられるエッチング加工部材、および積層型樹脂封止型半導体装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4649415A (en) * 1985-01-15 1987-03-10 National Semiconductor Corporation Semiconductor package with tape mounted die
US5060844A (en) * 1990-07-18 1991-10-29 International Business Machines Corporation Interconnection structure and test method
US5233221A (en) * 1990-10-24 1993-08-03 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology
US5227232A (en) * 1991-01-23 1993-07-13 Lim Thiam B Conductive tape for semiconductor package, a lead frame without power buses for lead on chip package, and a semiconductor device with conductive tape power distribution
US5166772A (en) * 1991-02-22 1992-11-24 Motorola, Inc. Transfer molded semiconductor device package with integral shield
KR940006164B1 (ko) * 1991-05-11 1994-07-08 금성일렉트론 주식회사 반도체 패키지 및 그 제조방법

Also Published As

Publication number Publication date
KR940012549A (ko) 1994-06-23
DE4337675A1 (de) 1994-05-11
JPH06209069A (ja) 1994-07-26
US5471088A (en) 1995-11-28
JP3388609B2 (ja) 2003-03-24
DE4337675B4 (de) 2008-04-30

Similar Documents

Publication Publication Date Title
KR960005042B1 (ko) 반도체 펙케지
US6482674B1 (en) Semiconductor package having metal foil die mounting plate
US5428248A (en) Resin molded semiconductor package
USRE35109E (en) Semiconductor device and method for fabricating the same
JP3038553B2 (ja) 半導体パッケ―ジ用基板及び半導体パッケ―ジ並びにそれらの製造方法
JP2509595B2 (ja) 電子構成要素のパツケ−ジおよびその製造方法
EP1911092B1 (en) Integrated circuit packaging
US4448306A (en) Integrated circuit chip carrier
JP4860939B2 (ja) 半導体装置
KR970067781A (ko) 반도체 장치와 그의 제조방법 및 집합형 반도체 장치
US20090267214A1 (en) Electronic circuit device and method for manufacturing same
EP0474224B1 (en) Semiconductor device comprising a plurality of semiconductor chips
KR970002136B1 (ko) 반도체 패키지
KR940008290Y1 (ko) 반도체 패키지
JPH10189792A (ja) 半導体パッケージ
JP3211116B2 (ja) 電子部品及びそのモジュール構造
KR940006084B1 (ko) 브이에스엠피(vsmp : vertical small mounting package) 구조 및 그 제작방법
KR950003904B1 (ko) 반도체 패키지
KR100537893B1 (ko) 리드 프레임과 이를 이용한 적층 칩 패키지
KR200159861Y1 (ko) 반도체 패키지
KR100427541B1 (ko) 패턴 필름 제조 방법 및 이를 이용한 칩 모듈
KR100252861B1 (ko) 적층형 반도체 패키지 및 그의 어셈블리 방법
KR100195507B1 (ko) 박형 반도체 칩 패키지 소자
KR200179997Y1 (ko) 반도체패키지의 히트슬러그 구조
KR20000027519A (ko) 멀티 칩 패키지

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110325

Year of fee payment: 16

LAPS Lapse due to unpaid annual fee