KR940012549A - 반도체 펙케지 - Google Patents

반도체 펙케지 Download PDF

Info

Publication number
KR940012549A
KR940012549A KR1019920020847A KR920020847A KR940012549A KR 940012549 A KR940012549 A KR 940012549A KR 1019920020847 A KR1019920020847 A KR 1019920020847A KR 920020847 A KR920020847 A KR 920020847A KR 940012549 A KR940012549 A KR 940012549A
Authority
KR
South Korea
Prior art keywords
semiconductor
lead
semiconductor chip
bond pads
patchage
Prior art date
Application number
KR1019920020847A
Other languages
English (en)
Other versions
KR960005042B1 (ko
Inventor
송치중
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019920020847A priority Critical patent/KR960005042B1/ko
Priority to DE19934337675 priority patent/DE4337675B4/de
Priority to JP27660493A priority patent/JP3388609B2/ja
Publication of KR940012549A publication Critical patent/KR940012549A/ko
Priority to US08/409,911 priority patent/US5471088A/en
Application granted granted Critical
Publication of KR960005042B1 publication Critical patent/KR960005042B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

본 발명은 반도체 펙케지에 관한 것으로 특히, 반도체 조립 공정을 간소화하고, 반도체 제품을 소형 경박화 또는 메모리 확장을 손쉽게 할 수 있도록 한 반도체 펙케지에 관한 것이다. 이를 위하여 본 발명에서는, 다수의 본드 패드가 형성되어 있는 반도체 칩의 측면에, 제1단턱과 제1단턱보다 높은 제2단턱이 형성되어 있는 다수의 리드바가 소정의 간격으로 배열되고, 제1단턱 위에 상기 반도체 칩이 절연되게 위치하고, 다수의 본드 패드와 대응하는 위치에 있는 리드바가 금속와이어로 연결되고, 리드바의 상면과 하면만 노출되게 하고 리드바의 측면과 반도체 칩 및 금속와이어를 몰딩 컴파운드로 둘러싸도록 구성된 것이다.

Description

반도체 펙케지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 따른 반도체 펙케지의 구조를 나타낸 단면도.
제4도는 본 발명에 따른 반도체 펙케지의 접착 테이프에 부착된 예시도.
제5도는 본 발명에 따른 반도체 펙케지의 인쇄된 회로 기판에 실장한 예시도.

Claims (4)

  1. 다수의 본드 패드가 형성되어 있는 반도체 칩의 측면에, 제1단턱과 제1단턱보다 높은 제2단턱이 형성되어 있는 다수의 리드바가 소정의 간격으로 배열되고, 제1단턱 위에 상기 반도체 칩이 절연되게 위치하고, 다수의 본드 패드와 대응하는 위치에 있는 리드바가 금속와이어로 연결되고, 리드바의 상면과 하면과 노출되게 하고 리드바의 측면과 반도체 칩 및 금속와이어를 몰딩 컴파운드를 둘러싸도록 구성된 반도체 펙케지.
  2. 제1항에 있어서, 상기 다수의 리드바 밑면에 숄더를 부착하여 적층시 다수개의 반도체 펙케지가 확장되도록 한 것을 특징으로 하는 반도체 펙케지.
  3. 반도체 칩의 펙케지 방법에 있어서, (1)접착테이프위에 제1단턱과 제2단턱이 형성된 다수의 리드바를 단턱이 서로 마주보게 배열하여 부착하는 단계, (2)반도체칩을 절연성 접착제로 제1단턱을 위에 위치시키는 단계, (3)반도체칩의 본드패드와 제2단턱은 도선으로 연결시키는 단계, (4)리드바의 상하면만 남기고 리드바와 반도체 칩 및 도선을 컴파운드로 몰딩하는 단계로 이루어지는 반도체 칩 펙케지 방법.
  4. 제3단계에 있어서, 상기 (4)단계후에 접착테이프를 제거하는 단계를 추가로 구비하는 반도체 칩 펙케지 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920020847A 1992-11-07 1992-11-07 반도체 펙케지 KR960005042B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019920020847A KR960005042B1 (ko) 1992-11-07 1992-11-07 반도체 펙케지
DE19934337675 DE4337675B4 (de) 1992-11-07 1993-11-04 Verfahren zur Herstellung von stapelbaren Halbleitergehäusen
JP27660493A JP3388609B2 (ja) 1992-11-07 1993-11-05 半導体パッケージおよびその製造方法
US08/409,911 US5471088A (en) 1992-11-07 1995-03-23 Semiconductor package and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920020847A KR960005042B1 (ko) 1992-11-07 1992-11-07 반도체 펙케지

Publications (2)

Publication Number Publication Date
KR940012549A true KR940012549A (ko) 1994-06-23
KR960005042B1 KR960005042B1 (ko) 1996-04-18

Family

ID=19342670

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920020847A KR960005042B1 (ko) 1992-11-07 1992-11-07 반도체 펙케지

Country Status (4)

Country Link
US (1) US5471088A (ko)
JP (1) JP3388609B2 (ko)
KR (1) KR960005042B1 (ko)
DE (1) DE4337675B4 (ko)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3475306B2 (ja) * 1994-10-26 2003-12-08 大日本印刷株式会社 樹脂封止型半導体装置の製造方法
KR100214463B1 (ko) * 1995-12-06 1999-08-02 구본준 클립형 리드프레임과 이를 사용한 패키지의 제조방법
KR0179803B1 (ko) * 1995-12-29 1999-03-20 문정환 리드노출형 반도체 패키지
KR100186309B1 (ko) * 1996-05-17 1999-03-20 문정환 적층형 버텀 리드 패키지
US5817530A (en) * 1996-05-20 1998-10-06 Micron Technology, Inc. Use of conductive lines on the back side of wafers and dice for semiconductor interconnects
US5847458A (en) * 1996-05-21 1998-12-08 Shinko Electric Industries Co., Ltd. Semiconductor package and device having heads coupled with insulating material
KR100206910B1 (ko) * 1996-06-14 1999-07-01 구본준 반도체 패키지의 디플래쉬 방법
KR0179925B1 (ko) * 1996-06-14 1999-03-20 문정환 리드프레임 및 그를 이용한 버텀 리드 반도체 패키지
KR0179924B1 (ko) * 1996-06-14 1999-03-20 문정환 버텀리드 반도체 패키지
KR100232221B1 (ko) * 1996-12-31 1999-12-01 김영환 반도체 패키지 및 그 제조 방법
US5940687A (en) * 1997-06-06 1999-08-17 International Business Machines Corporation Wire mesh insert for thermal adhesives
KR100431315B1 (ko) * 1997-06-26 2004-10-06 주식회사 하이닉스반도체 반도체패키지및그제조방법
US6157074A (en) * 1997-07-16 2000-12-05 Hyundai Electronics Industries Co., Ltd. Lead frame adapted for variable sized devices, semiconductor package with such lead frame and method for using same
KR100271657B1 (ko) * 1998-05-30 2000-11-15 김영환 칼럼 리드형 반도체 패키지 및 그 제조방법
US6831352B1 (en) * 1998-10-22 2004-12-14 Azimuth Industrial Company, Inc. Semiconductor package for high frequency performance
JP3297387B2 (ja) 1998-11-20 2002-07-02 沖電気工業株式会社 半導体装置の製造方法
US6265761B1 (en) * 1999-05-07 2001-07-24 Maxim Integrated Products, Inc. Semiconductor devices with improved lead frame structures
KR100344927B1 (ko) * 1999-09-27 2002-07-19 삼성전자 주식회사 적층 패키지 및 그의 제조 방법
KR100426494B1 (ko) * 1999-12-20 2004-04-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이것의 제조방법
JP4637380B2 (ja) * 2001-02-08 2011-02-23 ルネサスエレクトロニクス株式会社 半導体装置
JP4598316B2 (ja) * 2001-07-06 2010-12-15 パナソニック株式会社 樹脂封止型半導体装置およびその製造方法
JP3801121B2 (ja) * 2002-08-30 2006-07-26 松下電器産業株式会社 樹脂封止型半導体装置およびその製造方法
JP3736516B2 (ja) * 2002-11-01 2006-01-18 松下電器産業株式会社 リードフレームおよびその製造方法ならびに樹脂封止型半導体装置およびその製造方法
FR2851374B1 (fr) * 2003-02-18 2005-12-16 St Microelectronics Sa Boitier-semi-conducteur a puce de circuits integres portee par les pattes de connexion electrique
US20060201709A1 (en) * 2003-04-07 2006-09-14 Mciver Chandler H Low profile small outline leadless semiconductor device package
JP3910598B2 (ja) * 2004-03-04 2007-04-25 松下電器産業株式会社 樹脂封止型半導体装置およびその製造方法
US7161232B1 (en) * 2004-09-14 2007-01-09 National Semiconductor Corporation Apparatus and method for miniature semiconductor packages
FR2917236B1 (fr) * 2007-06-07 2009-10-23 Commissariat Energie Atomique Procede de realisation de via dans un substrat reconstitue.
JP2009094118A (ja) * 2007-10-04 2009-04-30 Panasonic Corp リードフレーム、それを備える電子部品及びその製造方法
JP5167963B2 (ja) * 2007-11-02 2013-03-21 大日本印刷株式会社 樹脂封止型半導体装置とそれに用いられるエッチング加工部材、および積層型樹脂封止型半導体装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4649415A (en) * 1985-01-15 1987-03-10 National Semiconductor Corporation Semiconductor package with tape mounted die
US5060844A (en) * 1990-07-18 1991-10-29 International Business Machines Corporation Interconnection structure and test method
US5233221A (en) * 1990-10-24 1993-08-03 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology
US5227232A (en) * 1991-01-23 1993-07-13 Lim Thiam B Conductive tape for semiconductor package, a lead frame without power buses for lead on chip package, and a semiconductor device with conductive tape power distribution
US5166772A (en) * 1991-02-22 1992-11-24 Motorola, Inc. Transfer molded semiconductor device package with integral shield
KR940006164B1 (ko) * 1991-05-11 1994-07-08 금성일렉트론 주식회사 반도체 패키지 및 그 제조방법

Also Published As

Publication number Publication date
DE4337675B4 (de) 2008-04-30
JP3388609B2 (ja) 2003-03-24
KR960005042B1 (ko) 1996-04-18
JPH06209069A (ja) 1994-07-26
US5471088A (en) 1995-11-28
DE4337675A1 (de) 1994-05-11

Similar Documents

Publication Publication Date Title
KR940012549A (ko) 반도체 펙케지
US6297547B1 (en) Mounting multiple semiconductor dies in a package
US6175149B1 (en) Mounting multiple semiconductor dies in a package
US6002167A (en) Semiconductor device having lead on chip structure
US5402006A (en) Semiconductor device with enhanced adhesion between heat spreader and leads and plastic mold compound
US6261865B1 (en) Multi chip semiconductor package and method of construction
US5563443A (en) Packaged semiconductor device utilizing leadframe attached on a semiconductor chip
KR970067781A (ko) 반도체 장치와 그의 제조방법 및 집합형 반도체 장치
KR920001696A (ko) 반도체 다이를 절연시키기 위한 히트 싱크 및 다중 장착 패드 리드 프레임 패키지 및 그 방법
US4167647A (en) Hybrid microelectronic circuit package
US5818698A (en) Method and apparatus for a chip-on-board semiconductor module
KR970053679A (ko) 리드노출형 반도체 패키지
US4994897A (en) Multi-level semiconductor package
KR970013236A (ko) 금속 회로 기판을 갖는 칩 스케일 패키지
KR950030323A (ko) 반도체 장치와 반도체 장치의 생산방법 및 반도체 모듈
KR920001689A (ko) 반도체장치 및 그 제조방법
KR930014916A (ko) 반도체 패키지
KR960043132A (ko) 엘오씨(loc) 반도체 패키지 및 반도체 장치를 패키징하는 방법
KR880001053A (ko) 집적 회로용 팔라듐 도금 리이드 프레임 및 그 제조 방법
KR970024055A (ko) 동시에 절단된 반도체 칩을 이용한 고밀도 실장형 패키지 및 그 제조 방법
KR940010298A (ko) 반도체 패키지 및 그의 제조방법
KR100216065B1 (ko) 멀티 리드 온 칩 패키지
KR930009035A (ko) 접착리드를 이용한 반도체 패키지 구조 및 그 제조방법
KR20000026099A (ko) 칩크기 반도체 패키지와 그 제조방법
US20040217449A1 (en) Electronic component packaging

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110325

Year of fee payment: 16

LAPS Lapse due to unpaid annual fee