KR970053679A - 리드노출형 반도체 패키지 - Google Patents

리드노출형 반도체 패키지 Download PDF

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KR970053679A
KR970053679A KR1019950067335A KR19950067335A KR970053679A KR 970053679 A KR970053679 A KR 970053679A KR 1019950067335 A KR1019950067335 A KR 1019950067335A KR 19950067335 A KR19950067335 A KR 19950067335A KR 970053679 A KR970053679 A KR 970053679A
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lead
substrate connection
semiconductor chip
connection lead
semiconductor package
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KR1019950067335A
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KR0179803B1 (ko
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송치중
이주화
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문정환
Lg 반도체 주식회사
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Priority to KR1019950067335A priority Critical patent/KR0179803B1/ko
Priority to US08/701,949 priority patent/US5770888A/en
Priority to CN96109458A priority patent/CN1065662C/zh
Priority to TW085110298A priority patent/TW344887B/zh
Priority to JP34529096A priority patent/JP2992814B2/ja
Publication of KR970053679A publication Critical patent/KR970053679A/ko
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Publication of KR0179803B1 publication Critical patent/KR0179803B1/ko

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Abstract

본 발명은 패키지의 상하면으로 제1 및 제2 기판접속리드가 노출되도록 몰딩시켜 패키지를 형성하므로써 다수개의 패키지를 적층시켜 용량확장이 가능하도록 된 리드노출형 반도체 패키지에 관한 것으로, 그 구성은 다수개의 본드패드가 다수개의 본드패드가 그의 하면에 형성된 반도체칩(21)과, 그의 상면에 상기 반도체칩(21)을 지지하는 제1 기판연결리드(22a)와 상기 제1 기판연결리드(22a)로부터 소정높이(h)를 가지도록 연장형성된 제2 기판연결리드(22b)를 포함하여 구성된 리드프레임(22)과, 상기 제1 기판연결리드(22a)와 상기 반도체칩(21) 사이에 개재되어 상기 반도체칩(21)을 상기 제1 기판연결리드(22a)의 상면에 고정시키는 접착부재(23)와, 상기 반도체칩(21)의 하면에 형성된 다수개의 본드패드와 상기 제2 기판연결리드(22b)의 하면을 전기적으로 연결시키는 금속와이어(24)와, 상기 반도체칩(21)과, 상기 제1 및 제2 기판연결리드(22a, 22b)를 포함하는 소정체적을 패키지의 하면 및 상면으로 상기 제1 기판연결리드(22a)의 하면과 제2 기판연결리드(22b)의 상면이 노출되도록 밀봉하는 수지(26)를 포함하여 구성된다.

Description

리드노출형 반도체 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 따른 리드노출형 반도체 패키지의 제1실시예를 나타낸 단면도.

Claims (11)

  1. 다수개의 본드패드가 그의 하면에 형성된 반도체칩(21)과, 그의 상면에 상기 반도체칩(21)을 지지하는 제1 기판연결리드(22a)와 상기 제1 기판연결리드(22a)로부터 소정높이(h)의 단차를 가지도록 연장형성된 제2 기판연결리드(22b)를 포함하여 구성된 리드프레임(22)과, 상기 제1 기판연결리드(22a)와 상기 반도체칩(21) 사이에 개재되어 상기 반도체칩(21)을 상기 제1 기판연결리드(22a)의 상면에 고정시키는 접착부재(23)와, 상기 반도체칩(21)의 하면에 형성된 다수개의 본드패드와 상기 제2 기판연결리드(22b)의 하면을 전기적으로 연결시키는 금속와이어(24)와, 상기 반도체칩(21)과, 상기 제1 및 제2 기판연결리드(22a, 22b)를 포함하는 소정체적을 패키지의 하면 및 상면으로 상기 제1 기판연결리드(22a)의 하면과 제2 기판연결리드(22b)의 상면이 노출되도록 밀봉하는 수지(26)를 포함하여 구성된 것을 특징으로 하는 리드노출형 반도체 패키지.
  2. 제1항에 있어서, 상기 반도체칩(21)의 다수개의 본드패드와 제2 기판연결리드(22b)는 지그재그(zig-zag)형태로 금속와이어(24)에 의해 전기적으로 연결된 것을 특징으로 하는 리드노출형 반도체 패키지.
  3. 제1항에 있어서, 상기 접착부재(23)는 절연성 양면테이프인 것을 특징으로 하는 리드노출형 반도체 패키지.
  4. 제1항에 있어서, 상기 접착부재(23)는 절연성 페이스트 접착제인 것을 특징으로 하는 리드노출형 반도체 패키지.
  5. 제1항에 있어서, 상기 접착부재(23)는 에폭시계 테이프인 것을 특징으로 하는 리드노출형 반도체 패키지.
  6. 제1항에 있어서, 상기 접착부재(23)는 폴리이미드계 테이프인 것을 특징으로 하는 리드노출형 반도체 패키지.
  7. 다수개의 본드패드가 그의 하면에 형성된 반도체칩(21)과, 그의 상면에 상기 반도체칩(21)을 지지하는 제1 기판연결리드(22a)와 상기 제1 기판연결리드(22b)로부터 소정높이(h)의 단차를 가지고 연장형성된 제2 기판연결리드(22b)를 포함항 구성된 리드드레임(22)과, 상기 제1 기판연결리드(22a)와 상기 반도체칩(21)의 사이에 개재되어 상기 반도체칩(21)을 상기 제1 기판연결리드(22a)의 상면에 고정시키는 접착부재(23)와, 상기 제1 기판연결리드(22a)의 상면에 형성되어 상기 반도체칩(21)의 하면에 형성된 다수개의 본드패드와 전기적으로 연결시키는 솔더범프(25)와, 상기 반도체칩(21)과, 상기 제1 및 제2 기판연결리드(22a, 22b)를 포함하는 소정체적을 패키지의 하면 및 상면으로 상기 제1 기판연결리드(22a)의 하면과 제1 기판연결리드(22b)의 상면이 노출되도록 밀봉하는 수지(26)를 포함하여 구성된 것을 특징으로 하는 리드노출형 반도체 패키지.
  8. 제7항에 있어서, 상기 접착부재(23)는 절연성 양면테이프인 것을 특징으로 하는 리드노출형 반도체 패키지.
  9. 제7항에 있어서, 상기 접착부재(23)는 절연성 페이스트 접착제인 것을 특징으로 하는 리드노출형 반도체 패키지.
  10. 제7항에 있어서, 상기 접착부재(23)는 에폭시계 테이프인 것을 특징으로 하는 리드노출형 반도체 패키지.
  11. 제7항에 있어서, 상기 접착부재(23)는 폴리이미드계 테이프인 것을 특징으로 하는 리드노출형 반도체 패키지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950067335A 1995-12-29 1995-12-29 리드노출형 반도체 패키지 KR0179803B1 (ko)

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KR1019950067335A KR0179803B1 (ko) 1995-12-29 1995-12-29 리드노출형 반도체 패키지
US08/701,949 US5770888A (en) 1995-12-29 1996-08-23 Integrated chip package with reduced dimensions and leads exposed from the top and bottom of the package
CN96109458A CN1065662C (zh) 1995-12-29 1996-08-23 半导体芯片封装及其制造方法
TW085110298A TW344887B (en) 1995-12-29 1996-08-23 An improved integrated chip package with reduced dimensions
JP34529096A JP2992814B2 (ja) 1995-12-29 1996-12-25 半導体パッケージ

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CN1153997A (zh) 1997-07-09
CN1065662C (zh) 2001-05-09
KR0179803B1 (ko) 1999-03-20
US5770888A (en) 1998-06-23
JP2992814B2 (ja) 1999-12-20

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