JP2992814B2 - 半導体パッケージ - Google Patents
半導体パッケージInfo
- Publication number
- JP2992814B2 JP2992814B2 JP34529096A JP34529096A JP2992814B2 JP 2992814 B2 JP2992814 B2 JP 2992814B2 JP 34529096 A JP34529096 A JP 34529096A JP 34529096 A JP34529096 A JP 34529096A JP 2992814 B2 JP2992814 B2 JP 2992814B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- lead frame
- semiconductor package
- semiconductor
- tip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
脂モールドされた形態の半導体パッケージに係わるもの
で、詳しくは、上下側面にリードが露出した半導体パッ
ケージの構成に関するものである。
国特許第5,428,248 号に記載されたものが知られてい
る。このものは、図7に示すように、基板に接続された
接続部12aと該接続部12aから屈曲延長されたチップ接
続部12bとを有するリードフレーム12と、該リードフレ
ーム12の接続部12a上に接着剤13により接着された半導
体チップ11と、該半導体チップ11上面と前記リードフレ
ーム12の接着部12bとに接続された金属ワイヤ14と、を
備え、これらのリードフレーム12、半導体チップ11及び
金属ワイヤ14がモールド樹脂15により密封成形された
後、前記リードフレーム12の接続部12a下面及び接続部
12b側面が夫々外部に露出するように構成されている。
パッケージにおいては、リードフレーム12は成形体の下
面又は側面のみ露出し、上面には露出していないため、
複数の半導体装置を半導体パッケージに実装したまま積
層して接続することはできず、メモリ容量の拡大を図る
ようなことはできなかった。
部位が少なく、半導体チップからの発生熱を、この露出
部位のみから放熱したのでは、該熱を充分に放熱し得
ず、半導体装置の作動効率を向上し得ないという不都合
な点があった。さらに、金属ワイヤ14の接続部位が半導
体チップ11及びリードフレーム12の接続12bの上面に位
置しているため、モールド樹脂により成形された成形体
のサイズが大きくなって半導体パッケージのコンパクト
化を図り得ないという下都合な点があった。
されたもので、半導体チップメモリの容量を拡大しなが
らコンパクト化を図り、かつ、半導体チップの発生熱を
外部に効率的に放熱し得る半導体パッケージを提供する
ことを目的とする。
明では、ボンドパッド面を下面に有する半導体チップを
実装する半導体パッケージであって、基端部及び先端部
を有し、前記基端部は前記半導体チップ下面に付着され
て前記半導体チップの下面と略平行に外方へ延び、前記
先端部は基端部の延長端から上向きに延びて屈曲して段
差をなし半導体チップの上面と略平行に外方へ延びた複
数のリードフレームと、前記半導体チップのボンドパッ
ド面に形成されたボンドパッドと前記先端部の下面とを
電気的に接続する複数の接続手段と、前記リードフレー
ムの基端部下面及び先端部上面が露出するように、半導
体チップ、リードフレーム及び接続手段を密封成形した
絶縁性のモールド樹脂と、を備えている。
半導体チップ、リードフレーム、及び接続手段が密封成
形される際、リードフレームの基端部下面及び先端部上
面の2面が露出されるとともに、接続手段がボンドパッ
ド面に形成されたボンドパッドと前記先端部の下面とを
電気的に接続する。
の先端部側面もモールド樹脂から露出するように構成さ
れている。かかる構成によれば、リードフレームの先端
部もモールド樹脂から露出しているので、横方向につい
ても半導体チップの接続が可能となる。
記ボンドパッドと前記先端部の下面をジグザグ状に接続
した金属ワイヤである。 かかる構成によれば、ワイヤフ
レームの先端部下面とボンドパッドとが金属ワイヤによ
って、夫々ジグザグ状に接続される。
面に有する半導体チップを実装する半導体パッケージで
あって、基端部及び先端部を有し、前記基端部は前記半
導体チップ下面に付着されて前記半導体チップの下面と
略平行に外方へ延び、前記先端部は基端部の延長端から
上向きに延びて屈曲して段差をなし半導体チップの上面
と略平行に外方へ延びた複数のリードフレームと、前記
半導体チップのボンドパッド面に形成されたボンドパッ
ドと前記基端部の上面とを電気的に接続する複数の接続
手段と、前記リードフレームの基端部下面及び先端部上
面が露出するように、半導体チップ、リードフレーム及
び接続手段を密封成形した絶縁性のモールド樹脂と、を
備えている。
半導体チップ、リードフレーム、及び接続手段が密封成
形される際、リードフレームの基端部下面及び先端部上
面の2面が露出されるとともに、接続手段がボンドパッ
ド面に形成されたボンドパッドと前記基端部の上面とを
電気的に接続する。
に基づいて説明する。まず、本発明に係る半導体パッケ
ージの第1の実施の形態について説明する。第1の実施
の形態においては、図1に示すように、半導体チップ21
に接続された基端部としての第1基板接続部22aと該第
1基板接続部22aから所定高さhの段をなすように上方
向き延長形成された先端部としての第2基板接続部22b
と、を有した複数のリードフレーム22と、これらのリー
ドフレーム22の第1基板接続部22a上に接着剤23により
接着された半導体チップ21と、該半導体チップ21下面と
各リードフレーム22の第2基板接続部22b下面とに夫々
接続された複数の金属ワイヤ24と、を備え、これらの半
導体チップ21、リードフレーム22及び金属ワイヤ24が、
モールド樹脂26により密封成形され、各リードフレーム
22の第1基板接続部22a下面と第2基板接続部22b上面
及び側面とが夫々外部に露出するように構成されてい
る。
封成形する前、密封成形した後の半導体パッケージの底
面を示す。図2で示すように、前記各リードフレーム22
の第2基板接続部22bの下面は、半導体チップ21下面に
夫々形成されたボンドパッドと前記各金属ワイヤ24によ
り夫々ジグザグ(zig-zag) 状に電気的に接続され、これ
らのリードフレーム22の第1基板接続部22a下面は夫々
露出して、実装の際、印刷回路基板上の金属パターンに
電気的に接続される。
エボキシ系の絶縁性両面テープ若しくは絶縁性のペース
ト接着剤が用いられる。尚、前記所定高さhは、図1に
示すように、リード22の板厚に接着剤23の厚さ、半導体
チップ21の厚さを加えた厚さよりも高くなるように設定
される。このように構成することにより、半導体チップ
からの発生熱を放熱する露出部位が基端部の下面、先端
部の上面の2面となり、放熱面積が広くなる。従って、
半導体チップ内の発生熱を外部に効率的に放熱し、半導
体パッケージの作動能率を向上し得るという効果があ
る。
半導体パッケージに実装したまま、複数個積層して用い
ることもできる。このように複数個積層した半導体装置
を用いることにより、単位面積当たりの半導体チップメ
モリの処理容量が増大するため、小型化を図りながらメ
モリ容量を増大させることができる。かかる構造を有す
る半導体パッケージを製造するには、ウェーハ(wafer)
から各半導体チップをカッター等で分離する切断(sawin
g)工程と、各リードフレーム22を夫々所定間隔に配列
し、これらのリードフレーム22の第1基板接続部22a上
に接着剤23により前記半導体チップ21を接着する接着工
程と、該半導体チップ21下面の各ボンドパットと各リー
ドフレーム22の第2基板接続部22bとを、夫々、金属ワ
イヤ24により接続する接続工程と、これらの半導体チッ
プ21、リードフレーム22及び金属ワイヤ24をモールド樹
脂26により成形し、リードフレーム22の第1基板接続部
22a下面と第2基板連続部22b上面及び側面とを夫々露
出させるモールド工程と、を順次行う。
導体装置は、トレイ(tray)又はチューブ(tube)を用いて
電気的特性試験が行われた後、印刷回路基板上に実装さ
れる。次に、本発明に係る半導体パッケージの第2の実
施の形態について説明する。このものは、金属ワイヤの
代わりにソルダーバンプを用いるようにしたものであ
る。
ように、基板に接続された第1基板接続部22aと該第1
基板接続部22aから所定高さhの段をなすように上方向
き延長形成された第2基板接続部22bとを有した複数の
リードフレーム22と、これらのリードフレーム22の第l
基板接続部22a上に接着剤で接着された半導体チップ21
と、該半導体チップ21の下面と各リードフレーム22の第
1基板接続部22a上面と夫々接続された複数のソルダー
バンプ25と、を備え、これらの半導体チップ21,リード
フレーム22及びソルダーバンプ25がモールド樹脂26によ
り密封成形された後、各リードフレーム22の第1基板接
続部22a下面と第2基板接続部22b上面及び側面とが夫
々外部に露出して構成されている。
接続部22aが露出した下面は、夫々、実装の際、印刷回
路基板上の金属パターンに、第1の実施の形態と同様に
電気的に接続される。又、前記接着剤は、第1の実施の
形態と同様に、ポリイミド系又はエポキシ系の絶縁性両
面テープ若しくは絶縁性ペースト接着剤が用いられる。
用いて半導体チップ21の下面と第1基板接続部22aとを
接続することができる。尚、図4と同様に、半導体チッ
プ21を半導体パッケージに実装したまま、図6に示すよ
うに複数個積層して用いることもでき、複数個積層した
半導体装置を用いることにより、半導体パッケージの小
型化を図りながらメモリの処理能力を増大させることが
できる。
造するには、第1の実施の形態と同様に、切断工程と、
接着工程と、を行い、接続工程では、前記リードフレー
ム22の第l基板接続部22a上面と前記半導体チップ21下
面とを夫々ソルダーバンプ25により接続する。そして、
モールド工程において、これらの半導体チップ21、リー
ドフレーム22及びソルダーパンプ25をモールド樹脂26に
より成形し、リードフレーム22の第1基板接続部22a下
面と第2基板連続部22b上面及び側面とを夫々露出させ
る。
体パッケージに実装された半導体装置は、トレイ又はチ
ューブを用いて電気的特性試験が行われた後、印刷回路
基板上に実装される。
係る半導体パッケージによれば、複数のものを積層する
ことができるため、成形体の高さが低くなり、パッケー
ジのコンパクト化を図りながらメモリ容量を増大し得る
という効果がある。且つ、成形体の上下の2面に各リー
ドフレームの基端部及び先端部が露出するため、放熱面
積が広くなり、半導体チップ内の発生熱を外部に効率的
に放熱し、半導体パッケージの作動能率を向上し得ると
いう効果がある。
よれば、半導体パッケージの側面方向に半導体チップを
接続してメモリ容量を増やすことができる。請求項3の
発明に係る半導体パッケージによれば、金属ワイヤとリ
ードフレームとの干渉を防止することができる。
よれば、パッケージのコンパクト化、メモリ容量の増
大、更に、放熱効果の増大による半導体パッケージの作
動能率の向上を図れると共に、ボンドパッドと基端部の
上面とが電気的に接続されるので接続手段を短くするこ
とができ、製造コストを抑制すると共に信頼性が高い半
導体パッケージとすることができる。
形態の構造を示す断面図。
図。
図。
形態の構造を示す縦断面図。
ージを積層した構造を示す縦断面図。
ージを積層した構造を示す縦断面図。
図。
Claims (4)
- 【請求項1】ボンドパッド面を下面に有する半導体チッ
プ(21)を実装する半導体パッケージであって、 基端部(22a)及び先端部(22b)を有し、前記基
端部(22a)は前記半導体チップ(21)下面に付着
されて前記半導体チップ(21)の下面と略平行に外方
へ延び、前記先端部(22b)は基端部(22a)の延
長端から上向きに延びて屈曲して段差をなし半導体チッ
プ(21)の上面と略平行に外方へ延びた複数のリード
フレーム(22)と、 前記半導体チップ(21)のボンドパッド面に形成され
たボンドパッドと前記先端部(22b)の下面とを電気
的に 接続する複数の接続手段と、 前記リードフレーム(22)の基端部(22a)下面及
び先端部(22b)上面が露出するように、半導体チッ
プ(21)、リードフレーム(22)及び接続手段を密
封成形した絶縁性のモールド樹脂(26)と、 を備えたことを特徴とする半導体パッケージ。 - 【請求項2】前記リードフレームの先端部(22b)側
面もモールド樹脂(26)から露出するように構成され
たことを特徴とする請求項1記載の半導体パッケージ。 - 【請求項3】前記接続手段は、前記ボンドパッドと前記
先端部(22b)下面をジグザグ状に接続した金属ワイ
ヤ(24)であることを特徴とする請求項1又は請求項
2記載の半導体パッケージ。 - 【請求項4】ボンドパッド面を下面に有する半導体チッ
プ(21)を実装する半導体パッケージであって、 基端部(22a)及び先端部(22b)を有し、前記基
端部(22a)は前記半導体チップ(21)下面に付着
されて前記半導体チップ(21)の下面と略平行に外方
へ延び、前記先端部(22b)は基端部(22a)の延
長端から上向きに延びて屈曲して段差をなし半導体チッ
プ(21)の上面と略平行に外方へ延び た複数のリード
フレーム(22)と、 前記半導体チップ(21)のボンドパッド面に形成され
たボンドパッドと前記基端部(22a)の上面とを電気
的に接続する複数の接続手段と、 前記リードフレーム(22)の基端部(22a)下面及
び先端部(22b)上面が露出するように、半導体チッ
プ(21)、リードフレーム(22)及び接続手段を密
封成形した絶縁性のモールド樹脂(26)と、を備えた
ことを特徴とする 半導体パッケージ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950067335A KR0179803B1 (ko) | 1995-12-29 | 1995-12-29 | 리드노출형 반도체 패키지 |
KR67335/1995 | 1995-12-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09326452A JPH09326452A (ja) | 1997-12-16 |
JP2992814B2 true JP2992814B2 (ja) | 1999-12-20 |
Family
ID=19447662
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP34529096A Expired - Fee Related JP2992814B2 (ja) | 1995-12-29 | 1996-12-25 | 半導体パッケージ |
Country Status (5)
Country | Link |
---|---|
US (1) | US5770888A (ja) |
JP (1) | JP2992814B2 (ja) |
KR (1) | KR0179803B1 (ja) |
CN (1) | CN1065662C (ja) |
TW (1) | TW344887B (ja) |
Families Citing this family (115)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09260538A (ja) | 1996-03-27 | 1997-10-03 | Miyazaki Oki Electric Co Ltd | 樹脂封止型半導体装置及び製造方法とその実装構造 |
US5731244A (en) * | 1996-05-28 | 1998-03-24 | Micron Technology, Inc. | Laser wire bonding for wire embedded dielectrics to integrated circuits |
KR100242994B1 (ko) * | 1996-12-28 | 2000-02-01 | 김영환 | 버텀리드프레임 및 그를 이용한 버텀리드 반도체 패키지 |
KR100214544B1 (ko) * | 1996-12-28 | 1999-08-02 | 구본준 | 볼 그리드 어레이 반도체 패키지 |
KR100237051B1 (ko) * | 1996-12-28 | 2000-01-15 | 김영환 | 버텀리드 반도체 패키지 및 그 제조 방법 |
KR100214561B1 (ko) * | 1997-03-14 | 1999-08-02 | 구본준 | 버틈 리드 패키지 |
JP2954110B2 (ja) * | 1997-09-26 | 1999-09-27 | 九州日本電気株式会社 | Csp型半導体装置及びその製造方法 |
US6143981A (en) | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
US6168975B1 (en) * | 1998-06-24 | 2001-01-02 | St Assembly Test Services Pte Ltd | Method of forming extended lead package |
KR100293815B1 (ko) * | 1998-06-30 | 2001-07-12 | 박종섭 | 스택형 패키지 |
DE19844966A1 (de) * | 1998-09-30 | 2000-01-13 | Siemens Ag | Halbleiterbauteil sowie dieses umfassender Chipkartenmodul |
KR100319616B1 (ko) * | 1999-04-17 | 2002-01-05 | 김영환 | 리드프레임 및 이를 이용한 버텀리드 반도체패키지 |
US6265761B1 (en) * | 1999-05-07 | 2001-07-24 | Maxim Integrated Products, Inc. | Semiconductor devices with improved lead frame structures |
US6420779B1 (en) | 1999-09-14 | 2002-07-16 | St Assembly Test Services Ltd. | Leadframe based chip scale package and method of producing the same |
KR100344927B1 (ko) * | 1999-09-27 | 2002-07-19 | 삼성전자 주식회사 | 적층 패키지 및 그의 제조 방법 |
KR100379089B1 (ko) | 1999-10-15 | 2003-04-08 | 앰코 테크놀로지 코리아 주식회사 | 리드프레임 및 이를 이용한 반도체패키지 |
JP3602997B2 (ja) * | 1999-12-15 | 2004-12-15 | 松下電器産業株式会社 | 半導体装置及び半導体装置の製造方法 |
KR100421774B1 (ko) * | 1999-12-16 | 2004-03-10 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 및 그 제조 방법 |
KR100370851B1 (ko) * | 1999-12-30 | 2003-02-05 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
US7042068B2 (en) | 2000-04-27 | 2006-05-09 | Amkor Technology, Inc. | Leadframe and semiconductor package made using the leadframe |
JP4637380B2 (ja) * | 2001-02-08 | 2011-02-23 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US6545345B1 (en) | 2001-03-20 | 2003-04-08 | Amkor Technology, Inc. | Mounting for a package containing a chip |
KR100369393B1 (ko) | 2001-03-27 | 2003-02-05 | 앰코 테크놀로지 코리아 주식회사 | 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법 |
US6603196B2 (en) * | 2001-03-28 | 2003-08-05 | Siliconware Precision Industries Co., Ltd. | Leadframe-based semiconductor package for multi-media card |
JP4598316B2 (ja) * | 2001-07-06 | 2010-12-15 | パナソニック株式会社 | 樹脂封止型半導体装置およびその製造方法 |
DE10147376B4 (de) * | 2001-09-26 | 2009-01-15 | Infineon Technologies Ag | Elektronisches Bauteil und Systemträger sowie Verfahren zur Herstellung derselben |
DE10147375B4 (de) * | 2001-09-26 | 2006-06-08 | Infineon Technologies Ag | Elektronisches Bauteil mit einem Halbleiterchip und Verfahren zur Herstellung desselben |
US6608366B1 (en) | 2002-04-15 | 2003-08-19 | Harry J. Fogelson | Lead frame with plated end leads |
US6919620B1 (en) | 2002-09-17 | 2005-07-19 | Amkor Technology, Inc. | Compact flash memory card with clamshell leadframe |
US6905914B1 (en) | 2002-11-08 | 2005-06-14 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US7723210B2 (en) | 2002-11-08 | 2010-05-25 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US8129222B2 (en) * | 2002-11-27 | 2012-03-06 | United Test And Assembly Test Center Ltd. | High density chip scale leadframe package and method of manufacturing the package |
US20040124508A1 (en) * | 2002-11-27 | 2004-07-01 | United Test And Assembly Test Center Ltd. | High performance chip scale leadframe package and method of manufacturing the package |
US6798047B1 (en) | 2002-12-26 | 2004-09-28 | Amkor Technology, Inc. | Pre-molded leadframe |
US6750545B1 (en) | 2003-02-28 | 2004-06-15 | Amkor Technology, Inc. | Semiconductor package capable of die stacking |
US6927483B1 (en) | 2003-03-07 | 2005-08-09 | Amkor Technology, Inc. | Semiconductor package exhibiting efficient lead placement |
US6794740B1 (en) | 2003-03-13 | 2004-09-21 | Amkor Technology, Inc. | Leadframe package for semiconductor devices |
US20060201709A1 (en) * | 2003-04-07 | 2006-09-14 | Mciver Chandler H | Low profile small outline leadless semiconductor device package |
US6879034B1 (en) | 2003-05-01 | 2005-04-12 | Amkor Technology, Inc. | Semiconductor package including low temperature co-fired ceramic substrate |
US6921967B2 (en) | 2003-09-24 | 2005-07-26 | Amkor Technology, Inc. | Reinforced die pad support structure |
US7568059B2 (en) * | 2004-07-08 | 2009-07-28 | Asocs Ltd. | Low-power reconfigurable architecture for simultaneous implementation of distinct communication standards |
JP2006190972A (ja) * | 2004-12-08 | 2006-07-20 | Mitsubishi Electric Corp | 電力用半導体装置 |
US20090327546A1 (en) * | 2005-03-03 | 2009-12-31 | Gaby Guri | System for and method of hand-off between different communication standards |
KR100630741B1 (ko) * | 2005-03-04 | 2006-10-02 | 삼성전자주식회사 | 다중 몰딩에 의한 적층형 반도체 패키지 및 그 제조방법 |
US7968377B2 (en) * | 2005-09-22 | 2011-06-28 | Stats Chippac Ltd. | Integrated circuit protruding pad package system |
US7507603B1 (en) | 2005-12-02 | 2009-03-24 | Amkor Technology, Inc. | Etch singulated semiconductor package |
US7572681B1 (en) | 2005-12-08 | 2009-08-11 | Amkor Technology, Inc. | Embedded electronic component package |
US7385299B2 (en) * | 2006-02-25 | 2008-06-10 | Stats Chippac Ltd. | Stackable integrated circuit package system with multiple interconnect interface |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US7968998B1 (en) | 2006-06-21 | 2011-06-28 | Amkor Technology, Inc. | Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package |
US7683461B2 (en) * | 2006-07-21 | 2010-03-23 | Stats Chippac Ltd. | Integrated circuit leadless package system |
US7687892B2 (en) * | 2006-08-08 | 2010-03-30 | Stats Chippac, Ltd. | Quad flat package |
US7687893B2 (en) | 2006-12-27 | 2010-03-30 | Amkor Technology, Inc. | Semiconductor package having leadframe with exposed anchor pads |
US7829990B1 (en) | 2007-01-18 | 2010-11-09 | Amkor Technology, Inc. | Stackable semiconductor package including laminate interposer |
US7982297B1 (en) | 2007-03-06 | 2011-07-19 | Amkor Technology, Inc. | Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same |
US7977774B2 (en) | 2007-07-10 | 2011-07-12 | Amkor Technology, Inc. | Fusion quad flat semiconductor package |
US7687899B1 (en) | 2007-08-07 | 2010-03-30 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
US7868471B2 (en) * | 2007-09-13 | 2011-01-11 | Stats Chippac Ltd. | Integrated circuit package-in-package system with leads |
US7777351B1 (en) | 2007-10-01 | 2010-08-17 | Amkor Technology, Inc. | Thin stacked interposer package |
US8089159B1 (en) | 2007-10-03 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor package with increased I/O density and method of making the same |
JP2009094118A (ja) * | 2007-10-04 | 2009-04-30 | Panasonic Corp | リードフレーム、それを備える電子部品及びその製造方法 |
US7847386B1 (en) | 2007-11-05 | 2010-12-07 | Amkor Technology, Inc. | Reduced size stacked semiconductor package and method of making the same |
US7977782B2 (en) * | 2007-11-07 | 2011-07-12 | Stats Chippac Ltd. | Integrated circuit package system with dual connectivity |
US7956453B1 (en) | 2008-01-16 | 2011-06-07 | Amkor Technology, Inc. | Semiconductor package with patterning layer and method of making same |
US7723852B1 (en) | 2008-01-21 | 2010-05-25 | Amkor Technology, Inc. | Stacked semiconductor package and method of making same |
US8063474B2 (en) * | 2008-02-06 | 2011-11-22 | Fairchild Semiconductor Corporation | Embedded die package on package (POP) with pre-molded leadframe |
US8067821B1 (en) | 2008-04-10 | 2011-11-29 | Amkor Technology, Inc. | Flat semiconductor package with half package molding |
US7768135B1 (en) | 2008-04-17 | 2010-08-03 | Amkor Technology, Inc. | Semiconductor package with fast power-up cycle and method of making same |
US7808084B1 (en) | 2008-05-06 | 2010-10-05 | Amkor Technology, Inc. | Semiconductor package with half-etched locking features |
US8125064B1 (en) | 2008-07-28 | 2012-02-28 | Amkor Technology, Inc. | Increased I/O semiconductor package and method of making same |
US8184453B1 (en) | 2008-07-31 | 2012-05-22 | Amkor Technology, Inc. | Increased capacity semiconductor package |
US7847392B1 (en) | 2008-09-30 | 2010-12-07 | Amkor Technology, Inc. | Semiconductor device including leadframe with increased I/O |
US7989933B1 (en) | 2008-10-06 | 2011-08-02 | Amkor Technology, Inc. | Increased I/O leadframe and semiconductor device including same |
US8008758B1 (en) | 2008-10-27 | 2011-08-30 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe |
US8089145B1 (en) | 2008-11-17 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor device including increased capacity leadframe |
US8072050B1 (en) | 2008-11-18 | 2011-12-06 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including passive device |
US7875963B1 (en) | 2008-11-21 | 2011-01-25 | Amkor Technology, Inc. | Semiconductor device including leadframe having power bars and increased I/O |
US7982298B1 (en) | 2008-12-03 | 2011-07-19 | Amkor Technology, Inc. | Package in package semiconductor device |
US8487420B1 (en) | 2008-12-08 | 2013-07-16 | Amkor Technology, Inc. | Package in package semiconductor device with film over wire |
CN101764127B (zh) * | 2008-12-23 | 2012-01-04 | 日月光封装测试(上海)有限公司 | 无外引脚的半导体封装体及其堆迭构造 |
US20170117214A1 (en) | 2009-01-05 | 2017-04-27 | Amkor Technology, Inc. | Semiconductor device with through-mold via |
US8680656B1 (en) | 2009-01-05 | 2014-03-25 | Amkor Technology, Inc. | Leadframe structure for concentrated photovoltaic receiver package |
US8058715B1 (en) | 2009-01-09 | 2011-11-15 | Amkor Technology, Inc. | Package in package device for RF transceiver module |
US8026589B1 (en) | 2009-02-23 | 2011-09-27 | Amkor Technology, Inc. | Reduced profile stackable semiconductor package |
US7960818B1 (en) | 2009-03-04 | 2011-06-14 | Amkor Technology, Inc. | Conformal shield on punch QFN semiconductor package |
US8575742B1 (en) | 2009-04-06 | 2013-11-05 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including power bars |
USRE48111E1 (en) | 2009-08-21 | 2020-07-21 | JCET Semiconductor (Shaoxing) Co. Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
US8169058B2 (en) | 2009-08-21 | 2012-05-01 | Stats Chippac, Ltd. | Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars |
US8383457B2 (en) | 2010-09-03 | 2013-02-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
US8796561B1 (en) | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
US9391005B2 (en) * | 2009-10-27 | 2016-07-12 | Alpha And Omega Semiconductor Incorporated | Method for packaging a power device with bottom source electrode |
US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
US8324511B1 (en) | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US8294276B1 (en) | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
JP2012069764A (ja) | 2010-09-24 | 2012-04-05 | On Semiconductor Trading Ltd | 回路装置およびその製造方法 |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
US8791501B1 (en) | 2010-12-03 | 2014-07-29 | Amkor Technology, Inc. | Integrated passive device structure and method |
US8390130B1 (en) | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
TWI557183B (zh) | 2015-12-16 | 2016-11-11 | 財團法人工業技術研究院 | 矽氧烷組成物、以及包含其之光電裝置 |
US8648450B1 (en) | 2011-01-27 | 2014-02-11 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands |
BRPI1103019A2 (pt) * | 2011-06-21 | 2013-07-16 | Whirlpool Sa | conector para compressores hermÉticos |
US8552548B1 (en) | 2011-11-29 | 2013-10-08 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
CN103187381B (zh) * | 2011-12-30 | 2015-09-16 | 联咏科技股份有限公司 | 导线架封装结构 |
US9704725B1 (en) | 2012-03-06 | 2017-07-11 | Amkor Technology, Inc. | Semiconductor device with leadframe configured to facilitate reduced burr formation |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
KR101486790B1 (ko) | 2013-05-02 | 2015-01-28 | 앰코 테크놀로지 코리아 주식회사 | 강성보강부를 갖는 마이크로 리드프레임 |
KR101563911B1 (ko) | 2013-10-24 | 2015-10-28 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 |
US9673122B2 (en) | 2014-05-02 | 2017-06-06 | Amkor Technology, Inc. | Micro lead frame structure having reinforcing portions and method |
JP6262086B2 (ja) * | 2014-07-04 | 2018-01-17 | アルプス電気株式会社 | 圧力検出装置 |
CN104600045B (zh) * | 2015-01-30 | 2017-06-06 | 无锡中感微电子股份有限公司 | 电路系统、芯片封装及其封装方法 |
US9917041B1 (en) * | 2016-10-28 | 2018-03-13 | Intel Corporation | 3D chip assemblies using stacked leadframes |
FR3104317A1 (fr) * | 2019-12-04 | 2021-06-11 | Stmicroelectronics (Tours) Sas | Procédé de fabrication de puces électroniques |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6089945A (ja) * | 1983-10-24 | 1985-05-20 | Matsushita Electric Works Ltd | 封止半導体装置 |
JPH071793B2 (ja) * | 1985-07-23 | 1995-01-11 | 松下電器産業株式会社 | ハイブリツド光ic装置 |
US4857989A (en) * | 1986-09-04 | 1989-08-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
JPS63182845A (ja) * | 1987-01-23 | 1988-07-28 | Nec Ic Microcomput Syst Ltd | 半導体装置 |
JPH01232753A (ja) * | 1988-03-14 | 1989-09-18 | Matsushita Electron Corp | 半導体装置 |
JP2530056B2 (ja) * | 1989-09-14 | 1996-09-04 | 株式会社東芝 | 樹脂封止型半導体装置及びその製造方法 |
JPH03250657A (ja) * | 1990-02-28 | 1991-11-08 | Hitachi Ltd | 表裏両面実装可能な樹脂封止型半導体装置 |
US5157480A (en) * | 1991-02-06 | 1992-10-20 | Motorola, Inc. | Semiconductor device having dual electrical contact sites |
FR2673042A1 (fr) * | 1991-02-18 | 1992-08-21 | Em Microelectronic Marin Sa | Module electronique resistant aux deformations mecaniques pour carte a microcircuits. |
JPH04284661A (ja) * | 1991-03-13 | 1992-10-09 | Toshiba Corp | 半導体装置 |
US5214307A (en) * | 1991-07-08 | 1993-05-25 | Micron Technology, Inc. | Lead frame for semiconductor devices having improved adhesive bond line control |
KR930014916A (ko) * | 1991-12-24 | 1993-07-23 | 김광호 | 반도체 패키지 |
JP3124381B2 (ja) * | 1992-07-07 | 2001-01-15 | 株式会社日立製作所 | 半導体装置及び実装構造体 |
KR0128251Y1 (ko) * | 1992-08-21 | 1998-10-15 | 문정환 | 리드 노출형 반도체 조립장치 |
KR960005042B1 (ko) * | 1992-11-07 | 1996-04-18 | 금성일렉트론주식회사 | 반도체 펙케지 |
US5406124A (en) * | 1992-12-04 | 1995-04-11 | Mitsui Toatsu Chemicals, Inc. | Insulating adhesive tape, and lead frame and semiconductor device employing the tape |
KR0152901B1 (ko) * | 1993-06-23 | 1998-10-01 | 문정환 | 플라스틱 반도체 패키지 및 그 제조방법 |
-
1995
- 1995-12-29 KR KR1019950067335A patent/KR0179803B1/ko not_active IP Right Cessation
-
1996
- 1996-08-23 CN CN96109458A patent/CN1065662C/zh not_active Expired - Fee Related
- 1996-08-23 US US08/701,949 patent/US5770888A/en not_active Expired - Lifetime
- 1996-08-23 TW TW085110298A patent/TW344887B/zh not_active IP Right Cessation
- 1996-12-25 JP JP34529096A patent/JP2992814B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5770888A (en) | 1998-06-23 |
KR970053679A (ko) | 1997-07-31 |
CN1153997A (zh) | 1997-07-09 |
KR0179803B1 (ko) | 1999-03-20 |
CN1065662C (zh) | 2001-05-09 |
TW344887B (en) | 1998-11-11 |
JPH09326452A (ja) | 1997-12-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2992814B2 (ja) | 半導体パッケージ | |
US6906424B2 (en) | Semiconductor package and method producing same | |
US6559525B2 (en) | Semiconductor package having heat sink at the outer surface | |
US6177718B1 (en) | Resin-sealed semiconductor device | |
US6303997B1 (en) | Thin, stackable semiconductor packages | |
US5800958A (en) | Electrically enhanced power quad flat pack arrangement | |
US6563217B2 (en) | Module assembly for stacked BGA packages | |
JP2934357B2 (ja) | 半導体装置 | |
US5639694A (en) | Method for making single layer leadframe having groundplane capability | |
JP2000133767A (ja) | 積層化半導体パッケ―ジ及びその製造方法 | |
JP2008545278A (ja) | 非対称なリードフレームコネクションを有するダイパッケージ | |
US7508060B2 (en) | Multi-chip semiconductor connector assemblies | |
US20130200507A1 (en) | Two-sided die in a four-sided leadframe based package | |
KR100649869B1 (ko) | 반도체 패키지 | |
JPH10284873A (ja) | 半導体集積回路装置およびicカードならびにその製造に用いるリードフレーム | |
JPH0661408A (ja) | 表面実装型半導体装置 | |
JP2524482B2 (ja) | Qfp構造半導体装置 | |
JP3454192B2 (ja) | リードフレームとそれを用いた樹脂封止型半導体装置およびその製造方法 | |
JP3125891B2 (ja) | 半導体装置 | |
JP2000183275A (ja) | 半導体装置 | |
JP2690248B2 (ja) | 表面実装型半導体装置 | |
JPH10321670A (ja) | 半導体装置 | |
JP3670636B2 (ja) | 電子部品を実装した電子装置 | |
JP3250992B2 (ja) | 積層チップパッケージ | |
JPH05211274A (ja) | リードフレーム及び半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071022 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081022 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091022 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091022 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101022 Year of fee payment: 11 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111022 Year of fee payment: 12 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111022 Year of fee payment: 12 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121022 Year of fee payment: 13 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121022 Year of fee payment: 13 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131022 Year of fee payment: 14 |
|
LAPS | Cancellation because of no payment of annual fees |