KR920001690A - 수지봉지형 반도체장치 - Google Patents
수지봉지형 반도체장치 Download PDFInfo
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- KR920001690A KR920001690A KR1019910008853A KR910008853A KR920001690A KR 920001690 A KR920001690 A KR 920001690A KR 1019910008853 A KR1019910008853 A KR 1019910008853A KR 910008853 A KR910008853 A KR 910008853A KR 920001690 A KR920001690 A KR 920001690A
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- semiconductor device
- semiconductor
- wiring pattern
- lead frame
- semiconductor element
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Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 관한 반도체장치의 부분단면 사시도.
제2도는 제 1실시예에 관한 반도체장치의 단면도.
제3도는 제1실시예에 관한 반도체장치의 전극 부근의 확대단면도.
제4도는 제1실시예에 관한 반도체장치의 패케이지 측면 부근의 확대단면도.
제5도는 제1실시예에 관한 반도체장치의 제조방법을 도시한 설명도.
제6도, 제7도, 제8도, 제9도, 제10도, 제11도는 모두 제1실시예에 관한 반도체장치를 부분적으로 변경한 실시예 장치의 단면도.
제12도는 본 발명의 제2실시예에 관한 반도체장치의 부분확대 단면도.
제13도는 제2실시예에 관한 반도체장치를 부분적으로 변경한 실시예 장치의 부분확대 단면도.
제14도는 본 발명의 제3실시예에 관한 반도체장치의 부분확대 단면도.
제15도는 본 발명의 제4실시예에 관한 반도체장치의 부분확대 단면도.
제16도는 본 발명의 제5실시예에 관한 반도체장치의 부분확대 단면도.
제17도는 종래의 리이드 온 칩 구조의 내부를 도시한 사시도.
제18도는 64메가비트 DRAM의 최적 설계의 레이아우트 평면도.
제19도, 제20도는 모두 본딩 패드와 내부리이드의 전기적 접속의 설명도.
Claims (23)
- 반도체소자, 리이드의 집합체로 이루어지는 리이드 프레임 및 상기 반도체소자와 상기 리이드 프레임을 전기적으로 접속하는 수단을 마련하고, 상기 리이드 프레임의 일부, 상기 반도체소자 및 전기적 접속부분을 수지로 봉지하는 것에 의해 패케이지를 형성한 반도체장치에 있어서, 상기 반도체소자를 2매 사용하고, 상기 2매의 반도체소자의 회로 형성면이 대향하고 있고, 각각의 상기 반도체소자의 회로형성면상의 전극을 제외한 부분의 적어도 일부분에 절연필름을 마련하고, 각각의 상기 반도체소자의 상기 절연필름상에 금속의 배선패턴을 형성하고, 상기 배선패턴과 각각의 상기 반도체소자의 상기 전극을 와이어에 의해 전기적으로 접속하고, 2매의 상기 반도체소자 사이에 상기 리이드 프레임을 삽입하여 상기 배선패턴과 상기 리이드 프레임을 전기적으로 접속한 수지봉지형 반도체장치.
- 특허청구의 범위 제1항에 있어서, 상기 배선패턴과 리이드 프레임을 땜납에 의해 전기적으로 접속한 반도체장치.
- 특허청구의 범위 제2항에 있어서, 상기 땜납의 융점이 250℃ 이상인 반도체장치.
- 특허청구의 범위 제1항에 있어서, 상기 배선패턴과 상기 리이드 프레임을 도전성 수지에 의해 전기적으로 접속한 반도체장치.
- 특허청구의 범위 제1항에 있어서, 상기 반도체소자의 장방형이고, 상기 반도체소자의 전극이 상기 반도체소자의 2개의 중심선중 적어도 하나의 중심선의 근방에 배치되어 있는 반도체장치.
- 특허청구의 범위 제1항에 있어서, 상기 반도체소자의 메모리 LSI인 반도체장치.
- 특허청구의 범위 제1항에 있어서, 상기 배선패턴이 금속박인 반도체장치.
- 반도체소자, 리이드의 집합체로 이루어지는 리이드 프레임 및 상기 반도체소자와 상기 리이드 프레임을 전기적으로 접속하는 수단을 마련하고, 상기 라이드 프레임의 일부, 상기 반도체소자 및 전기적 접속부분을 봉지하는 것에 의해 패케이지를 형성한 반도체장치에 있어서, 상기 반도체소자를 2매 사용하고, 상기 2매의 반도체소자의 회로 형성면이 대향하고 있고, 각각의 상기 반도체소자의 회로형성면상의 전극을 제외한 부분의 적어도 일부분에 절연필름을 마련하고, 각각의 상기 반도체소자의 상기 절연필름상에 금속의 배선패턴을 형성하고, 상기 배선패턴과 각각의 상기 반도체소자의 상기 전극을 전기적으로 접속하고, 2매의 상기 반도체소자 사이에 상기 리이드 프레임을 삽입하여 상기 배선패턴과 상기 리이드 프레임을 전기적으로 접속하고, 상기 배선패턴과 상기 반도체소자를 전기적으로 접속하는 부분 및 상기 반도체소자의 회로형성면에서 필름으로 피복되어 있지 않은 부분의 적어도 일부를 제1의 봉지수지로 피복하고, 상기 리이드 프레임의 일부와 이들 구성부재를 제2의 수지로 봉지한 반도체장치.
- 특허청구의 범위 제8항에 있어서, 상기 반도체소자의 전극과 상기 배선패턴을 와이어에 의해 전기적으로 접속한 반도체장치.
- 특허청구의 범위 제8항에 있어서, 상기 배선패턴의 금속의 일부분을 상기 절연필름에서 돌출시키고, 이 부분의 금속과 상기 반도체소자의 전극을 열압착에 의해 전기적으로 접속한 반도체장치.
- 특허청구의 범위 제8항에 있어서, 상기 배선패턴과 리이드 프레임을 땜납에 의해 전기적으로 접속한 반도체장치.
- 특허청구의 범위 제11항에 있어서, 상기 땜납의 융점이 250℃ 이상인 반도체장치.
- 특허청구의 범위 제8항에 있어서, 상기 배선패턴과 상기 리이드 프레임을 도전성 수지에 의해 전기적으로 접속한 반도체장치.
- 특허청구의 범위 제8항에 있어서, 상기 반도체소자가 장방형이고, 상기 반도체소자의 전극이 상기 반도체소자의 2개의 중심선중 적어도 하나의 중심선의 근방에 배치되어 있는 반도체장치.
- 특허청구의 범위 제8항에 있어서, 상기 반도체소자가 메모리 LSI인 반도체장치.
- 특허청구의 범위 제8항에 있어서, 상기 배선패턴이 금속박인 반도체장치.
- 반도체소자, 리이드의 집합체로 이루어지는 리이드 프레임 및 상기 반도체소자와 상기 리이드 프레임을 전기적으로 접속하는 수단을 마련하고, 상기 리이드 프레임의 일부, 상기 반도체소자 및 전기적 접속부분을 수지로 봉지하는 것에 의해 패케이지를 형성한 반도체장치에 있어서, 상기 반도체소자를 2매 사용하고, 상기 2매의 반도체소자의 회로 형성면이 대향하고 있고, 각각의 상기 반도체소자의 회로형성면상의 전극을 제외한 부분의 적어도 일부분에 절연필름을 마련하고, 각각의 상기 반도체소자의 상기 절연필름상에 금속의 배선패턴을 형성하고, 상기 배선패턴의 금속의 일부분을 상기 절연필름에서 돌출시키고 이 부분의 금속과 상기 반도체소자의 전극을 열압착에 의해 전기적으로 접속하고, 2매의 상기 반도체소자 사이에 상기 리이드 프레임을 삽입하여 상기 배선패턴과 상기 리이드 프레임을 전기적으로 접속한 수지봉지형 반도체장치.
- 특허청구의 범위 제17항에 있어서, 상기 배선패턴과 리이드 프레임을 땜납에 의해 전기적으로 접속한 반도체장치.
- 특허청구의 범위 제18항에 있어서, 상기 땜납의 융점이 250℃ 이상인 반도체장치.
- 특허청구의 범위 제17항에 있어서, 상기 배선패턴과 상기 리이드 프레임을 도전성 수지에 의해 전기적으로 접속한 반도체장치.
- 특허청구의 범위 제17항에 있어서, 상기 반도체소자가 장방형이고, 상기 반도체소자의 전극이 상기 반도체소자의 2개의 중심선중 적어도 하나의 중심선의 근방에 배치되어 있는 반도체장치.
- 특허청구의 범위 제17항에 있어서, 상기 반도체소자가 메모리 LSI인 반도체장치.
- 특허청구의 범위 제17항에 있어서, 상기 배선패턴이 금속박인 반도체장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
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JP2155167A JP2816239B2 (ja) | 1990-06-15 | 1990-06-15 | 樹脂封止型半導体装置 |
JP2-155167 | 1990-06-15 |
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KR920001690A true KR920001690A (ko) | 1992-01-30 |
KR950005446B1 KR950005446B1 (ko) | 1995-05-24 |
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EP (1) | EP0461639B1 (ko) |
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Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2708191B2 (ja) * | 1988-09-20 | 1998-02-04 | 株式会社日立製作所 | 半導体装置 |
US5313367A (en) * | 1990-06-26 | 1994-05-17 | Seiko Epson Corporation | Semiconductor device having a multilayer interconnection structure |
US5086018A (en) * | 1991-05-02 | 1992-02-04 | International Business Machines Corporation | Method of making a planarized thin film covered wire bonded semiconductor package |
KR940003560B1 (ko) * | 1991-05-11 | 1994-04-23 | 금성일렉트론 주식회사 | 적층형 반도체 패키지 및 그 제조방법. |
DE4214102C2 (de) * | 1991-06-01 | 1997-01-23 | Gold Star Electronics | Multichip-Halbleiterbaustein |
JPH0661289A (ja) * | 1992-08-07 | 1994-03-04 | Mitsubishi Electric Corp | 半導体パッケージ及びこれを用いた半導体モジュール |
FI92734C (fi) * | 1993-02-11 | 1994-12-27 | Valmet Paper Machinery Inc | Menetelmä paperikoneen telan pinnoituksessa ja pinnoitettu paperikoneen tela |
JP2856642B2 (ja) * | 1993-07-16 | 1999-02-10 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP3150253B2 (ja) * | 1994-07-22 | 2001-03-26 | 三菱電機株式会社 | 半導体装置およびその製造方法並びに実装方法 |
KR0147259B1 (ko) * | 1994-10-27 | 1998-08-01 | 김광호 | 적층형 패키지 및 그 제조방법 |
GB2296992A (en) * | 1995-01-05 | 1996-07-17 | Int Rectifier Co Ltd | Electrode configurations in surface-mounted devices |
US5615475A (en) * | 1995-01-30 | 1997-04-01 | Staktek Corporation | Method of manufacturing an integrated package having a pair of die on a common lead frame |
US5689135A (en) * | 1995-12-19 | 1997-11-18 | Micron Technology, Inc. | Multi-chip device and method of fabrication employing leads over and under processes |
KR100204753B1 (ko) * | 1996-03-08 | 1999-06-15 | 윤종용 | 엘오씨 유형의 적층 칩 패키지 |
US5907184A (en) * | 1998-03-25 | 1999-05-25 | Micron Technology, Inc. | Integrated circuit package electrical enhancement |
US5763945A (en) * | 1996-09-13 | 1998-06-09 | Micron Technology, Inc. | Integrated circuit package electrical enhancement with improved lead frame design |
JP2908350B2 (ja) * | 1996-10-09 | 1999-06-21 | 九州日本電気株式会社 | 半導体装置 |
KR100226737B1 (ko) * | 1996-12-27 | 1999-10-15 | 구본준 | 반도체소자 적층형 반도체 패키지 |
US5780923A (en) | 1997-06-10 | 1998-07-14 | Micron Technology, Inc. | Modified bus bar with Kapton™ tape or insulative material on LOC packaged part |
US6580157B2 (en) * | 1997-06-10 | 2003-06-17 | Micron Technology, Inc. | Assembly and method for modified bus bar with Kapton™ tape or insulative material in LOC packaged part |
US6175149B1 (en) * | 1998-02-13 | 2001-01-16 | Micron Technology, Inc. | Mounting multiple semiconductor dies in a package |
US6297547B1 (en) * | 1998-02-13 | 2001-10-02 | Micron Technology Inc. | Mounting multiple semiconductor dies in a package |
JP2000100814A (ja) * | 1998-09-18 | 2000-04-07 | Hitachi Ltd | 半導体装置 |
KR100333388B1 (ko) * | 1999-06-29 | 2002-04-18 | 박종섭 | 칩 사이즈 스택 패키지 및 그의 제조 방법 |
JP3406270B2 (ja) * | 2000-02-17 | 2003-05-12 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
DE10023823A1 (de) * | 2000-05-15 | 2001-12-06 | Infineon Technologies Ag | Multichip-Gehäuse |
DE10114897A1 (de) * | 2001-03-26 | 2002-10-24 | Infineon Technologies Ag | Elektronisches Bauteil |
US6576992B1 (en) | 2001-10-26 | 2003-06-10 | Staktek Group L.P. | Chip scale stacking system and method |
DE10255289A1 (de) * | 2002-11-26 | 2004-06-17 | Infineon Technologies Ag | Elektronisches Bauteil mit gestapelten Halbleiterchips in paralleler Anordnung und Verfahren zu dessen Herstellung |
DE10259221B4 (de) * | 2002-12-17 | 2007-01-25 | Infineon Technologies Ag | Elektronisches Bauteil mit einem Stapel aus Halbleiterchips und Verfahren zur Herstellung desselben |
DE102006026023A1 (de) * | 2006-06-01 | 2007-12-06 | Infineon Technologies Ag | Halbleiterbauteil mit Halbleiterchipstapel und Kunststoffgehäuse sowie Verfahren zur Herstellung des Halbleiterbauteils |
DE112008003425B4 (de) * | 2007-12-20 | 2023-08-31 | Aisin Aw Co., Ltd. | Verfahren zum Herstellen eines Halbleiterbauelements |
JP5018909B2 (ja) * | 2009-06-30 | 2012-09-05 | 株式会社デンソー | 半導体装置 |
JP6598740B2 (ja) * | 2016-07-15 | 2019-10-30 | 三菱電機株式会社 | 半導体装置 |
JP2018049942A (ja) * | 2016-09-21 | 2018-03-29 | アイシン精機株式会社 | 変位センサ |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3893158A (en) * | 1972-03-15 | 1975-07-01 | Motorola Inc | Lead frame for the manufacture of electric devices having semiconductor chips placed in a face to face relation |
DE2409312C3 (de) * | 1974-02-27 | 1981-01-08 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Halbleiteranordnung mit einer auf der Halbleiteroberfläche angeordneten Metallschicht und Verfahren zu ihrer Herstellung |
JPS5588356A (en) * | 1978-12-27 | 1980-07-04 | Hitachi Ltd | Semiconductor device |
WO1982003727A1 (en) * | 1981-04-21 | 1982-10-28 | Seiichiro Aigoo | Method of making a semiconductor device having a projecting,plated electrode |
JPS59229850A (ja) * | 1983-05-16 | 1984-12-24 | Rohm Co Ltd | 半導体装置 |
JPS6224650A (ja) * | 1985-07-24 | 1987-02-02 | Hitachi Vlsi Eng Corp | 半導体装置 |
JPS6477135A (en) * | 1987-09-18 | 1989-03-23 | Hitachi Maxell | Semiconductor device |
JP2702219B2 (ja) * | 1989-03-20 | 1998-01-21 | 株式会社日立製作所 | 半導体装置及びその製造方法 |
US4862322A (en) * | 1988-05-02 | 1989-08-29 | Bickford Harry R | Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween |
KR0158868B1 (ko) * | 1988-09-20 | 1998-12-01 | 미다 가쓰시게 | 반도체장치 |
US4965654A (en) * | 1989-10-30 | 1990-10-23 | International Business Machines Corporation | Semiconductor package with ground plane |
SG52794A1 (en) * | 1990-04-26 | 1998-09-28 | Hitachi Ltd | Semiconductor device and method for manufacturing same |
-
1990
- 1990-06-15 JP JP2155167A patent/JP2816239B2/ja not_active Expired - Fee Related
-
1991
- 1991-05-30 KR KR1019910008853A patent/KR950005446B1/ko not_active IP Right Cessation
- 1991-06-11 US US07/713,100 patent/US5539250A/en not_active Expired - Lifetime
- 1991-06-12 EP EP91109654A patent/EP0461639B1/en not_active Expired - Lifetime
- 1991-06-12 DE DE69127587T patent/DE69127587T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0461639A2 (en) | 1991-12-18 |
EP0461639A3 (en) | 1993-09-22 |
US5539250A (en) | 1996-07-23 |
DE69127587T2 (de) | 1998-04-23 |
JP2816239B2 (ja) | 1998-10-27 |
JPH0448767A (ja) | 1992-02-18 |
KR950005446B1 (ko) | 1995-05-24 |
EP0461639B1 (en) | 1997-09-10 |
DE69127587D1 (de) | 1997-10-16 |
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