JP2708191B2 - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP2708191B2
JP2708191B2 JP63236156A JP23615688A JP2708191B2 JP 2708191 B2 JP2708191 B2 JP 2708191B2 JP 63236156 A JP63236156 A JP 63236156A JP 23615688 A JP23615688 A JP 23615688A JP 2708191 B2 JP2708191 B2 JP 2708191B2
Authority
JP
Japan
Prior art keywords
chip
lead
semiconductor device
semiconductor chip
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63236156A
Other languages
English (en)
Other versions
JPH0283962A (ja
Inventor
隆 山崎
一義 大嶋
哲郎 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP63236156A priority Critical patent/JP2708191B2/ja
Priority to KR1019890013440A priority patent/KR0158868B1/ko
Priority to US07/409,332 priority patent/US5068712A/en
Publication of JPH0283962A publication Critical patent/JPH0283962A/ja
Priority to US07/990,272 priority patent/US5358904A/en
Priority to US08/293,555 priority patent/US5530286A/en
Priority to KR1019940023054A priority patent/KR0167389B1/ko
Priority to KR1019940023053A priority patent/KR0167388B1/ko
Priority to US08/464,131 priority patent/US5612569A/en
Priority to US08/646,031 priority patent/US5793099A/en
Priority to US08/790,985 priority patent/US5821606A/en
Application granted granted Critical
Publication of JP2708191B2 publication Critical patent/JP2708191B2/ja
Priority to US09/035,104 priority patent/US6018191A/en
Priority to US09/046,542 priority patent/US5863817A/en
Priority to US09/052,981 priority patent/US5914530A/en
Priority to US09/060,368 priority patent/US6069029A/en
Priority to US09/066,877 priority patent/US6072231A/en
Priority to KR1019980018646A priority patent/KR0161354B1/ko
Priority to KR1019980018645A priority patent/KR0161355B1/ko
Priority to KR1019980018647A priority patent/KR0161353B1/ko
Priority to KR1019980023314A priority patent/KR0167437B1/ko
Priority to KR1019980023317A priority patent/KR0167440B1/ko
Priority to KR1019980023315A priority patent/KR0167438B1/ko
Priority to KR1019980023316A priority patent/KR0167439B1/ko
Priority to US09/166,121 priority patent/US6100115A/en
Priority to US09/166,532 priority patent/US5981315A/en
Priority to US09/167,736 priority patent/US6100580A/en
Priority to US09/168,097 priority patent/US6124629A/en
Priority to US09/288,673 priority patent/US6081023A/en
Priority to US09/290,582 priority patent/US6130114A/en
Priority to US09/481,398 priority patent/US6204552B1/en
Priority to US09/482,648 priority patent/US6326681B1/en
Priority to US09/558,105 priority patent/US6531760B1/en
Priority to US09/771,617 priority patent/US6303982B2/en
Priority to US10/322,672 priority patent/US6720208B2/en
Priority to US10/774,405 priority patent/US6919622B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関し、特にパッゲージに収容
された半導体チップとリードとの間に形成される寄生容
量の低減に適用して有効な技術に関するものである。
〔従来の技術〕
４メガビット〔Mbit〕ダイナミックRAM（Dynatic Ran
dom Access Memory）や、１メガビットスタティックRAM
（SRAM）などの大規模集積回路を備えた近年の半導体装
置においては、半導体チップ（以下、チップという）の
面積が増大しているにもかかわらず、これを収容するパ
ッケージの寸法が規格化され、その面積を大きくするこ
とができないという制約がある。
そのため、外部端子であるリードのパッケージに埋設
された部分（インナリード）の長さが短くなり、リード
がパッケージから抜け易くなったり、リードを折り曲げ
る際にパッケージにクラックが発生したりする問題が生
じている。
特に、表面実装方式のパッケージでは、パッケージ中
に含まれる水分が半田リフロー時の熱で膨張することに
よって、パッケージにクラックが発生する、いわゆるリ
フロークラックの問題が深刻になっている。
その解決手段として、特開昭60−167454や特開昭61−
218139号に開示されているように、チップを搭載するタ
ブ（ダイパッド）をなくして、リード上に接着された絶
縁フィルムの上にチップを搭載し（Chip On Lead）、チ
ップのボンディングパッドとリードの先端部とをワイヤ
で結線する、いわゆるタブレスリードフレーム方式のパ
ッケージ構造が提案されている。
また、特開昭59−92556号や特開昭61−236130号に開
示されているように、リードを接着剤でチップの上面に
接着し（Lead On Chip）、チップのボンディングパッド
とリードの先端部とをワイヤで結線するパッケージ構造
も提案されている。
チップの上面または下面にリードを配設する上記パッ
ケージ構造によれば、パッケージ内部のリード長を長く
することができるため、パッケージの耐熱性や耐湿性が
向上する。また、タブをなくすことによって、樹脂とリ
ードとの密着性が向上するため、リフロークラック耐性
が向上する。その結果、大形化したチップでも従来寸法
のパッケージに収容することが可能となる。さらに、こ
のパッケージ構造は、ボンディングワイヤ長を短くする
ことができるため、配線遅延を低減することができる、
という利点も備えている。
〔発明が解決しようとする課題〕
しかしながら、本発明者の検討によれば、チップの上
面または下面にリードを配設する上記従来のパッケージ
構造は、チップとリードとの間に形成される寄生容量が
増大してしまう、という問題についての配慮がなされて
いない。そして、チップとリードとの間の寄生容量が増
大すると、入出力ピン容量が増大し、配線遅延が増大す
ることから、半導体装置の高速動作が妨げられることに
なる。
本発明は、上記した問題点に着目してなされたもので
あり、その目的は、チップの回路形成面に対向させてリ
ードを配設するパッケージ構造を備えた半導体装置にお
いて、チップとリードとの間に形成される寄生容量を低
減することができる技術を提供することにある。
本発明の前記ならびにその他の目的と新規な特徴は、
本明細書の記述および添付図面から明らかになるであろ
う。
〔課題を解決するための手段〕
本願において開示される発明のうち、代表的なものの
概要を簡単に説明すれば、次のとおりである。
すなわち、本発明の半導体装置は、半導体チップと、
この半導体チップの回路形成面に対向するように配置さ
れ、かつ前記回路形成面の電極に電気的に接続される複
数のインナーリードと、前記インナーリードと前記半導
体チップ間に存在する絶縁物とから成り、前記インナー
リードの前記回路形成面に対向する部分は第一部分と第
二部分とを有し、前記第一部分と前記半導体チップの前
記回路形成面との距離よりも前記第二部分と前記半導体
チップの前記回路形成面との距離の方が大きくなるよう
に構成され、前記インナーリードと前記電極とを前記第
一部分で電気的に接続したことを特徴とする。
〔作用〕
チップとその回路形成面に対向するように配置された
インナーリードとの間に形成される寄生容量の大きさ
は、チップとインナーリードとの距離に逆比例し、それ
らの対向面積に比例する。従って、インナーリードとチ
ップとの間に絶縁物が配置され、インナーリードの回路
形成面に対向する部分は第一部分と第二部分とを有し、
前記第一部分と前記半導体チップの前記回路形成面との
距離よりも前記第二部分と前記半導体チップの前記回路
形成面との距離の方が大きくなるように構成されている
本発明によれば、上記寄生容量を低減することができ
る。
〔参考例〕
本発明の半導体装置を実施例に基づいて説明する前
に、その参考例について説明する。
第１図は、本発明の参考例である半導体装置を示す第
３図のＩ−Ｉ線断面図、第２図は、同じく第３図のII−
II線部分破断断面図、第３図は、この半導体装置の略平
面図、第４図は、この半導体装置の回路ブロックを示す
半導体チップの略平面図である。
参考例の半導体装置は樹脂封止形半導体装置であり、
そのパッケージ構造は、タブレスリードフレーム方式を
用いたDIP（Dual in−line package）である。
パッケージ本体１は、例えばエポキシ樹脂にシリカ
（SiO2）などのフィラーを充填してその熱膨張係数をシ
リコンの熱膨張係数に近づけた樹脂からなり、曲げ強度
やリフロー・クラックに強い構造となっている。
パッケージ本体１の長手方向の両側面には、入出力ピ
ンおよび電源ピンを構成する複数本のリード２が外方に
延在するとともに、下方に折り曲げられている。これら
のリード２は、例えばCuからなり、その表面には、例え
ばSn−Ni合金などのメッキが施されている。
パッケージ本体１の内部に埋設されたリード２の上面
には、例えばポリイミド樹脂からなる矩形の絶縁フィル
ム3aが接着剤４を介して接合されている。この接着剤４
は、例えばポリイミド樹脂系の接着剤である。
リード２は、第３図に示すように、絶縁フィルム3aの
下面において、水平方向にほぼ直角に折り曲げられ、例
えばAgメッキが施されたリード２の先端部が、絶縁フィ
ルム3aの短辺から外方に突出されている。
リード２は、さらに、第１図、第２図に示すように、
絶縁フィルム3aの下面において、その中途部分が下方に
折り曲げられ、これによって生じたリード２と絶縁フィ
ルム3aとの隙間には、モールド時におけるリード２の変
形を防止するため、この隙間とほぼ等しい膜厚の第２の
絶縁フィルム3bが接着されている。第２図に示されるよ
うに、リード２のうち外方に突出した部分がアウターリ
ード2aであり、パッケージ本体１の内部に埋設された部
分がインナーリード2bであり、インナーリード2bは、図
示するように、第一部分2b1と、第２部分2b2とを有して
いる。そして、第１部分2b1とチップ５の回路形成面と
の距離よりも第２部分2b2とチップ５の回路形成面との
距離の方が大きく成るように構成されている。なお、こ
の絶縁フィルム3bは、例えば前記絶縁フィルム3aと同じ
ポリイミド樹脂からなる。
絶縁フィルム3aの上面には、シリコン単結晶からなる
矩形の半導体チップ５が接着剤６を介して接合されてい
る。この接着剤６は、例えばシリコーン樹脂系の接着剤
である。チップ５は、その面積が絶縁フィルム3aの面積
よりも僅かに小さくなっている。また、チップ５の上面
側が集積回路形成面となっており、その表面には、平坦
化などを目的として、例えばポリイミド樹脂からなる保
護膜７が被着されている。このチップ５の集積回路形成
面には、例えば４メガビットMOS・DRAMが形成されてい
る。
第４図に示すように、チップ５の中央部には、この４
メガビットMOS・DRAMのメモリセルアレイＭが配置さ
れ、その両側に、周辺回路Ｐが配置されている。チップ
５の短辺側周縁部と周辺回路Ｐとの間には、複数のボン
ディングパッド８が配置され、各ボンディングパッド８
とリード２とは、図示するようにインナーリード2bの第
一部分2b1で、Au、CuあるいはAlなどからなるワイヤ９
を介して電気的に接続されている。
ところで、樹脂封止形半導体装置においては、通常チ
ップ５とリード２との間に寄生容量が形成されている。
この寄生容量は、チップ５とリード２との距離に逆比例
し、それらの対向面積に比例して増大するため、パッケ
ージ本体１の内部に埋設されたリード２の大部分がチッ
プ５の下面に位置しているようなパッケージ構造におい
ては、チップ５とリード２との対向面積が大きくなるた
め、大きな寄生容量が形成されてしまう。
しかしながら、チップ５の下面に位置しているリード
２の中途部分が下方に折り曲げられているため、チップ
５とリード２との距離がその分だけ大きくなっている。
従って、リード２の中途部分が下方に折り曲げられてい
ない場合に比べ、チップ５とリード２との間に形成され
る寄生容量を低減することができる。
その結果、入出力ピンを構成するリード２の容量も小
さくなり、チップ５に形成された４メガビットMOS・DRA
Mへのアクセスが高速化される。
なお、リード２と絶縁フィルム3aとの隙間に、絶縁フ
ィルム3aと同じ材質の第２の絶縁フィルム3bを接着した
が、例えば絶縁フィルム3a,3bを一体成形してもよく、
また、絶縁フィルム3aと絶縁フィルム3bとを異なる材料
で構成してもよい。
〔実施例〕
第５図は、本発明の一実施例である半導体装置を示す
第６図のＶ−Ｖ線断面図、第６図は、この半導体装置の
略平面図、第７図は、この半導体装置の回路ブロックを
示す半導体装置チップの略平面図である。
本実施例のパッケージ構造は、前記参考例と同じく、
タブレスリードフレーム方式のDIPであるが、前記参考
例が、チップ５の下面にリード２を配設する、いわゆる
チップ・オン・リード（Chip On Lead）方式を用いてい
るのに対し、本実施例の半導体装置は、リード２の下面
にチップ５を配設する、いわゆるリード・オン・チップ
（Lead On Chip）方式を用いている。
すなわち、前記参考例と同様の樹脂からなるパッケー
ジ本体１に封止されたチップ５は、その上面側が集積回
路形成面となっており、この集積回路形成面には、例え
ば４メガビットMOS・DRAMが形成されている。
第７図に示すように、このチップ５の中央部には、チ
ップの長辺方向に延びる周辺回路Ｐが配置され、その両
側にメモリセルアレイＭが配置されている。チップ５の
中央部に周辺回路Ｐを配置したことにより、チップ５の
短辺側に周辺回路Ｐが配置されている前記参考例の４メ
ガビットMOS・DRAMに比べて、チップ５の長辺方向に延
びる配線長を短くすることができるので、配線遅延がよ
り低減される。
チップ５の中央部において、周辺回路Ｐとメモリアレ
イＭとの間には、ボンディングパッド８が集中的に配置
されている。
第５図に示すように、チップ５の上面には、例えばポ
リイミド樹脂からなる矩形の絶縁フィルム3aが接着剤６
を介して接合されている。この絶縁フィルム3aは、その
面積チップ５よりも僅かに大きく、かつ、中央部には、
開孔10が形成されている。
絶縁フィルム3aの上面には、複数のリード２が接着剤
４を介して接合されている。このリード２は、第６図に
示すように、絶縁フィルム3aの上面で水平方向に折り曲
げられ、その先端部が電極つまりボンディングパッド８
の近傍に配置されている。そして、リード２とボンディ
ングパッド８とが、ワイヤ９を介して電気的に接続され
ている。
リード２は、第５図に示すように、絶縁フィルム3aの
上面において、その中途部分が上方に折り曲げられ、こ
れによって生じたリード２と絶縁フィルム3aとの隙間に
は、この隙間とほぼ等しい膜厚の絶縁フィルム3bが接着
されている。
このように、本実施例においては、チップ５の上面に
位置しているリード２の中途部分が上方に折り曲げられ
て、インナーリード2bは第一部分2b1と第二部分2b2とを
有し、チップ５の回路形成面とインナーリード2bとの距
離が、第一部分2b1よりも第二部分2b2の方が大きくなっ
ているため、リード２の中途部分が上方に折り曲げられ
ていない従来技術に比べ、チップ５とリード２との間に
形成される寄生容量を低減することができる。
従って、入出力ピンを構成するリード２の容量も小さ
くなり、チップ５に形成された４メガビットMOS・DRAM
へのアクセスを高速化することができる。
以上、本発明者によってなされた発明を実施例に基づ
き具体的に説明したが、本発明は前記実施例に限定され
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であることはいうまでもない。
例えば第８図に示すように、チップ５に形成された所
定の集積回路とリード２とが、半田バンプ11を介して電
気的に接続されているようなパッケージ構造に適用する
こともできる。すなわち、図示したように、パッケージ
本体１の内部に埋設されたリード２の大部分が、チップ
５の下面に沿って配設されている場合において、半田バ
ンプ11,11間を接続するリード２の中途部分を下方に折
り曲げることにより、このリード２とチップ５との間に
形成される寄生容量を低減することができる。
また、前記実施例のパッケージは、DIPであったが、
これに限定されるものではなく、例えばSOJ（Small Out
line J−lead Package）やPLCC（Plastic Leaded Chip
Carrier）などであってもよい。
さらに、タブレスリードフレーム方式を用いた半導体
装置に限定されるものではなく、例えばタブに搭載され
たチップの上面にリードを配設する方式の半導体装置に
も適用することができる。
以上の説明では、主として本発明者によってなされた
発明をその背景となった利用分野であるMOS・RAMに適用
した場合について説明したが、本発明は、それに限定さ
れるものではなく、例えばEPROMなどの他の半導体メモ
リや、マイクロコンピュータなどの論理LSIにも適用す
ることができる。
〔発明の効果〕
本願において開示される発明のうち、代表的なものに
よって得られる効果を簡単に説明すれば、下記のとおり
である。
すなわち、インナーリードとチップ間に絶縁物が配置
され、インナーリードのうちチップと対向する部分は第
一部分と第２部分とを有し、第１部分とチップの回路形
成面との距離よりも第二部分とチップの回路形成面との
距離の方が大きくなるように構成されているので、チッ
プとリードとの間に形成される寄生容量を低減すること
ができる。
さらに、チップの中央部に周辺回路を配置することに
より、チップの長辺方向に延びる配線長を短くすること
ができるので、配線遅延を低減することができる。
【図面の簡単な説明】
第１図は本発明の参考例である半導体装置を示す第３図
のＩ−Ｉ線断面図、 第２図は同じく第３図のII−II線部分破断断面図、 第３図はこの半導体装置の略平面図、 第４図はこの半導体装置の回路ブロックを示す半導体チ
ップの略平面図、 第５図は本発明の一実施例である半導体装置を示す第６
図のＶ−Ｖ線断面図、 第６図は第５図に示した半導体装置の概略平面図、 第７図は第５図に示した半導体装置の回路ブロックを示
す半導体チップの略平面図、 第８図は本発明の他の実施例である半導体装置を示す要
部破断断面図である。 １……パッケージ本体、２……リード、2a……アウター
リード、2b……インナーリード、2b1……第一部分、2b2
……第二部分、3a,3b……絶縁フィルム、4,6……接着
剤、５……半導体チップ、７……保護膜、８……ボンデ
ィングパッド、９……ワイヤ、10……開孔、11……半田
バンプ、Ｍ……メモリセルアレイ、Ｐ……周辺回路。
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭63−152161（ＪＰ，Ａ) 特開 昭48−56065（ＪＰ，Ａ) 特開 昭63−293963（ＪＰ，Ａ)

Claims (8)

    (57)【特許請求の範囲】
  1. 【請求項１】半導体チップと、この半導体チップの回路
    形成面に対向するように配置され、かつ前記回路形成面
    の電極に電気的に接続される複数のインナーリードと、
    前記インナーリードと前記半導体チップ間に存在する絶
    縁物とから成り、前記インナーリードの前記回路形成面
    に対向する部分は第一部分と第二部分とを有し、前記第
    一部分と前記半導体チップの前記回路形成面との距離よ
    りも前記第二部分と前記半導体チップの前記回路形成面
    との距離の方が大きくなるように構成され、前記インナ
    ーリードと前記電極とを前記第一部分で電気的に接続し
    たことを特徴とする半導体装置。
  2. 【請求項２】前記電極と前記第一部分とをボンディング
    ワイヤにより電気的に接続したことを特徴とする請求項
    １記載の半導体装置。
  3. 【請求項３】前記電極と前記第一部分とを半田バンプを
    介して電気的に接続したことを特徴とする請求項１記載
    の半導体装置。
  4. 【請求項４】前記絶縁物は樹脂から成ることを特徴とす
    る請求項１記載の半導体装置。
  5. 【請求項５】前記半導体チップの中央部に前記ボンディ
    ングパッドが配置されていることを特徴とする請求項１
    記載の半導体装置。
  6. 【請求項６】前記半導体チップは長方形であることを特
    徴とする請求項１記載の半導体装置。
  7. 【請求項７】前記半導体チップの長辺方向に沿って前記
    ボンディングパッドが形成されていることを特徴とする
    請求項６記載の半導体装置。
  8. 【請求項８】前記半導体チップの長辺方向に沿って周辺
    回路が形成されていることを特徴とする請求項６記載の
    半導体装置。
JP63236156A 1988-03-20 1988-09-20 半導体装置 Expired - Lifetime JP2708191B2 (ja)

Priority Applications (34)

Application Number Priority Date Filing Date Title
JP63236156A JP2708191B2 (ja) 1988-09-20 1988-09-20 半導体装置
KR1019890013440A KR0158868B1 (ko) 1988-09-20 1989-09-19 반도체장치
US07/409,332 US5068712A (en) 1988-09-20 1989-09-19 Semiconductor device
US07/990,272 US5358904A (en) 1988-09-20 1992-12-14 Semiconductor device
US08/293,555 US5530286A (en) 1988-03-20 1994-08-22 Semiconductor device
KR1019940023054A KR0167389B1 (ko) 1988-09-20 1994-09-13 반도체장치
KR1019940023053A KR0167388B1 (ko) 1988-09-20 1994-09-13 반도체장치
US08/464,131 US5612569A (en) 1988-03-20 1995-06-05 Semiconductor device
US08/646,031 US5793099A (en) 1988-09-20 1996-05-07 Semiconductor device
US08/790,985 US5821606A (en) 1988-09-20 1997-01-29 Semiconductor device
US09/035,104 US6018191A (en) 1988-09-20 1998-03-05 Semiconductor device
US09/046,542 US5863817A (en) 1988-09-20 1998-03-24 Semiconductor device
US09/052,981 US5914530A (en) 1988-09-20 1998-04-01 Semiconductor device
US09/060,368 US6069029A (en) 1988-09-20 1998-04-15 Semiconductor device chip on lead and lead on chip manufacturing
US09/066,877 US6072231A (en) 1988-03-20 1998-04-28 Semiconductor device
KR1019980018646A KR0161354B1 (ko) 1988-09-20 1998-05-23 반도체장치
KR1019980018645A KR0161355B1 (ko) 1988-09-20 1998-05-23 반도체장치의 제조방법
KR1019980018647A KR0161353B1 (ko) 1988-09-20 1998-05-23 수지봉지패키지의 제조방법
KR1019980023314A KR0167437B1 (en) 1988-09-20 1998-06-22 Method for manufacturing semicondutor device
KR1019980023316A KR0167439B1 (ko) 1988-09-20 1998-06-22 반도체장치
KR1019980023317A KR0167440B1 (ko) 1988-09-20 1998-06-22 반도체장치
KR1019980023315A KR0167438B1 (ko) 1988-09-20 1998-06-22 반도체장치의 제조방법
US09/166,121 US6100115A (en) 1988-09-20 1998-10-05 Semiconductor device
US09/166,532 US5981315A (en) 1988-09-20 1998-10-06 Semiconductor device
US09/167,736 US6100580A (en) 1988-09-20 1998-10-07 Semiconductor device having all outer leads extending from one side of a resin member
US09/168,097 US6124629A (en) 1988-09-20 1998-10-08 Semiconductor device including a resin sealing member which exposes the rear surface of the sealed semiconductor chip
US09/288,673 US6081023A (en) 1988-03-20 1999-04-09 Semiconductor device
US09/290,582 US6130114A (en) 1988-03-20 1999-04-13 Semiconductor device
US09/481,398 US6204552B1 (en) 1988-03-20 2000-01-12 Semiconductor device
US09/482,648 US6326681B1 (en) 1988-09-20 2000-01-13 Semiconductor device
US09/558,105 US6531760B1 (en) 1988-09-20 2000-04-25 Semiconductor device
US09/771,617 US6303982B2 (en) 1988-09-20 2001-01-30 Semiconductor device
US10/322,672 US6720208B2 (en) 1988-09-20 2002-12-19 Semiconductor device
US10/774,405 US6919622B2 (en) 1988-09-20 2004-02-10 Semiconductor device

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US5793099A (en) 1998-08-11
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US5914530A (en) 1999-06-22
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US6531760B1 (en) 2003-03-11
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US6069029A (en) 2000-05-30
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US6919622B2 (en) 2005-07-19
US6326681B1 (en) 2001-12-04

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