KR880014671A - 수지로 충진된 반도체 장치 - Google Patents

수지로 충진된 반도체 장치 Download PDF

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Publication number
KR880014671A
KR880014671A KR1019880006089A KR880006089A KR880014671A KR 880014671 A KR880014671 A KR 880014671A KR 1019880006089 A KR1019880006089 A KR 1019880006089A KR 880006089 A KR880006089 A KR 880006089A KR 880014671 A KR880014671 A KR 880014671A
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South Korea
Prior art keywords
chip
lead
semiconductor
semiconductor device
resin
Prior art date
Application number
KR1019880006089A
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English (en)
Inventor
구니히로 쯔보사기
겐 무라가미
도시유기 사구다
마사미찌 이시하라
사도루 이도우
야스오 모리
Original Assignee
미다 가쓰시게
가부시기가이샤 히다찌세이사꾸쇼
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Priority claimed from JP62128248A external-priority patent/JP2543525B2/ja
Priority claimed from JP20691387A external-priority patent/JPS6450451A/ja
Priority claimed from JP62234188A external-priority patent/JPS6477152A/ja
Application filed by 미다 가쓰시게, 가부시기가이샤 히다찌세이사꾸쇼 filed Critical 미다 가쓰시게
Publication of KR880014671A publication Critical patent/KR880014671A/ko

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Abstract

내용 없음

Description

수지로 충진된 반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도a 는 본 발명의 제1실시예를 도시하는 주요부 단면도, 제1도b는 본 발명의 제1실시예중 다른 예를 도시하는 주요부 단면도, 제1도 c는 본 발명의 상기 제1실시예를 도시하는 반도체 장치의 구성 단면도.

Claims (20)

  1. 여러개의 리이드로 되는 펠릿 탑재부에 반도체 펠릿을 다이본딩해서 되는 수지로 충진된 반도체 장치에 있어서, 상기 리이드의 적어도 표면 및 양측면을 피복해서 형성된 수지 성형부에 반도체 펠릿을 다이본딩해서 되는 것을 특징으로 하는 수지로 충진된 반도체 장치.
  2. 특허청구의 범위 제1항에 있어서, 수지 성형부가 리이드의 전면을 피복해서 형성된 수지 층인 것을 특징으로 하는 수지로 충진된 반도체 장치.
  3. 리이드의 일부를 칩 밑에 연장시키고, 그 위에 절연막을 거쳐서 상기 칩을 지지하는 반도체 장치로써, 상기 리이드의 칩 밑의 부분이 상기 절연막 중에 매입되어 있는 것을 특징으로 하는 반도체 장치.
  4. 특허청구의 범위 제3항에 있어서, 상기 절연막은 폴리이미드로 되어 있는 것을 특징으로 하는 반도체 장치.
  5. 특허청구의 범위 제3항에 있어서, 상기 칩은 열가소성 수지 또는 Ag페이스트에 의해서 상기 절연막상에 접착되어 있는 것을 특징으로 하는 반도체 장치.
  6. 특허청구의 범위 제3항에 있어서, 상기 칩은 상기 폴리이미드로 되는 절연막을 열처리에, 의해서 경화하기 이전에 그 절연막에 접착되어 그것을 열경화해서 고착시킨 것을 특징으로 하는 반도체 장치.
  7. 특허청구의 범위 제3항에 있어서, 상기 반도체 장치는 상기 절연막이 하나하나의 리이드 마다 둘러싸도록 마련되어 있고, 또 절연막과 칩 사이에 금속으로 되는 방열판을 개재시키는 것에 의해서 방열효과를 높이는 것을 특징으로 하는 반도체 장치.
  8. 탭없는 리이드 프레임의 내부 리이드의 반도체 칩 탑재부에 반도체 칩을 탑재하고 내부 리이드와 반도체 칩을 본딩 와이어에 의해 전기적으로 접속하여 수지 성형 재료로 충진하는 반도체 장치용 리이드 프레임으로써, 상기 각각 내부 리이드의 반도체 탑재부의 일부 또는 전부를 절연 처리한 것을 특징으로 하는 리이드 프레임.
  9. 특허청구 범위 제8항에 있어서, 상기 리이드 반도체 칩 탑재부의 일부 또는 전부의 절연 처리는 열 경화성 폴리이미드계 수지 등의 액체 상태의 절연성 물질을 도포해서 열처리를 행하는 처리인 것을 특징으로 하는 리이드 프레임.
  10. 특허청구의 범위 제8항에 있어서, 상기 내부 리이드의 반도체 칩 탑재부의 일부 또는 전부의 절연 처리는 열경화성 폴리이미드계 수지 등의 테이프형 절연성 물질로 내부 리이드의 반도체 칩 탑재부를 덮고 열처리해서 피복하는 처리인 것을 특징으로 하는 리이드 프레임.
  11. 특허청구의 범위 제8항 내지 제10항에 있어서, 상기 반도체 칩은 내부 리이드의 반도체 칩 탑재부에 직접 접착제로 접착하는 것을 특징으로 하는 리이드 프레임.
  12. 특허청구의 범위 제11항에 있어서, 상기 접착제는 내부 리이드측에서 차례로 열가소성의 접착제, 열경화성 폴리이미드계 수지 접착제 및 펠렛 붙임용 열경화성 접착제를 적층한 다층 접착제인 것을 특징으로 하는 반도체 장치.
  13. 특허청구의 범위 제8항에 있어서, 상기 절연 처리된 내부 리이드의 반도체 칩 탑재부 상에만 절연성막을 접착하고 그 위에 접착제로 반도체 칩을 접착한 것을 특징으로 하는 리이드 프레임.
  14. 다수의 내부 리이드상에 직접 회로 반도체 칩을 그 이면에 있어서 고착하고, 상기 내부 리이드와 상기 칩의 주표면상의 다수의 본딩 패드사이를 다수의 본딩 와이어에 의해 전기적으로 접속한 후 상기 내부 리이드, 칩 및 본딩 와이어를 수지에 의해 성형한 반도체 집적회로 장치에 있어서, 상기 내부 리이드에 연결한 다수의 외부 리이드는 상기 수지 성형부 측면에서 돌출하여 면내장에 적합한 형상으로 정형되어 있는 반도체 집적회로 장치.
  15. 특허청구의 범위 제14항에 있어서, 면내장에 적합한 형상은 SOJ(Small Outline J-bend Package)형인 반도체 집적회로 장치.
  16. 특허청구 범위 제15항에 있어서, 상기 칩은 장방형의 판 형상인 반도체 집적회로 장치.
  17. 특허청구 범위 제14항에 있어서, 상기 칩은 장방형의 판 형상이고, 그 1쌍의 짧은 변에 근접해서 상기 다수의 본딩 패드가 배치되어 있는 반도체 집적 회로 장치
  18. 특허청구의 범위 제17항에 있어서, 상기 다수의 내부 리이드는 상기 장방형의 1쌍의 긴변중 어느 것인가 한쪽에서 상기 칩의 이면으로 들어가고, 상기 1쌍의 짧은 변중 어느 것인가 한쪽에서 칩밖으로 돌출하고 있는 반도체 집적 회로 장치.
  19. 특허청구의 범위 제18항에 있어서, 상기 다수의 내부 리이드는 각각 안쪽끝이 근접하고 있는 상기 어느 것인가 한쪽의 짧은 변 근방의 대응하는 본딩 패드와 본디 와이어에 의해 접속되어 있는 반도체 집적회로장치.
  20. (a) 제1 및 제2의 주면을 가지고 있는 장방형 판 형상의 반도체 칩, (b) 상기 제1의 주면상에 형성되어 있는 다수 개의 소자, (c) 상기 제1의 주면상의 1쌍의 짧은 변의 각각의 근방에 마련된 다수의 본딩 패드, (d) 상기 제2의 주면 밑은 근방의 이 주면에 평행한 평면내에 실질적으로 연장하는 다수의 내부 리이드, 다수의 내부 리이드인 제1, 제2, 제3 및 제4의 조로 구성되는 상기 내부 리이드, 상기 칩의 제1의 긴변에서 상기 칩밑으로 들어가며, 다른 내부 리이드와 교차하는 일없이 상기칩의 제1의 짧은 변에서 칩밖으로 돌출하는 상기 제1조에 대응하는 내부 리이드, 상기 칩의 제1의 긴변에서 상기 칩밑으로 들어가며, 다른 리이드와 교차하는 일 없이 상기 칩의 제2의 짧은 변에서 칩밖으로 돌출하는 상기 제2조에 대응하는 내부 리이드, 상기 칩의 제2의 긴변에서 상기 칩밑으로 들어가며, 다른 리이드와 교차하는 일 없이 상기 칩의 제2의 짧은 변에서 칩밖으로 돌출하는 상기 제4조에 대응하는 내부 리이드, 절연층에 고착되어 있는 상기 내부 리이드의 제1의 주면과 상기 칩의 상기 제2의 주면, (e) 상기 제1 및 제2의 짧은 변 근방의 다수의 본딩 패드와 상기 제1 및 제2의 짧은 변에서 돌출한 내부 리이드 사이를 상기 제1 및 제2의 짧은 변의 각각의 근방에 있어서 전기적으로 접속한 다수의 본딩 와이어, (f) 상기 칩, 내부 리이드 및 본딩 와이어의 전체를 실질적으로 성형하는 수지 성형부, 두꺼운 장방형에 근사한 거의 직육면체 형상을 하여, 제1, 제2의 긴축면과 제1, 제2의 짧은 측면과 제1, 제2의 주면을 가지고 있는 상기 성형부, 상기 성형부내에 그 긴측면과 긴변, 짧은 측면과 짧은 변, 주면과 주면이 1쌍으로써 각각 평행하게 근접하도록 상기 성형부의 대략 중앙에 매입되어 있는 상기 칩, (g) 상기 제1 및 제2조의 내부 리이드 각각에 상기 성형부의 상기 제1의 긴측면에 있어서 연결하여 외부로 돌출한 다수의 제1조의 외부 리이드, (h) 상기 제3 및 제4조의 내부 리이드의 각각에 상기 성형부의 상기 제2의 긴측면에 있어서 연결하여 외부로 돌출한 제2조의 외부 리이드, 실제적으로 한 장의 얇은 금속판으로 형성되어 있는 상기 제1, 제2, 제3 및 제4조의 내부 리이드 및 상기 제1 및 제2조의 외부 리이드, 상기 제1의 긴측면에서 그 돌출점이 그 긴측면상에 긴쪽방향으로 1직선형상으로 늘어서도록 되고, 그 위치에서 외부 리이드의 선단이 상기 제2의 긴측면 근방에 있어서 상기 성형부의 제2의 주면에 향해서 돌아가도록 상기 성형부 외면에 따라서 원호 형상으로 굽어지고, 그 원호 형상으로 정형된 외부 리이드의 하부 외면에 있어서 면내장이 가능하도록 되어 있는 상기 제2조의 외부 리이드로 구성되는 반도체 장치.
    ※ ㄴ참고사항:최초출원 내용에 의하여 공개하는 것임.
KR1019880006089A 1987-05-27 1988-05-24 수지로 충진된 반도체 장치 KR880014671A (ko)

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JP62128248A JP2543525B2 (ja) 1987-05-27 1987-05-27 樹脂封止型半導体装置
JP62-128248 1987-05-27
JP62-206913 1987-08-20
JP20691387A JPS6450451A (en) 1987-08-20 1987-08-20 Semiconductor device
JP62-234188 1987-09-18
JP62234188A JPS6477152A (en) 1987-09-18 1987-09-18 Lead frame

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