WO2005000568A2 - Lead frame device with vented die flag - Google Patents

Lead frame device with vented die flag Download PDF

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Publication number
WO2005000568A2
WO2005000568A2 PCT/US2004/019636 US2004019636W WO2005000568A2 WO 2005000568 A2 WO2005000568 A2 WO 2005000568A2 US 2004019636 W US2004019636 W US 2004019636W WO 2005000568 A2 WO2005000568 A2 WO 2005000568A2
Authority
WO
WIPO (PCT)
Prior art keywords
die
electrically
package
die paddle
aperture
Prior art date
Application number
PCT/US2004/019636
Other languages
French (fr)
Other versions
WO2005000568A3 (en
Inventor
Frank J. Juskey
Gregory J. Phipps
Daniel K. Lau
Original Assignee
Advanced Interconnect Technologies Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Interconnect Technologies Limited filed Critical Advanced Interconnect Technologies Limited
Publication of WO2005000568A2 publication Critical patent/WO2005000568A2/en
Publication of WO2005000568A3 publication Critical patent/WO2005000568A3/en

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    • H—ELECTRICITY
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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Definitions

  • This invention relates to packages for encasing one or more semiconductor devices and more particularly to a molded plastic package having enhanced moisture egress to reduce the problems of resin swelling and cracking caused by expansion of moisture trapped within such a semiconductor package.
  • Integrated circuit semiconductor devices are encased in a package that provides environmental protection and electrically interconnects the devices to external circuitry, such as a printed circuit board.
  • One common type of package is a molded plastic package.
  • the semiconductor device is bonded to a centrally disposed die paddle and electrically interconnected to inner portions of an array of leads on a lead frame.
  • a molding resin then encapsulates the semiconductor device and inner portions to provide environmental protection.
  • Outer lead portions of the lead frame extend outward from the molding resin and are electrically interconnected to the external circuitry.
  • the outer lead portions may extend outwards from the sides of the package in a J-shape or gull-wing shape as a leaded package.
  • the outer lead portions may be exposed along a bottom surface of the molding resin, as a leadless package.
  • a leadless package is referred to as a QFN, or Quad - Flat - No lead, package.
  • QFN Quad - Flat - No lead
  • One method for the manufacture of a QFN package is disclosed in United States Patent No. 6,498,099 to McLellan et al., that is incorporated by reference in its entirety herein.
  • a significant problem with the molded plastic package is a susceptibility to moisture. When exposed to a moist environment, the package absorbs moisture.
  • a metallic base and a metallic cover are adhesively joined together to define a cavity.
  • the semiconductor die and lead frame are encased in this cavity and outer portions of the lead frame extend through the adhesive to outside the package sidewalls.
  • the metallic base includes an aperture to allow the escape of reaction byproducts generated during curing of this adhesive.
  • a package for encasing at least one semiconductor die includes an electrically conductive lead frame having a centrally disposed die paddle with a first side and an opposing second side and an array of electrically isolated lead pads with a first side and an opposing second side disposed about the die paddle. At least one aperture extends from the first side of the die paddle to the second side of the die paddle. The at least one semiconductor die spans the at least one aperture and is bonded to the first side of the die attach paddle by a die attach adhesive.
  • the semiconductor die is further electrically interconnected to the array of electrically isolated lead pads by interconnects extending from input/output pads on a front surface of the at least one semiconductor die to first sides of respective lead pad members of the array of electrically isolated lead pads.
  • a molding resin encapsulates the at least one semiconductor die, the first side of the centrally disposed die paddle and the first side of the array of electrically isolated lead pads.
  • This method includes the steps of: (A) providing a laminate having an electrically conductive layer and an electrically insulating layer; (B) partially removing selected portions of the electrically conductive layer to define a centrally disposed die paddle having a first side and an opposing second side, an array of electrically isolated lead pads having a first side and an opposing second side disposed about the die paddle, and at least one aperture extending from the first side of the die paddle to the second side of the die paddle; (C) bonding the at least one semiconductor die to the die paddle whereby the at least one semiconductor die spans the at least one aperture; (D) electrically interconnecting the at least one semiconductor die to first sides of respective lead pad members of the array of electrically isolated lead pads; (E) encapsulating the at least one semiconductor die, the first side of the centrally disposed die paddle and the first side of the array of electrically isolated lead pads; (F) removing the electrically insulating layer; and (G) completely removing the selected portions of the electrically conductive layer to electrically isolate the
  • FIGS. 1 A through IE illustrate in cross-sectional representation a method to manufacture the semiconductor package of the invention.
  • FIG. 2 illustrates in top planar view a lead frame used in the manufacture of the semiconductor package of the invention.
  • FIG. 3 illustrates in cross-sectional representation the semiconductor package of the invention.
  • FIGS. 1 A through IE illustrate in cross-sectional representation a method for the manufacture of a package for encasing at least one semiconductor die.
  • the package 10 so manufactured is illustrated in cross-sectional representation in FIG. 3.
  • a laminate 12 has an electrically conductive layer 14 and an electrically insulating layer 16.
  • the electrically conductive layer 14 is formed from copper or a copper- base alloy.
  • copper-base it is meant that the alloy is predominantly, or more than 50% by weight, copper.
  • the electrically conductive layer 14 preferably has a thickness of from 0.004 inch to 0.010 inch.
  • the electrically insulating layer 16 is preferably formed from a polyimide or similar polymer and has a thickness of from 0.003 inch to 0.005 inch.
  • selected portions 18 of the electrically conductive layer 14 are partially removed. This partial removal may be by any effective means such as a chemical etch or laser ablation, h a preferred embodiment, a chemical resist coats all of a first side 20 of the electrically conductive layer 14 except for the selected portions 18.
  • the laminate 12 is then immersed in a chemical etch. The chemical etch attacks the metal forming the electrically conductive portion but not the chemical resist or the electrically insulating layer for a time period effective to partially, but not completely, remove selected portions 18.
  • the removal step defines a centrally disposed die paddle 22 and an array of lead pads 24.
  • at least one aperture 26 is formed to extend from the first side 20 to an opposing second side 28 of the electrically conductive layer. The egress of moisture absorbed by the package is facilitated by way of aperture 26. The one or more apertures prevent the package from swelling, cracking and/or fracturing caused by expansion of moisture trapped in a semiconductor package.
  • Photolithography utilizing a photoresist is one alternative to extend the aperture to all the way through the electrically conductive layer 14 while removal of the selected portions is incomplete.
  • the chemical resist if employed, is removed and at least one semiconductor die 30 is mounted to a first side 32 of the die paddle 22.
  • the at least one semiconductor die 30 is positioned to span aperture 26.
  • a die attach adhesive 34 is dispensed in a controlled amount around aperture 26. While it is desirable to avoid the flow of die attach adhesive into aperture 26 thereby forming a plug, the flow of a small amount of die attach material into the hole is not detrimental.
  • the electrically insulating layer 16 prevents any excess die attach adhesive from contaminating a second side 36 of the die paddle 22.
  • a preferred die attach material is Sumitomo 1064MB-7 (Sumitomo Plastics America Inc., Santa Clara, CA). [0024] As shown in FIG.
  • the at least one semiconductor die 30 is then electrically interconnected to a first side 38 of one of the array of lead pads 24.
  • the interconnect 40 is typically a thin gold or aluminum wire or a thin strip of copper foil as utilized in tape automated bonding as shown in FIG. ID.
  • a molding resin 42 then encapsulates the at least one semiconductor die 30, the first side 32 of the die paddle 22 and the first side 38 of the array of lead pads 24.
  • a suitable molding resin 42 is an epoxy, such as Hitachi CEL 9220 (Hitachi Chemical Co. America, Ltd., Santa Clara, CA). [0025] Referring to FIG.
  • the electrically insulating layer is then removed and the remainder of the selected portions removed thereby electrically isolating the die paddle 22 from the array of lead pads 24 and electrically isolating each one of the lead pads from the other members of the array.
  • the lead pads and the plurality of leads extending outward therefrom form an electronically conductive lead frame.
  • the laminate is provided in extended lengths and a number of package assemblies completed at the same time. In this instance, the final step of manufacture is removal of the laminate portion 44 from between packages 10, referred to as singulation.
  • FIG. 2 illustrates the laminate 12 following the step illustrated in FIG. IB. Selected portions 18 have been partially removed to define a die paddle 22 and lead pads 24.
  • FIG. 3 illustrates in cross-sectional representation the semiconductor package 10 for encasing at least one semiconductor die 30.
  • the semiconductor package 10 is preferably of the QFN type and has an electrically conductive lead frame with a centrally disposed die paddle 22 and an array of electrically isolated lead pads 24. However, it is within the scope of the invention to utilize other semiconductor packages known in the art.
  • the interconnects are typically small diameter, on the order of 0.001 inch gold or aluminum wires or thin strips of copper foil.
  • the interconnects extend from input/output pads 50 formed on an electrically active face of the semiconductor die to first sides 38 of respective lead pad members 24.
  • a molding resin 42 encapsulates the semiconductor die 30, the first side 32 of the die paddle 22 and the first side 38 of electrically isolated lead pads 24.
  • the molding resin may be any suitable polymer and is preferably Hitachi CEL 9220.

Abstract

A molded plastic semiconductor package (10) having reduced sensitivity to moisture level includes a die paddle (22) having at least one aperture (26) extending therethrough. A semiconductor die (30) is bonded to a first surface (32) of the die paddle (22) and spans the aperture (26). Once the semiconductor die (30) is electrically interconnected to an array of lead pads (24), the molding resin (42) encapsulates the semiconductor die (30) and first sides (32) of the die paddle (22) and array of lead pads (24). Opposing second sides of the die paddle (22) and array of lead pads (24) are exposed through a package surface in a QFN (Quad Flat No lead) configuration. The egress of moisture absorbed by the package (10) is facilitated by way of the aperture (26).

Description

LEAD FRAME DEVICE WITH VENTED DIE FLAG
CROSS REFERENCE TO RELATED PATENT APPLICATION [0001] This patent application relates to, and claims priority to, United States Provisional Patent Application Serial No. 60/482,533. The subject matter of that provisional patent application is incorporated by reference in its entirety herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention: [0002] This invention relates to packages for encasing one or more semiconductor devices and more particularly to a molded plastic package having enhanced moisture egress to reduce the problems of resin swelling and cracking caused by expansion of moisture trapped within such a semiconductor package.
2. Description of the Related Art: [0003] Integrated circuit semiconductor devices are encased in a package that provides environmental protection and electrically interconnects the devices to external circuitry, such as a printed circuit board. One common type of package is a molded plastic package. The semiconductor device is bonded to a centrally disposed die paddle and electrically interconnected to inner portions of an array of leads on a lead frame. A molding resin then encapsulates the semiconductor device and inner portions to provide environmental protection. Outer lead portions of the lead frame extend outward from the molding resin and are electrically interconnected to the external circuitry. [0004] The outer lead portions may extend outwards from the sides of the package in a J-shape or gull-wing shape as a leaded package. Alternatively, the outer lead portions may be exposed along a bottom surface of the molding resin, as a leadless package. One such leadless package is referred to as a QFN, or Quad - Flat - No lead, package. One method for the manufacture of a QFN package is disclosed in United States Patent No. 6,498,099 to McLellan et al., that is incorporated by reference in its entirety herein. [0005] A significant problem with the molded plastic package is a susceptibility to moisture. When exposed to a moist environment, the package absorbs moisture. When the package is subsequently exposed to elevated temperatures, such as during solder reflow to join the outer lead portions to externally circuitry, the moisture vaporizes and the resultant expanding gas may deform or rupture the molding resin leading to device failure. While advances have been made to modify the molding resins and die attach materials to limit moisture absorption, this approach has had limited success. [0006] The moisture problem is of such concern to the manufacturers of semiconductor packages that an industry standard, IPC/JEDEC J-STD-020B, was implemented for "Moisture / Reflow Sensitivity Classification for Nonhermetic Solid Sates Surface Mount Devices." Packages are classified at a level from 1 (unlimited shelf life when exposed to a temperature of 30°C and 85% relative humidity) down to level 5a (shelf life of 24 hours when exposed to a temperature of 30°C and 60% relative humidity). [0007] A different type of electronic package is a leaded metal package as disclosed in United States patent number 4,897,508 to Mahulikar et al., that is incorporated by reference in its entirety herein. A metallic base and a metallic cover are adhesively joined together to define a cavity. The semiconductor die and lead frame are encased in this cavity and outer portions of the lead frame extend through the adhesive to outside the package sidewalls. In one embodiment, the metallic base includes an aperture to allow the escape of reaction byproducts generated during curing of this adhesive. [0008] In a molded plastic package of the type having molding resin on both sides of the die paddle, differences in molding resin pressure have been known to cause the die paddle to move or distort. United States Patent No. 5,708,294 to Toriyama discloses forming slits in the die paddle so that molding resin may pass through the die paddle and apply equal pressure to both sides. The Toriyama patent is incorporated by reference in its entirety herein. [0009] While changes in the molding resin and die attach materials have increased the moisture resistance of a molded plastic semiconductor package, there remains a need for a molded plastic semiconductor package better able to achieve JEDEC J-STD-020B level 1 classification. This invention is believed to be an answer to that need.
BRIEF SUMMARY OF THE INVENTION [0010] In accordance with a first embodiment of the invention, there is provided a package for encasing at least one semiconductor die. The package includes an electrically conductive lead frame having a centrally disposed die paddle with a first side and an opposing second side and an array of electrically isolated lead pads with a first side and an opposing second side disposed about the die paddle. At least one aperture extends from the first side of the die paddle to the second side of the die paddle. The at least one semiconductor die spans the at least one aperture and is bonded to the first side of the die attach paddle by a die attach adhesive. The semiconductor die is further electrically interconnected to the array of electrically isolated lead pads by interconnects extending from input/output pads on a front surface of the at least one semiconductor die to first sides of respective lead pad members of the array of electrically isolated lead pads. A molding resin encapsulates the at least one semiconductor die, the first side of the centrally disposed die paddle and the first side of the array of electrically isolated lead pads. [0011] It is a feature of this first embodiment that the aperture provides a low resistance escape path for moisture that will prevent the package from bulging or fracturing due to the expansion of stream when heated. [0012] In accordance with a second embodiment of the invention, there is provided a method for the manufacture of a package for encasing at least one semiconductor die. This method includes the steps of: (A) providing a laminate having an electrically conductive layer and an electrically insulating layer; (B) partially removing selected portions of the electrically conductive layer to define a centrally disposed die paddle having a first side and an opposing second side, an array of electrically isolated lead pads having a first side and an opposing second side disposed about the die paddle, and at least one aperture extending from the first side of the die paddle to the second side of the die paddle; (C) bonding the at least one semiconductor die to the die paddle whereby the at least one semiconductor die spans the at least one aperture; (D) electrically interconnecting the at least one semiconductor die to first sides of respective lead pad members of the array of electrically isolated lead pads; (E) encapsulating the at least one semiconductor die, the first side of the centrally disposed die paddle and the first side of the array of electrically isolated lead pads; (F) removing the electrically insulating layer; and (G) completely removing the selected portions of the electrically conductive layer to electrically isolate the centrally disposed die paddle from the array of electrically isolated lead pads. [0013] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the invention will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS [0014] FIGS. 1 A through IE illustrate in cross-sectional representation a method to manufacture the semiconductor package of the invention. [0015] FIG. 2 illustrates in top planar view a lead frame used in the manufacture of the semiconductor package of the invention. [0016] FIG. 3 illustrates in cross-sectional representation the semiconductor package of the invention. [0017] Like reference numbers and designations in the various drawings indicate like elements.
DETAILED DESCRIPTION
[0018] FIGS. 1 A through IE illustrate in cross-sectional representation a method for the manufacture of a package for encasing at least one semiconductor die. The package 10 so manufactured is illustrated in cross-sectional representation in FIG. 3. With reference back to FIG. 1A, a laminate 12 has an electrically conductive layer 14 and an electrically insulating layer 16. Preferably, the electrically conductive layer 14 is formed from copper or a copper- base alloy. By "copper-base" it is meant that the alloy is predominantly, or more than 50% by weight, copper. The electrically conductive layer 14 preferably has a thickness of from 0.004 inch to 0.010 inch. [0019] The electrically insulating layer 16 is preferably formed from a polyimide or similar polymer and has a thickness of from 0.003 inch to 0.005 inch. [0020] Referring to FIG. 1 B, selected portions 18 of the electrically conductive layer 14 are partially removed. This partial removal may be by any effective means such as a chemical etch or laser ablation, h a preferred embodiment, a chemical resist coats all of a first side 20 of the electrically conductive layer 14 except for the selected portions 18. The laminate 12 is then immersed in a chemical etch. The chemical etch attacks the metal forming the electrically conductive portion but not the chemical resist or the electrically insulating layer for a time period effective to partially, but not completely, remove selected portions 18. The removal step defines a centrally disposed die paddle 22 and an array of lead pads 24. [0021] During this removal step, at least one aperture 26 is formed to extend from the first side 20 to an opposing second side 28 of the electrically conductive layer. The egress of moisture absorbed by the package is facilitated by way of aperture 26. The one or more apertures prevent the package from swelling, cracking and/or fracturing caused by expansion of moisture trapped in a semiconductor package. [0022] Photolithography utilizing a photoresist is one alternative to extend the aperture to all the way through the electrically conductive layer 14 while removal of the selected portions is incomplete. [0023] Referring now to FIG. 1C, following the removal step, the chemical resist, if employed, is removed and at least one semiconductor die 30 is mounted to a first side 32 of the die paddle 22. The at least one semiconductor die 30 is positioned to span aperture 26. A die attach adhesive 34 is dispensed in a controlled amount around aperture 26. While it is desirable to avoid the flow of die attach adhesive into aperture 26 thereby forming a plug, the flow of a small amount of die attach material into the hole is not detrimental. The electrically insulating layer 16 prevents any excess die attach adhesive from contaminating a second side 36 of the die paddle 22. A preferred die attach material is Sumitomo 1064MB-7 (Sumitomo Plastics America Inc., Santa Clara, CA). [0024] As shown in FIG. ID, the at least one semiconductor die 30 is then electrically interconnected to a first side 38 of one of the array of lead pads 24. The interconnect 40 is typically a thin gold or aluminum wire or a thin strip of copper foil as utilized in tape automated bonding as shown in FIG. ID. A molding resin 42 then encapsulates the at least one semiconductor die 30, the first side 32 of the die paddle 22 and the first side 38 of the array of lead pads 24. A suitable molding resin 42 is an epoxy, such as Hitachi CEL 9220 (Hitachi Chemical Co. America, Ltd., Santa Clara, CA). [0025] Referring to FIG. IE, the electrically insulating layer is then removed and the remainder of the selected portions removed thereby electrically isolating the die paddle 22 from the array of lead pads 24 and electrically isolating each one of the lead pads from the other members of the array. The lead pads and the plurality of leads extending outward therefrom form an electronically conductive lead frame. [0026] Typically, the laminate is provided in extended lengths and a number of package assemblies completed at the same time. In this instance, the final step of manufacture is removal of the laminate portion 44 from between packages 10, referred to as singulation. [0027] FIG. 2 illustrates the laminate 12 following the step illustrated in FIG. IB. Selected portions 18 have been partially removed to define a die paddle 22 and lead pads 24. Portions of the laminate 44 that extend beyond the intended perimeter (shown as broken line 46) of the package will be removed during singulation. Aperture 26 extends through the die paddle 22. Alternatively, a plurality of apertures may extend through the die paddle 22. Frequently, a corner 48 is different from the other corners of the die paddle 22 to assist with alignment of the semiconductor die and wire bond equipment. [0028] FIG. 3 illustrates in cross-sectional representation the semiconductor package 10 for encasing at least one semiconductor die 30. The semiconductor package 10 is preferably of the QFN type and has an electrically conductive lead frame with a centrally disposed die paddle 22 and an array of electrically isolated lead pads 24. However, it is within the scope of the invention to utilize other semiconductor packages known in the art. [0029] At least one aperture 26 extends through the die paddle. While FIG. 3 illustrates a single aperture 26 extending through die paddle 22, it is within the scope of the invention for there to be multiple apertures extending through a single die paddle. [0030] The semiconductor die 30 spans the aperture 26 (or the multiple apertures if such are present) and is bonded to the die paddle 22 by a die attach adhesive 34. The die attach adhesive is preferably a polymer, such as an epoxy, for example Sumitomo 1064, to enhance egress of moisture from the semiconductor package 10 through the aperture 26. The semiconductor die 30 is electrically interconnected to the array of electrically isolated lead pads 24 by interconnects 40. The interconnects are typically small diameter, on the order of 0.001 inch gold or aluminum wires or thin strips of copper foil. The interconnects extend from input/output pads 50 formed on an electrically active face of the semiconductor die to first sides 38 of respective lead pad members 24. [0031] A molding resin 42 encapsulates the semiconductor die 30, the first side 32 of the die paddle 22 and the first side 38 of electrically isolated lead pads 24. The molding resin may be any suitable polymer and is preferably Hitachi CEL 9220. [0032] One or more embodiments of the present invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.

Claims

CLAIMSWHAT IS CLAIMED IS:
1. A package (10) for encasing at least one semiconductor die (30), comprising: an electrically conductive lead frame having a centrally disposed die paddle (22) with a first side (32) and an opposing second side and an array of electrically isolated lead pads (24) with a first side (38) and an opposing second side disposed about said die paddle (22), at least one aperture (26) extending from said first side (32) of said die paddle (22) to said second side of said die paddle (22); said at least one semiconductor (30) die spanning said at least one aperture (26) and bonded to said first side (32) of said die paddle (22) by a die attach adhesive (34) and electrically interconnected to said array of electrically isolated lead pads (24) by interconnects (40) extending from input/output pads (50) of said at least one semiconductor die (30) to first sides (38) of respective lead pad members of said array of electrically isolated lead pads (24); and a molding resin (42) encapsulating said at least one semiconductor die (30), said first side (32) of said centrally disposed die paddle (22) and said first side (38) of said array of electrically isolated lead pads (24).
2. The package of claim 1 wherein said aperture (26) is effective for the egress of moisture that accumulates in the resin (42).
3. The package of claim 1 wherein said at least one aperture (26) is formed by photolithography.
4. The package of claim 3 wherein said photolithography forms a plurality of apertures (26).
5. The package of claim 3 wherein said photolithography forms a single aperture (26).
6. A method for the manufacture of a package (10) for encasing at least one semiconductor die (30), comprising the steps of: providing a laminate (12) having an electrically conductive layer (14) and an electrically insulating layer (16); partially removing selected portions (18) of said electrically conductive layer (14) to define a centrally disposed die paddle (22) having a first side (32) and an opposing second side, an array of electrically isolated lead pads (24) having a first side (38) and an opposing second side disposed about said die paddle (22), and at least one aperture (26) extending from said first side (32) of said die paddle (22) to said second side of said die paddle; bonding said at least one semiconductor die (30) to said die paddle (22) whereby said at least one semiconductor die (30) spans said at least one aperture (26); electrically interconnecting said at least one semiconductor die (30) to first sides (38) of respective lead pad members of said aπay of electrically isolated lead pads (24); encapsulating said at least one semiconductor die (30), said first side (32) of said centrally disposed die paddle (22) and said first side (38) of said aπay of electrically isolated lead pads (24); removing said electrically insulating layer (16); and completely removing said selected portions (18) of said electrically conductive layer (14) to electrically isolate said centrally disposed die paddle (22) from array of electrically isolated lead pads (24).
7. The method of claim 6 wherein said electrically conductive layer (14) is copper or a copper-base alloy.
8. The method of claim 7 wherein said electrically conductive layer (14) has a thickness of from 0.004 inch to 0.010 inch.
9. The method of claim 6 wherein said electrically insulating layer (16) is polyimide.
10. The method of claim 9 wherein said electrically insulating layer (16) has a thickness of from 0.003 inch to 0.005 inch.
PCT/US2004/019636 2003-06-25 2004-06-16 Lead frame device with vented die flag WO2005000568A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US48253303P 2003-06-25 2003-06-25
US60/482,533 2003-06-25

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013023840A1 (en) 2011-08-12 2013-02-21 Telefonaktiebolaget L M Ericsson (Publ) Channel quality index determination
US9281218B2 (en) 2006-08-30 2016-03-08 United Test And Assembly Center Ltd. Method of producing a semiconductor package

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR880014671A (en) * 1987-05-27 1988-12-24 미다 가쓰시게 Resin Filled Semiconductor Device
JPH047850A (en) * 1990-04-25 1992-01-13 Mitsubishi Electric Corp Tape carrier
JP3019821B2 (en) * 1997-10-22 2000-03-13 日本電気株式会社 Semiconductor device
TWI267958B (en) * 2002-11-21 2006-12-01 Siliconware Precision Industries Co Ltd Semiconductor package with stilts for supporting dice
US6867481B2 (en) * 2003-04-11 2005-03-15 Fairchild Semiconductor Corporation Lead frame structure with aperture or groove for flip chip in a leaded molded package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9281218B2 (en) 2006-08-30 2016-03-08 United Test And Assembly Center Ltd. Method of producing a semiconductor package
US9842792B2 (en) 2006-08-30 2017-12-12 UTAC Headquarters Pte. Ltd. Method of producing a semiconductor package
WO2013023840A1 (en) 2011-08-12 2013-02-21 Telefonaktiebolaget L M Ericsson (Publ) Channel quality index determination

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