KR930020649A - 리이드프레임 및 그것을 사용한 반도체집적회로장치와 그 제조방법 - Google Patents

리이드프레임 및 그것을 사용한 반도체집적회로장치와 그 제조방법 Download PDF

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Publication number
KR930020649A
KR930020649A KR1019930004078A KR930004078A KR930020649A KR 930020649 A KR930020649 A KR 930020649A KR 1019930004078 A KR1019930004078 A KR 1019930004078A KR 930004078 A KR930004078 A KR 930004078A KR 930020649 A KR930020649 A KR 930020649A
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South Korea
Prior art keywords
lead
inner lead
manufacturing
suspension
chip
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KR1019930004078A
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English (en)
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KR100552353B1 (ko
Inventor
유지로 가지하라
가즈나리 스즈끼
구니히로 쯔보사끼
히로미찌 스즈끼
요시노리 미야끼
다까히로 나이또
스에오 가와이
Original Assignee
가나이 쯔또무
가부시끼가이샤 히다찌세이사꾸쇼
오야 유이찌로
가부시끼가이샤 히다찌마이컴시스템
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Application filed by 가나이 쯔또무, 가부시끼가이샤 히다찌세이사꾸쇼, 오야 유이찌로, 가부시끼가이샤 히다찌마이컴시스템 filed Critical 가나이 쯔또무
Publication of KR930020649A publication Critical patent/KR930020649A/ko
Priority to KR1020050087296A priority Critical patent/KR100548093B1/ko
Priority to KR1020050087298A priority patent/KR100548092B1/ko
Priority to KR1020050087297A priority patent/KR100548091B1/ko
Application granted granted Critical
Publication of KR100552353B1 publication Critical patent/KR100552353B1/ko

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Abstract

반도체칩을 탑재하는 리이드프레임 및 그것을 사용한 반도체집적회로장치와 그 제조방법에 관한 것으로써, LSI패키지의 리플로 균열내성을 향상시키며, 또한 소량다품종 LSI패키지를 제공하기 위해, 다이패드(3)의 외형 치수를 그위에 탑재하는 반도체칩(2)의 외형치수보다도 작게 하는 것에 의해 반도체칩(2)와 수지의 접착면적을 크게하고, 반도체칩(2)의 외형치수에 따라서 리이드(5)의 선단을 적절한 길이로 절단하는 것에 의해, 외형치수가 다른 각종 반도체칩(2)를 다이패드(3)상에 탑재가능하게 하였다.
이러한 것을 취하는 것에 의해, LSI패키지의 리플로균열내성이 향상되고, 코스트저감을 실현할 수 있다.

Description

리이드프레임 및 그것을 사용한 반도체집적회로장치와 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예인 리이드프레임의 평면도이다.
제2도는 본 발명의 리이드프레임의 프레스공정을 도시한 평면도이다.
제3도는 본 발명의 리이드프레임의 프레스공정을 도시한 설명도이다.
제4도는 본 발명의 리이드프레임의 도금공정을 도시한 평면도이다.
제5도는 본 발명의 리이드프레임의 다운세트공정을 도시한 설명도이다.
제6도는 본 발명의 리이드프레임의 다운세트공정을 시도한 평면도이다.
제7도는 본 발명의 리이드프레임의 테이프접착공정을 도시한 설명도이다.
제8도는 본 발명의 리이드프레임의 테이프접착공정을 도시한 평면도이다.

Claims (24)

  1. 크기가 다른 여러종류의 반도체칩을 탑재할 수 있는 리이드프레임에 있어서, 소정의 크기를 갖는 반도체칩을 탑재하기 위한 칩탑재부 및 상기 칩탑재부를 지지하고 있는 서스펜션리이드, 상기 칩탑재부의 주위를 둘러싸도록 배치되며, 또한 탑재되는 반도체칩의 크기에 따라서 절단할 수 있는 영역을 포함하는 내부리이드부 및 상기 내부리이드부에 접속하고, 상기 내부리이드부에서 외부로 향하는 방향으로 연장하는 외부리이드부로 이루어지는 여러개의 리이드부 및 상기 내부리이드부에 있어서 와이어가 본딩되며, 또한 상기 절단할 수 있는 영역에 형성된 도금층을 포함하며, 상기 칩탑재부의 칩탑재영역의 면적은 탑재되어야할 반도체칩의 면적보다도 작은 리이드프레임.
  2. 특허청구의 범위 제1항에 있어서, 또 상기 내부리이드부 및 서스펜션리이드를 지지하기 위한 절연층을 포함하며, 상기 절연층은 상기내부리이드부에서 상기 서스펜션리이드에 걸쳐서 연속해서 형성되어 있는 리이드프레임.
  3. 특허청구의 범위 제1항에 있어서, 또 상기 서스펜션리이드에 형성된 여러개의 접착제 도포부를 포함하는 리이드프레임.
  4. 특허청구의 범위 제1항에 있어서, 또 상기 서스펜션리이드는 4개로 이루어지며, 그 각각에 여러개의 위치결정을 위한 홈이 형성되어 있는 리이드프레임.
  5. 특허청구의 범위 제1항에 있어서, 또 상기 서스펜션리이드는 4개로 이루어지며, 그 각각에 여러개의 위치결정을 위한 돌기가 형성되어 있는 리이드프레임.
  6. 특허청구의 범위 제1항에 있어서, 상기 내부리이드부의 길이는 상기 서스펜션리이드의 가까이에 위치하는 내부리이드부의 쪽이 상기 서스펜션리이드에서 멀리에 위치하는 내부리이드부보다도 긴 리이드프레임.
  7. 크기가 다른 여러종류의 반도체칩을 탑재할 수 있는 리이드프레임의 제조방법에 있어서, 제1의 면과 그것과 대향하는 제2의 면을 갖는 1개의 판형상의 프레임을 준비하는 공정, 상기 프레임의 제1의 면에서 제2의 면으로 향하는 방향으로 절단하는 것에 의해서 소정의 크기를 갖는 반도체칩을 탑재하기 위한 칩탑재부 및 상기 칩탑재부를 지지하고 있는 서스펜션리이드를 형성하는 공정, 상기 프레임의 제2의 면에서 제1의 면에서 향하는 방향으로 절단하는 것에 의해서 내부리이드부를 형성하는 공정 및 상기 내부리이드부에 접속하고, 상기 내부리이드부에서 외부로 향하는 방향으로 연장하는 외부리이드부를 형성하는 공정을 포함하며, 상기 칩탑재부의 칩탑재영역의 면적은 탑재되어야할 반도체칩의 면적보다도 작고, 상기 내부리이드부는 상기 칩탑재부의 주위를 둘러싸도록 배치되며, 또한 탑재되는 반도체칩의 크기에 따라서 절단할 수 있는 영역을 포함하며, 상기 내부리이드부에 있어서 와이어본딩되며, 또한 상기 절단할 수 있는 영역에 도금층을 형성하는 리이드프레임의 제조방법.
  8. 특허청구의 범위 제7항에 있어서, 또 상기 내부리이드부 및 서스펜션리이드를 지지하기 위한 절연층을 형성하는 공정을 포함하며, 상기 절연층은 상기 내부리이드부에서 상기 서스펜션리이드에 걸쳐서 연속해서 형성되어있는 리이드프레임의 제조방법.
  9. 특허청구의 범위 제7항에 있어서, 또 상기 서스펜션리이드에 여러개의 접착제도포부를 형성하는 공정을 포함하는 리이드프레임의 제조방법.
  10. 특허청구의 범위 제7항에 있어서, 또 상기 서스펜션리이드는 4개로 이루어지고, 그 각각에 여러개의 위치 결정을 위한 홈을 형성하는 공정을 포함하는 리이드프레임의 제조방법.
  11. 특허청구의 범위 제7항에 있어서, 또 상기 서스펜션리이드는 4개로 이루어지며, 그 각각에 여러개의 위치 결정을 위한 돌기를 형성하는 공정을 포함하는 리이드프레임의 제조방법.
  12. 특허청구의 범위 제7항에 있어서, 상기 내부리이드부의 길이는 상기 서스펜션리이드의 가까이에 위치하는 내부리이드부가 상기 서스펜션리이드에서 멀리 위치하는 내부 리이드부보다도 긴 리이드프레임의 제조방법.
  13. 크기가 다른 여러종류의 반도체칩을 탑재할 수 있는 리이드프레임을 사용한 반도체집적회로장치의 제조방법에 있어서, 제1의 면과 제2의 면을 갖는 리이드프레임을 준비하는 공정, 주면에 집적회로와 여러개의 본딩패드가 형성된 정사각형형상의 반도체칩을 준비하는 공정, 상기 반도체칩을 상기 칩탑재부에 본딩하는 공정, 상기 본딩패드와 내부리이드부를 각각 전기적으로 접속하는 공정 및 상기 반도체칩, 상기 내부리이드부 및 상기 칩탑재부를 봉하는 공정을 포함하며, 상기 리이드프레임은 소정의 크기의 반도체칩을 탑재하기 위한 칩탑재부, 상기 칩탑재부를 지지하고 있는 여러개의 서스펜션리이드, 상기칩 탑재부를 둘러싸도록 배치되며, 또한 탑재되는 반도체칩의 크기에 다라서 절단할 수 있는 영역을 포함하는 여러개의 내부리이드부 및 각각이 상기 내부리이드부와 접속되고, 외부로 향하는 방향으로 연장하는 외부리이드부로 이루어지고, 상기 내부리이드부의 제1의 면에 있어서 와이어가 본딩되며, 또한 상기 절단할 수 있는 영역에 도금층이 형성되어 있고, 상기 내부리이드부의 선단부는 탑재되는 칩의 크기에 대응해서 그 선단부를 절단하고 있는 반도체집적회로장치의 제조방법.
  14. 특허청구의 범위 제13항에 있어서, 상기 내부리이드부 및 서스펜션리이드를 지지하기 위한 절연층이 형성되어 있고, 상기 절연층은 상기 내부리이드부에서 상기 서스펜션 리이드에 걸쳐서 연속해서 형성되어 있는 반도체집적회로장치의 제조방법.
  15. 특허청구의 범위 제13항에 있어서, 또 상기 칩탑재부에 접착제를 공급하는 공정 및 상기 접착제를 거쳐서 상기 반도체칩을 상기 칩탑재부에 본딩하는 공정을 포함하는 반도체집적회로장치의 제조방법.
  16. 특허청구의 범위 제13항에 있어서, 상기 서스펜션리이드에 여러개의 접착제도포부가 형성되어 있는 반도체 집적회장치의 제조방법.
  17. 특허청구의 범위 제16항에 있어서, 또 상기 칩탑재부 및 상기 접착제도포부에 접착제를 공급하는 공정 및 상기 접착제를 거쳐서 상기 반도체칩을 상기 칩탑재부에 본딩하는 공정을 포함하는 반도체집적회로장치의 제조방법.
  18. 특허청구의 범위 제13항에 있어서, 상기 서스펜션리이드는 4개로 이루어지며, 그 각각에 여러개의 위치결정을 위한 홈이 형성되어 있는 반도체집적회로장치의 제조방법.
  19. 특허청구의 범위 제18항에 있어서, 또 상기 홈의 위치를 검출하고, 상기 홈에 의해서 상기 정사각형형상의 반도체칩의 본딩위치를 결정한 후 상기 반도체칩을 상기 칩탑재부에 본딩하는 공정을 포함하는 반도체집적회로장치의 제조방법.
  20. 특허청구의 범위 제13항에 있어서, 상기 서스펜션리이드는 4개로 이루어지며, 그 각각에 여러개의 위치결정을 위한 돌기가 형성되어 있는 반도체집적회로장치의 제조방법.
  21. 특허청구의 범위 제20항에 있어서, 또 상기 돌기의 위치를 검출하고, 상기 돌기에 의해서 상기 정사각형형상의 반도체칩의 본딩위치를 결정한 후 상기 반도체칩을 상기 칩탑재부에 본딩하는 공정을 포함하는 반도체집적회로장치의 제조방법.
  22. 특허청구의 범위 제13항에 있어서, 상기 내부리이드부의 길이는 상기 서스펜션리이드의 가까이에 위치하는 내부리이드부가 상기 서스펜션리이드에서 멀리에 위치하는 내부리이드부보다도 긴 반도체집적회로장치의 제조방법.
  23. 특허청구의 범위 제13항에 있어서, 상기 와이어본딩공저에 있어서, 상기 반도체칩을 탑재한 리이드프레임은 와이어본딩을 위한 허트스페이지에 탑재되어 와이어본딩되는 반도체집적회로장치의 제조방법.
  24. 특허 청구의 범위 제23항에 있어서, 상기 칩탑재부의 제1의 면은 상기 내부리이드부의 제1의 면보다도 제2의 면에 가까운 쪽에 위치하고 있고, 상기 히트스테이지에는 홈부가 형성되고, 상기 칩탑재부를 상기 홈부에 삽입하여 와이어 본딩되는 반도체집적회로장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930004078A 1992-03-27 1993-03-17 리이드프레임및그것을사용한반도체집적회로장치와그제조방법 KR100552353B1 (ko)

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