JP5634149B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5634149B2 JP5634149B2 JP2010161699A JP2010161699A JP5634149B2 JP 5634149 B2 JP5634149 B2 JP 5634149B2 JP 2010161699 A JP2010161699 A JP 2010161699A JP 2010161699 A JP2010161699 A JP 2010161699A JP 5634149 B2 JP5634149 B2 JP 5634149B2
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- lead
- semiconductor device
- plating
- free plating
- particles
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/1576—Iron [Fe] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
図1は本発明の実施の形態の半導体装置の製造方法によって組み立てられる半導体装置の構造の一例を示す平面図、図2は図1に示すA−A線に沿って切断した構造を示す断面図、図3は図2に示すA部におけるめっき構造の一例を示す部分断面図である。
2 マトリクスフレーム
2a インナリード
2b アウタリード
2c タブ(ダイパッド)
2d デバイス領域
2e 枠部
2f スプロケットホール
2g 長孔
2h 主面
2i ワイヤ接合部
2j 切断面
3 封止体
4 半導体チップ
4a 主面
4b 裏面
4c 電極パッド(表面電極)
5 ワイヤ
7 ダイボンディング材
8 外装めっき
8a 粒子層
8b 中心
8c 界面側
8d 表面側
8e (111)配向方向
8f C軸方向
8g,8h 結晶
9 銀めっき
9a 下地銅めっき
50 (111)配向方向
51 C軸方向
52,53 結晶
54 フレーム素材
55 外装めっき
Claims (16)
- 複数の表面電極が設けられた半導体チップと、
前記半導体チップが搭載されたダイパッドと、
前記半導体チップの周囲に配置された複数のリードと、
前記半導体チップの前記複数の表面電極と前記複数のリードとをそれぞれ電気的に接続する複数のワイヤと、
前記半導体チップ及び前記複数のワイヤを封止する封止体と、
前記複数のリードのそれぞれのうちの前記封止体から露出する表面に形成された鉛フリーめっきと、
を有し、
前記鉛フリーめっきは、(211)、(332)または(432)の配向を持った粒子を有し、
前記鉛フリーめっきの前記配向は、温度サイクル環境試験後の前記鉛フリーめっきの前記リードに対する垂直方向の解析における配向であり、
前記鉛フリーめっきは、その厚み方向の中心から前記リードに近い界面側と前記鉛フリーめっきの表面に近い表面側とで、前記界面側に存在する直径1μm以下の粒子の数が、前記表面側に存在する直径1μm以下の粒子の数より多い、半導体装置。 - 請求項1記載の半導体装置において、前記複数のリードのそれぞれは、鉄−ニッケル合金または銅合金から成る、半導体装置。
- 請求項2記載の半導体装置において、前記鉛フリーめっきは、錫を主材とするめっきであることを特徴とする、半導体装置。
- 請求項3記載の半導体装置において、前記複数のリードのそれぞれのワイヤ接合部に銀めっきが形成されている、半導体装置。
- 請求項1記載の半導体装置において、前記鉛フリーめっきの厚みに対して直径1μm以下の粒子を有する粒子層の厚みが1/10である、半導体装置。
- 請求項1記載の半導体装置において、前記鉛フリーめっきには、直径1μm以下の粒子が45%以上存在する、半導体装置。
- 請求項1記載の半導体装置において、前記鉛フリーめっきの厚み方向の中心から前記リードに近い前記界面側には、直径1μm以下の粒子が50%以上存在する、半導体装置。
- 請求項1記載の半導体装置において、前記鉛フリーめっきの厚み方向の中心から前記鉛フリーめっきの表面に近い前記表面側には、直径1μm以下の粒子が35%以上存在する、半導体装置。
- 請求項1記載の半導体装置において、温度サイクル環境試験後に、前記鉛フリーめっきには、直径1μm以下の粒子が45%以上存在する、半導体装置。
- 請求項1記載の半導体装置において、前記鉛フリーめっき内には、直径1μm以下の複数の粒子から成る層を有し、
前記層の厚みが1.5μm以上である、半導体装置。 - 請求項1記載の半導体装置において、前記鉛フリーめっきには、複数の異なる直径の粒子が含まれており、前記複数の異なる直径の粒子の平均断面積が2.5μm2以下である、半導体装置。
- 請求項1記載の半導体装置において、前記鉛フリーめっきには、複数の異なる直径の粒子が含まれており、前記鉛フリーめっきの厚み方向の中心から前記鉛フリーめっきの表面に近い前記表面側において、前記複数の異なる直径の粒子の平均断面積が2.4μm2以下である、半導体装置。
- 請求項1記載の半導体装置において、前記鉛フリーめっきには、複数の異なる直径の粒子が含まれており、前記鉛フリーめっきの厚み方向の中心から前記リードに近い前記界面側において、前記複数の異なる直径の粒子の平均断面積が1.6μm2以下である、半導体装置。
- 請求項1記載の半導体装置において、前記鉛フリーめっきには、複数の異なる直径の粒子が含まれており、前記鉛フリーめっきの前記複数の異なる直径の粒子の持つ線膨張係数が21ppm以下である、半導体装置。
- 請求項1記載の半導体装置において、前記鉛フリーめっきには、複数の異なる直径の粒子が含まれており、前記鉛フリーめっきの前記複数の異なる直径の粒子と前記リードとの線膨張係数差の平均値が16.3ppm以下である、半導体装置。
- 請求項1記載の半導体装置において、前記鉛フリーめっきの前記配向は、温度サイクル環境試験後の前記鉛フリーめっきの前記リードに対する前記垂直方向および水平方向の解析における配向である、半導体装置。
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US13/181,856 US8319330B2 (en) | 2010-07-16 | 2011-07-13 | Semiconductor package having exterior plating films formed over surfaces of outer leads |
CN201110204593.XA CN102339804B (zh) | 2010-07-16 | 2011-07-15 | 半导体器件 |
KR1020110070266A KR101807878B1 (ko) | 2010-07-16 | 2011-07-15 | 반도체 장치 |
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JP2015056540A (ja) * | 2013-09-12 | 2015-03-23 | 株式会社東芝 | 半導体装置及びその製造方法 |
US10147697B1 (en) * | 2017-12-15 | 2018-12-04 | Nxp Usa, Inc. | Bond pad structure for semiconductor device packaging |
JP6733940B1 (ja) * | 2019-03-22 | 2020-08-05 | 大口マテリアル株式会社 | リードフレーム |
JP6733941B1 (ja) * | 2019-03-22 | 2020-08-05 | 大口マテリアル株式会社 | 半導体素子搭載用基板 |
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JP6736719B1 (ja) * | 2019-03-28 | 2020-08-05 | 大口マテリアル株式会社 | 半導体素子搭載用部品、リードフレーム及び半導体素子搭載用基板 |
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