US20230411258A1 - Semiconductor device and corresponding method - Google Patents

Semiconductor device and corresponding method Download PDF

Info

Publication number
US20230411258A1
US20230411258A1 US18/241,414 US202318241414A US2023411258A1 US 20230411258 A1 US20230411258 A1 US 20230411258A1 US 202318241414 A US202318241414 A US 202318241414A US 2023411258 A1 US2023411258 A1 US 2023411258A1
Authority
US
United States
Prior art keywords
semiconductor device
molding material
enlarged end
plating layer
package molding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
US18/241,414
Inventor
Michele DERAI
Roberto Tiziani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Priority to US18/241,414 priority Critical patent/US20230411258A1/en
Publication of US20230411258A1 publication Critical patent/US20230411258A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8134—Bonding interfaces of the bump connector
    • H01L2224/81345—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Definitions

  • the description relates to manufacturing semiconductor devices.
  • One or more embodiments may be applied to manufacturing integrated circuits (ICs).
  • ICs integrated circuits
  • Quad-flat no-leads (QFN) packages and land grid array (LGA) packages are examples of surface-mount technology (SMT) packages known in the art.
  • SMT surface-mount technology
  • QFN packages are near chip-scale plastic encapsulated packages provided with a planar leadframe substrate, wherein perimeter lands on the package rear (e.g., bottom) side are configured to provide electrical connections to a printed circuit board (PCB).
  • the leads of the leadframe are thus fully incorporated in the package molding compound.
  • QFN packages may include an exposed thermal pad to improve heat transfer out of the integrated circuit, into the printed circuit board.
  • LGA packages also have leads fully incorporated in the package molding compound, and comprise a (rectangular) grid of contacts on the bottom side of the package.
  • the contacts on the package are configured to be coupled to a grid of contacts on the PCB.
  • Both QFN and LGA packages do not have external leads, but rather have “lands” or “pads” that are directly couplable to the PCB pads for soldering by means of solder paste or solder alloy.
  • the mounting (soldering) step may be complex and may result in a wide variability of welding strength and structure. Additionally, the different coefficients of thermal expansion between the package and the printed circuit board may lead to high stress in the solder material and/or to high thermal fatigue of QFN/LGA packages once mounted on a printed circuit board.
  • Wettable flanks help increase wettability of the leads with the purpose of improving solder adhesion and overall welding strength by increasing the solder attachment area on the vertical side of the lands or pads. Wettable flanks may only slightly improve the solder joint reliability, and facilitate automatic optical inspection of the solder joint after the surface mounting process, for surface mount process control.
  • Packaged semiconductor devices providing improved solder joint reliability and/or stronger anchorage to the PCB are desirable.
  • One or more embodiments may relate to a semiconductor device (e.g., an integrated circuit).
  • a semiconductor device e.g., an integrated circuit
  • One or more embodiments may relate to a corresponding method of manufacturing semiconductor devices.
  • One or more embodiments may provide a packaged semiconductor device (e.g., comprising a QFN or LGA package) comprising at least one semiconductor die electrically coupled to a set of electrically conductive leads, and package molding material molded over the at least one semiconductor die and the electrically conductive leads. At least a portion of the electrically conductive leads may be exposed at a rear surface of the package molding material to provide electrically conductive pads.
  • the electrically conductive pads may comprise enlarged end portions extending at least partially over the package molding material and configured for coupling to a printed circuit board.
  • FIG. 1 is a perspective view exemplary of a semiconductor device comprising a QFN package, shown upside-down (i.e., with the rear side facing upwards);
  • FIG. 3 A is a magnified view of a portion of the rear side of the semiconductor device of FIG. 2 ;
  • FIG. 4 B is a side view of the portion of the semiconductor device of FIG. 4 A mounted on a printed circuit board;
  • FIGS. 5 A to 5 G are exemplary of steps of a method of manufacturing semiconductor devices according to embodiments.
  • FIG. 3 A is a magnified view exemplary of a portion of the rear side 10 A of the integrated circuit 10 , e.g., portion 20 illustrated in FIG. 2 .
  • FIG. 3 B is a corresponding side view of portion 20 , exemplary of the integrated circuit 10 mounted on a printed circuit board by means of soldering material 32 interposed between the electrical pads 12 of the integrated circuit 10 and the respective solder pads 12 ′ on the PCB 30 .
  • reliability of such electro-mechanical coupling may be improved by increasing the area of the electrical pads 12 of the integrated circuit 10 .
  • the enlarged end portions 44 may comprise at least one metal selected out of copper (Cu), nickel (Ni), palladium (Pd) and gold (Au).
  • the enlarged end portions 44 comprise copper (Cu).
  • a further metallic layer may be provided over the enlarged end portions 44 .
  • the further metallic layer may comprise tin (Sn) plated over the enlarged end portions 44 at the pads 12 and/or 14 .
  • FIGS. 5 A to 5 G are exemplary of possible steps of a method of manufacturing semiconductor devices according to one or more embodiments.
  • manufacturing of a pair of semiconductor devices in exemplified.
  • wire bonding may be carried out to provide electrical coupling between a semiconductor die 50 and the respective leads 12 via bonding wires 54 .
  • the manufacturing method may comprise singulating the semiconductor devices 10 , e.g., by cutting or sawing along sawing lines, as conventional in the art.
  • the electrically conductive pads may comprise enlarged end portions (e.g., 44 ) extending at least partially over the package molding material, the enlarged end portions configured for coupling to a printed circuit board (e.g., 30 ).
  • the electrically conductive pads may comprise body portions (e.g., stem portions or web portions 12 ) embedded in the package molding material and the enlarged end portions may protrude from the package molding material.
  • a thickness (e.g., t) of the enlarged end portions may be in the range of 10 ⁇ m to 100 ⁇ m, preferably 50 ⁇ m to 70 ⁇ m.
  • a semiconductor device may comprise a metallic layer (e.g., 56 ) plated over the enlarged end portions.
  • the metallic layer may comprise tin.
  • a semiconductor device may comprise a quad-flat no-lead package or a land grid array package.

Abstract

A semiconductor device comprises at least one semiconductor die electrically coupled to a set of electrically conductive leads, and package molding material molded over the at least one semiconductor die and the electrically conductive leads. At least a portion of the electrically conductive leads is exposed at a rear surface of the package molding material to provide electrically conductive pads. The electrically conductive pads comprise enlarged end portions extending at least partially over the package molding material and configured for coupling to a printed circuit board.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of U.S. patent application Ser. No. 17/120,996, filed Dec. 14, 2020, now U.S. Pat. No. 11,749,588, which claims the priority benefit of Italian Application for Patent No. 102019000024259, filed on Dec. 17, 2019, the contents of which are hereby incorporated by reference in their entireties to the maximum extent allowable by law.
    • TECHNICAL FIELD
  • The description relates to manufacturing semiconductor devices.
  • One or more embodiments may be applied to manufacturing integrated circuits (ICs).
    • BACKGROUND
  • Semiconductor devices such as integrated circuits may be provided with packages of various types. For instance, quad-flat no-leads (QFN) packages and land grid array (LGA) packages are examples of surface-mount technology (SMT) packages known in the art.
  • QFN packages are near chip-scale plastic encapsulated packages provided with a planar leadframe substrate, wherein perimeter lands on the package rear (e.g., bottom) side are configured to provide electrical connections to a printed circuit board (PCB). The leads of the leadframe are thus fully incorporated in the package molding compound. QFN packages may include an exposed thermal pad to improve heat transfer out of the integrated circuit, into the printed circuit board.
  • LGA packages also have leads fully incorporated in the package molding compound, and comprise a (rectangular) grid of contacts on the bottom side of the package. The contacts on the package are configured to be coupled to a grid of contacts on the PCB.
  • Both QFN and LGA packages (as well as other SMT packages) do not have external leads, but rather have “lands” or “pads” that are directly couplable to the PCB pads for soldering by means of solder paste or solder alloy. The mounting (soldering) step may be complex and may result in a wide variability of welding strength and structure. Additionally, the different coefficients of thermal expansion between the package and the printed circuit board may lead to high stress in the solder material and/or to high thermal fatigue of QFN/LGA packages once mounted on a printed circuit board.
  • In this context, the use of “wettable flanks” is known in the art. Wettable flanks help increase wettability of the leads with the purpose of improving solder adhesion and overall welding strength by increasing the solder attachment area on the vertical side of the lands or pads. Wettable flanks may only slightly improve the solder joint reliability, and facilitate automatic optical inspection of the solder joint after the surface mounting process, for surface mount process control.
  • Packaged semiconductor devices providing improved solder joint reliability and/or stronger anchorage to the PCB are desirable.
  • There is a need in the art to contribute in providing packaged semiconductor devices, e.g., comprising a QFN- or LGA-type package, with improved solder joint reliability and/or stronger anchorage to the printed circuit board.
    • SUMMARY
  • One or more embodiments may relate to a semiconductor device (e.g., an integrated circuit).
  • One or more embodiments may relate to a corresponding method of manufacturing semiconductor devices.
  • One or more embodiments may provide a packaged semiconductor device (e.g., comprising a QFN or LGA package) comprising at least one semiconductor die electrically coupled to a set of electrically conductive leads, and package molding material molded over the at least one semiconductor die and the electrically conductive leads. At least a portion of the electrically conductive leads may be exposed at a rear surface of the package molding material to provide electrically conductive pads. The electrically conductive pads may comprise enlarged end portions extending at least partially over the package molding material and configured for coupling to a printed circuit board.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:
  • FIG. 1 is a perspective view exemplary of a semiconductor device comprising a QFN package, shown upside-down (i.e., with the rear side facing upwards);
  • FIG. 2 is a view of the rear side of the semiconductor device of FIG. 1 ;
  • FIG. 3A is a magnified view of a portion of the rear side of the semiconductor device of FIG. 2 ;
  • FIG. 3B is a side view of the portion of the semiconductor device of FIG. 3A mounted on a printed circuit board;
  • FIG. 4A is a magnified view of a portion of the rear side of a semiconductor device according to embodiments;
  • FIG. 4B is a side view of the portion of the semiconductor device of FIG. 4A mounted on a printed circuit board; and
  • FIGS. 5A to 5G are exemplary of steps of a method of manufacturing semiconductor devices according to embodiments.
    •  DETAILED DESCRIPTION
  • In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.
  • Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.
  • Throughout the figures annexed herein, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for brevity.
  • The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.
  • By way of introduction to the detailed description of exemplary embodiments, reference may be first had to FIGS. 1 and 2 , which are exemplary of a semiconductor device 10 comprising a QFN package.
  • While reference is made mainly to QFN packages in the present description and drawings for the sake of conciseness, one or more embodiments may be applied to other types of “leadless” packages, e.g., LGA packages.
  • As current in the art, together with other elements/features not visible in the Figures, a semiconductor device 10 as exemplified herein may comprise package molding material 100 encapsulating a semiconductor die (not visible in FIGS. 1 and 2 ), the molding material 100 being shaped to provide a rear (e.g., bottom) side 10A of the semiconductor device 10 configured for electrical and mechanical coupling to a printed circuit board.
  • A set of electrically conductive “lands” or “pads” 12 may be provided on the rear (or bottom) side 10A, e.g., at the periphery thereof, as illustrated in FIGS. 1 and 2 . Additionally or alternatively, the pads 12 may be arranged over the entire area of the rear side 10A, as customary in LGA packages. The pads 12 may be electrically coupled to the semiconductor die encapsulated in the molding material 100.
  • Optionally, the package may include an exposed thermal pad 14 on the rear side 10A. The thermal pad 14 may be thermally coupled to the semiconductor die encapsulated in the molding material 100 to improve heat transfer out of the integrated circuit 10.
  • Overall, the electrical pads 12 and the thermal pad 14 may provide the leadframe of the integrated circuit 10.
  • The (minimum) spacing between two adjacent pads 12 may be constrained by manufacturing constraints of the leadframe. Typically, the corresponding solder pads on a PCB may be wider and/or less spaced. For instance, FIG. 2 shows a bottom view of an exemplary integrated circuit 10 having electrical pads 12 and a thermal pad 14 (illustrated with solid lines), and a corresponding exemplary arrangement of solder pads 12′ and 14′ as may be present on a printed circuit board configured for coupling to the integrated circuit 10.
  • FIG. 3A is a magnified view exemplary of a portion of the rear side 10A of the integrated circuit 10, e.g., portion 20 illustrated in FIG. 2 . FIG. 3B is a corresponding side view of portion 20, exemplary of the integrated circuit 10 mounted on a printed circuit board by means of soldering material 32 interposed between the electrical pads 12 of the integrated circuit 10 and the respective solder pads 12′ on the PCB 30.
  • It is noted that, as a consequence of the spacing Do between pads 12 being (considerably) larger than the spacing d between pads 12′, electro-mechanical coupling of the integrated circuit to the PCB 30 may turn out to be unsatisfactory.
  • In one or more embodiments as exemplified in FIGS. 4A and 4B, reliability of such electro-mechanical coupling may be improved by increasing the area of the electrical pads 12 of the integrated circuit 10.
  • FIG. 4A is a magnified view exemplary of a portion 20 of the rear side 10A of an integrated circuit 10 according to one or more embodiments. FIG. 4B is a corresponding side view of portion 20, exemplary of the integrated circuit 10 mounted on a printed circuit board by means of soldering material 42.
  • As exemplified herein, a metallic layer may be selectively provided at the pads 12 after molding of the package material 100 to provide enlarged end portions 44 of the pads. The enlarged end portions 44 may thus partially extend over the molding material 100 at the interface between the pads 12 and the molding material 100 (e.g., “sidewise” of the body portion 12 of the pads which are embedded in the molding material), thereby increasing the area of the pads suitable for electrical and/or mechanical coupling to the soldering pads 12′.
  • Therefore, in one or more embodiments, a (thick) “pedestal” of metal material may be grown over the surface of the pads 12 and/or 14 left exposed by the molding material 100, thereby providing larger pads (i.e., providing a reduced spacing Dn between pads 12, which increase the soldering surface) and an increase of the standoff between the semiconductor package 100 and the printed circuit board 30. As a result, solder joint reliability may be improved and/or a stronger anchorage of the integrated circuit to the PCB may be obtained.
  • In one or more embodiments, the enlarged end portions 44 may be provided (e.g., grown) over the pads 12 and/or 14 after molding of the package material 100 by means of galvanic plating.
  • Providing the enlarged end portions 44 by galvanic plating may be advantageous insofar as it may facilitate growing the metal 44 (sidewise) over the molding compound 100 at the interface between the pads 12 and/or 14 and the molding compound 100, i.e., it may facilitate properly increasing the area of the pads (as exemplified in FIG. 4B).
  • Additionally or alternatively, any other selective metal deposition technique that would result in an isotropic growth of metal at the pads 12 and/or 14 may be used to form the enlarged portions 44.
  • In one or more embodiments, the thickness of the enlarged end portions 44 may be in the range of 10 μm to 100 μm, preferably 50 μm to 70 μm.
  • In one or more embodiments, the enlarged end portions 44 may extend (sidewise) over the molding compound 100 from the interface between the respective body portion of pad 12 and/or 14 and the molding compound 100 (see length Dp in FIG. 4B) for about 10 μm to 100 μm, preferably 50 μm to 70 μm.
  • In one or more embodiments, the enlarged end portions 44 may comprise at least one metal selected out of copper (Cu), nickel (Ni), palladium (Pd) and gold (Au). Preferably, the enlarged end portions 44 comprise copper (Cu).
  • In one or more embodiments, a further metallic layer may be provided over the enlarged end portions 44. For instance, the further metallic layer may comprise tin (Sn) plated over the enlarged end portions 44 at the pads 12 and/or 14.
  • One or more embodiments may provide improved reliability (e.g., longer life on board) over previous solutions, e.g., over solutions involving wettable flanks.
  • FIGS. 5A to 5G are exemplary of possible steps of a method of manufacturing semiconductor devices according to one or more embodiments. In FIGS. 5A-5G, manufacturing of a pair of semiconductor devices in exemplified.
  • As exemplified in FIG. 5A, an otherwise conventional leadframe may be provided as a first manufacturing step. For each semiconductor device, the leadframe may comprise a die pad 14 and respective leads 12.
  • As exemplified in FIG. 5B, at least one semiconductor die 50 may be mounted on each die pad 14 of the leadframe. For instance, the semiconductor dies 50 may be attached on the die pads 14 via die attach material 52, e.g., soft-solder die attach material and/or glue.
  • As exemplified in FIG. 5C, wire bonding may be carried out to provide electrical coupling between a semiconductor die 50 and the respective leads 12 via bonding wires 54.
  • As exemplified in FIG. 5D, package molding material 100 may be molded to encapsulate the semiconductor dies 50 and the leadframe, leaving exposed the electrical pads 12 and the thermal pads 14 at the rear side of the semiconductor devices.
  • As exemplified in FIG. 5E, a metallic layer 44 may be provided at the pads 12 and/or 14 after molding of the package material 100, thereby providing metallic “bumps” (the enlarged end portions) at the package leads. The enlarged end portions 44 may be grown, for instance, by galvanic plating. The thickness (t) of the enlarged end portions 44 may be in the range of 10 μm to 100 μm, preferably 50 μm to 70 μm. The lateral extension (Dp) of the enlarged end portions 44 may be in the range of 10 μm to 100 μm, preferably 50 μm to 70 μm. The enlarged end portions 44 may comprise one or more metals selected out of copper (Cu), nickel (Ni), palladium (Pd) and gold (Au).
  • As exemplified in FIG. 5F, a further metallic layer 56 may be provided over the metallic layer 44, e.g., by plating. The further metallic layer 56 may comprise tin (Sn).
  • As exemplified in FIG. 5G, the manufacturing method may comprise singulating the semiconductor devices 10, e.g., by cutting or sawing along sawing lines, as conventional in the art.
  • As exemplified herein, a semiconductor device (e.g., 10) may comprise: at least one semiconductor die (e.g., 50) electrically coupled (e.g., 54) to a set of electrically conductive leads; and package molding material (e.g., 100) molded over the at least one semiconductor die and the electrically conductive leads, wherein at least a portion of the electrically conductive leads is exposed at a rear surface (e.g., 10A) of the package molding material to provide electrically conductive pads (e.g., 12, 44).
  • As exemplified herein, the electrically conductive pads may comprise enlarged end portions (e.g., 44) extending at least partially over the package molding material, the enlarged end portions configured for coupling to a printed circuit board (e.g., 30).
  • As exemplified herein, the electrically conductive pads may comprise body portions (e.g., stem portions or web portions 12) embedded in the package molding material and the enlarged end portions may protrude from the package molding material.
  • As exemplified herein, the enlarged end portions may extend over the package molding material sidewise of said body portions for a length (e.g., Dp) of 10 μm to 100 μm, preferably 50 μm to 70 μm.
  • As exemplified herein, the enlarged end portions may comprise galvanic plating grown material.
  • As exemplified herein, the enlarged end portions may comprise at least one metal selected out of copper, nickel, palladium and gold, preferably copper.
  • As exemplified herein, a thickness (e.g., t) of the enlarged end portions may be in the range of 10 μm to 100 μm, preferably 50 μm to 70 μm.
  • As exemplified herein, a semiconductor device may comprise a metallic layer (e.g., 56) plated over the enlarged end portions. The metallic layer may comprise tin.
  • As exemplified herein, a semiconductor device may comprise a thermally conductive pad (e.g., 14). The thermally conductive pad may comprise a respective enlarged end portion extending at least partially over the package molding material and configured for coupling to a printed circuit board.
  • As exemplified herein, a semiconductor device may comprise a quad-flat no-lead package or a land grid array package.
  • As exemplified herein, a method may comprise: providing a leadframe comprising at least one die pad and at least one respective set of electrically conductive leads; mounting at least one semiconductor die onto the at least one die pad; electrically coupling the at least one semiconductor die to electrically conductive leads in the respective at least one set of electrically conductive leads; molding package molding material onto the at least one semiconductor die and the leadframe, the package molding material exposing at least a portion of the electrically conductive leads at a rear surface of the package molding material to provide electrically conductive pads; and providing enlarged end portions of the electrically conductive pads extending at least partially over the package molding material, the enlarged end portions configured for coupling to a printed circuit board.
  • Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.
  • The claims are an integral part of the technical teaching provided herein in respect of the embodiments.
  • The extent of protection is defined by the annexed claims.

Claims (22)

1. A semiconductor device, comprising:
a leadframe including a set of electrically conductive leads;
a semiconductor die electrically coupled to said set of electrically conductive leads; and
package molding material molded over the semiconductor die and the electrically conductive leads of the leadframe, wherein at least a portion of the electrically conductive leads is not covered by the package molding material;
electrically conductive pads at said portion of the electrically conductive leads which are not covered by the package molding material;
a plating layer on the electrically conductive pads that forms first enlarged end portions wherein said plating layer extends at least partially over a rear surface of the package molding material;
wherein the first enlarged end portions are configured for coupling to a printed circuit board.
2. The semiconductor device of claim 1, wherein the electrically conductive leads comprise body portions embedded in the package molding material and said plating layer forming the first enlarged end portions protrudes from the body portions at the rear surface of the package molding material.
3. The semiconductor device of claim 2, wherein the plating layer forming the first enlarged end portions extends over the rear surface of the package molding material sidewise of said body portions for a length of 10 μm to 100 μm.
4. The semiconductor device of claim 2, wherein the plating layer forming the first enlarged end portions extend over the rear surface of the package molding material sidewise of said body portions for a length of 50 μm to 70 μm.
5. The semiconductor device of claim 1, wherein said plating layer forming the first enlarged end portions comprises copper.
6. The semiconductor device of claim 1, wherein said plating layer forming the first enlarged end portions comprises at least one metal selected from the group consisting of: nickel, palladium and gold.
7. The semiconductor device of claim 1, wherein a thickness of the plating layer forming said first enlarged end portions is in a range of 10 μm to 100 μm.
8. The semiconductor device of claim 1, wherein a thickness of the plating layer forming said first enlarged end portions is in a range of 50 μm to 70 μm.
9. The semiconductor device of claim 1, further comprising a metallic layer plated over the plating layer forming said first enlarged end portions.
10. The semiconductor device of claim 9, wherein the metallic layer comprises tin.
11. The semiconductor device of claim 1, wherein said leadframe further comprises a thermally conductor to which the semiconductor die is mounted, wherein at least a portion of the thermally conductor that is not covered by the package molding material provides a thermally conductive pad; and wherein said plating layer is also present on the thermally conductive pad to form a second enlarged end portion extending at least partially over the rear surface of the package molding material.
12. The semiconductor device of claim 1, configured as a quad-flat no-lead package.
13. The semiconductor device of claim 1, configured as a land grid array package.
14. A semiconductor device, comprising:
a semiconductor die mounted to a thermally conductive pad and electrically coupled to a set of electrically conductive leads;
package molding material molded over the semiconductor die, the thermally conductive pad and the electrically conductive leads, wherein at least a portion of the thermally conductive pad is exposed at a rear surface of the package molding material; and
a plating layer on the thermally conductive pad forming an enlarged portion extending at least partially over the rear surface of the package molding material, wherein the enlarged portion is configured for coupling to a printed circuit board.
15. The semiconductor device of claim 14, wherein the thermally conductive pad comprises a body portion embedded in the package molding material and the plating layer forming said enlarged end portion protrudes from the rear surface of the package molding material.
16. The semiconductor device of claim 15, wherein the plating layer forming said enlarged end portion extends over the rear surface of the package molding material sidewise of said body portions for a length of 10 μm to 100 μm.
17. The semiconductor device of claim 15, wherein the plating layer forming said enlarged end portion extends over the rear surface of the package molding material sidewise of said body portions for a length of 50 μm to 70 μm.
18. The semiconductor device of claim 15, wherein the plating layer forming said enlarged end portion comprises at least one metal selected from the group consisting of: copper, nickel, palladium and gold.
19. The semiconductor device of claim 14, wherein a thickness of plating layer forming said enlarged end portion is in a range of 10 μm to 100 μm.
20. The semiconductor device of claim 14, wherein a thickness of the plating layer forming said enlarged end portion is in a range of 50 μm to 70 μm.
21. The semiconductor device of claim 14, further comprising a metallic layer plated over the plating layer forming said enlarged end portion.
22. The semiconductor device of claim 21, wherein the metallic layer comprises tin.
US18/241,414 2019-12-17 2023-09-01 Semiconductor device and corresponding method Pending US20230411258A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/241,414 US20230411258A1 (en) 2019-12-17 2023-09-01 Semiconductor device and corresponding method

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
IT102019000024259A IT201900024259A1 (en) 2019-12-17 2019-12-17 SEMICONDUCTOR DEVICE AND CORRESPONDING PROCEDURE
IT102019000024259 2019-12-17
US17/120,996 US11749588B2 (en) 2019-12-17 2020-12-14 Semiconductor device and corresponding method
US18/241,414 US20230411258A1 (en) 2019-12-17 2023-09-01 Semiconductor device and corresponding method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US17/120,996 Division US11749588B2 (en) 2019-12-17 2020-12-14 Semiconductor device and corresponding method

Publications (1)

Publication Number Publication Date
US20230411258A1 true US20230411258A1 (en) 2023-12-21

Family

ID=69904118

Family Applications (2)

Application Number Title Priority Date Filing Date
US17/120,996 Active 2041-08-05 US11749588B2 (en) 2019-12-17 2020-12-14 Semiconductor device and corresponding method
US18/241,414 Pending US20230411258A1 (en) 2019-12-17 2023-09-01 Semiconductor device and corresponding method

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US17/120,996 Active 2041-08-05 US11749588B2 (en) 2019-12-17 2020-12-14 Semiconductor device and corresponding method

Country Status (4)

Country Link
US (2) US11749588B2 (en)
EP (1) EP3840039A1 (en)
CN (2) CN215220709U (en)
IT (1) IT201900024259A1 (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1187602A (en) * 1997-09-09 1999-03-30 Sony Corp Semiconductor device and its manufacture
US8502357B2 (en) * 2009-10-01 2013-08-06 Stats Chippac Ltd. Integrated circuit packaging system with shaped lead and method of manufacture thereof
JP5287899B2 (en) * 2011-02-23 2013-09-11 凸版印刷株式会社 Lead frame for semiconductor light emitting device and manufacturing method thereof
US10236265B2 (en) * 2014-07-28 2019-03-19 Infineon Technologies Ag Semiconductor chip and method for forming a chip pad
JP6555927B2 (en) * 2015-05-18 2019-08-07 大口マテリアル株式会社 Semiconductor device mounting lead frame and semiconductor device manufacturing method
JP6476494B2 (en) * 2015-08-28 2019-03-06 Ｓｈマテリアル株式会社 Lead frame, semiconductor device, and manufacturing method thereof

Also Published As

Publication number Publication date
IT201900024259A1 (en) 2021-06-17
EP3840039A1 (en) 2021-06-23
CN215220709U (en) 2021-12-17
US20210183752A1 (en) 2021-06-17
US11749588B2 (en) 2023-09-05
CN112992838A (en) 2021-06-18

Similar Documents

Publication Publication Date Title
US8685795B2 (en) Flank wettable semiconductor device
US20030067057A1 (en) Lead frame and flip chip semiconductor package with the same
US7256481B2 (en) Leadframes for improved moisture reliability and enhanced solderability of semiconductor devices
TWI322493B (en) Leadframe strip, semiconductor device, and the method of fabricating a leadframe
US20030089981A1 (en) Semiconductor package having stacked dice and leadframes and method of fabrication
US20070269932A1 (en) Semiconductor Device Having Post-Mold Nickel/Palladium/Gold Plated Leads
US9184148B2 (en) Semiconductor package and method therefor
KR20050071524A (en) Thermal enhanced package for block mold assembly
KR19980054344A (en) Surface-Mount Semiconductor Packages and Manufacturing Method Thereof
US20230187223A1 (en) Semiconductor package with flip chip solder joint capsules
US9553068B2 (en) Integrated circuit (“IC”) assembly includes an IC die with a top metallization layer and a conductive epoxy layer applied to the top metallization layer
KR100804341B1 (en) A semiconductor device and method of manufacturing the same
US20210265214A1 (en) Methods and apparatus for an improved integrated circuit package
US20020117740A1 (en) Lead frame for plastic molded type semiconductor package
US20230057405A1 (en) QFN Device Having A Mechanism That Enables An Inspectable Solder Joint When Attached To A PWB And Method Of Making Same
EP3319122B1 (en) Semiconductor device with wettable corner leads
US20230411258A1 (en) Semiconductor device and corresponding method
US20200321228A1 (en) Method of manufacturing a lead frame, method of manufacturing an electronic apparatus, and electronic apparatus
US20190067033A1 (en) Surface Mount Semiconductor Device and Method of Manufacture
US11227820B2 (en) Through hole side wettable flank
JP2004335947A (en) Semiconductor device and formation method thereof
JPH0228356A (en) Surface mounting type semiconductor device and its manufacture
JP2000150761A (en) Resin sealed semiconductor device and its manufacture
JP2005235927A (en) Semiconductor apparatus and its manufacturing method
JPH04245670A (en) Lead frame and manufacture of semiconductor device using the same