JP2010109234A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2010109234A JP2010109234A JP2008281171A JP2008281171A JP2010109234A JP 2010109234 A JP2010109234 A JP 2010109234A JP 2008281171 A JP2008281171 A JP 2008281171A JP 2008281171 A JP2008281171 A JP 2008281171A JP 2010109234 A JP2010109234 A JP 2010109234A
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Abstract
【解決手段】リードフレームは、ダイパッドと、ダイパッドを支持する吊リードSLとを有する。接合部JPはリードフレーム上に設けられている。第1の半導体チップC1は接合部JPを介してリードフレーム上に設けられている。第2の半導体チップC2は第1の半導体チップC1上に設けられている。樹脂部材はダイパッドと第1および第2の半導体素子C1、C2とを覆っている。接合部JPはダイパッドおよび吊リードSLの各々の上に位置している。
【選択図】図10
Description
(実施の形態1)
図1は、本発明の実施の形態1における半導体装置の構成を概略的に示す平面図である。また図2は、図1の中央部の概略拡大図である。また図3は、図1の線III−IIIに沿った概略断面図である。また図4は、図2の線IV−IVに沿った概略断面図である。なお図1においては、樹脂部材はその外縁のみが二点鎖線で示されている。
次に比較例における半導体装置の製造方法について説明する。図12は、比較例における半導体装置の製造方法の一工程を概略的に示す概略断面図である。
図13は、本発明の実施の形態2における半導体装置の構成を概略的に示す断面図である。また図14は、本発明の実施の形態2における半導体装置の製造方法の一工程を示す概略的な部分平面図である。なお図13および図14のそれぞれにより示される範囲は、実施の形態1の図3および図10により示される範囲に対応している。
図15は、本発明の実施の形態3における半導体装置の構成を概略的に示す部分断面図である。また図16〜図20のそれぞれは、本発明の実施の形態3における半導体装置の製造方法の第1〜第5工程を概略的に示す部分平面図である。なお図15により示される範囲は、実施の形態1の図4により示される範囲に対応している。また図16〜図20のそれぞれにより示される範囲は、実施の形態1の図6〜図10により示される範囲に対応している。
Claims (5)
- ダイパッドと、前記ダイパッドを支持する吊リードとを有するリードフレームと、
前記リードフレーム上に設けられた接合部と、
前記接合部を介して前記リードフレーム上に設けられた第1の半導体チップと、
前記第1の半導体チップ上に設けられた第2の半導体チップと、
前記ダイパッドと前記第1および第2の半導体素子とを覆う樹脂部材とを備え、
前記接合部は前記ダイパッドおよび前記吊リードの各々の上に位置する、半導体装置。 - 前記吊リードは、前記接合部の前記ダイパッド上に位置する部分と前記接合部の前記吊リード上に位置する部分との間に貫通穴を有する、請求項1に記載の半導体装置。
- ダイパッドと、前記ダイパッドを支持する吊リードとを有するリードフレームと、
前記リードフレーム上に設けられた接合部と、
前記接合部を介して前記リードフレーム上に設けられ、平面視において、第1の中心線を有し、かつ前記ダイパッドと前記吊リードの一部とに重なるように配置された第1の半導体チップと、
前記第1の半導体チップ上に設けられ、平面視において、前記第1の中心線と平行であり、かつ前記第1の中心線の一の側に位置する第2の中心線を有する第2の半導体チップと、
前記ダイパッドと前記第1および第2の半導体素子とを覆う樹脂部材とを備え、
前記接合部は平面視において前記第2の中心線の両側に位置する、半導体装置。 - 前記第2の半導体素子は平面視において前記第1の中心線の前記一の側に位置する、請求項3に記載の半導体装置。
- 前記接合部材は硬化された樹脂からなる、請求項1〜4のいずれかに記載の半導体装置。
Priority Applications (2)
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JP2008281171A JP2010109234A (ja) | 2008-10-31 | 2008-10-31 | 半導体装置 |
US12/604,385 US20100109148A1 (en) | 2008-10-31 | 2009-10-22 | Semiconductor device |
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JP2008281171A JP2010109234A (ja) | 2008-10-31 | 2008-10-31 | 半導体装置 |
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JP2008281171A Pending JP2010109234A (ja) | 2008-10-31 | 2008-10-31 | 半導体装置 |
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Citations (6)
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JPH08236685A (ja) * | 1994-12-14 | 1996-09-13 | Anam Ind Co Inc | 半導体パッケージのリードフレーム構造 |
JP2000049272A (ja) * | 1998-07-31 | 2000-02-18 | Hitachi Ltd | リードフレーム及びそれを用いた半導体装置の製造方法並びに半導体装置 |
JP2002124626A (ja) * | 2000-10-16 | 2002-04-26 | Hitachi Ltd | 半導体装置 |
JP2004312053A (ja) * | 2004-08-09 | 2004-11-04 | Renesas Technology Corp | 半導体装置 |
JP2008034696A (ja) * | 2006-07-31 | 2008-02-14 | Mitsumi Electric Co Ltd | 半導体集積回路装置および不揮発性メモリ装置 |
WO2008114374A1 (ja) * | 2007-03-19 | 2008-09-25 | Renesas Technology Corp. | 半導体装置及びその製造方法 |
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KR100552353B1 (ko) * | 1992-03-27 | 2006-06-20 | 가부시키가이샤 히타치초엘에스아이시스템즈 | 리이드프레임및그것을사용한반도체집적회로장치와그제조방법 |
US6448633B1 (en) * | 1998-11-20 | 2002-09-10 | Amkor Technology, Inc. | Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant |
US7719122B2 (en) * | 2007-01-11 | 2010-05-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | System-in-package packaging for minimizing bond wire contamination and yield loss |
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2008
- 2008-10-31 JP JP2008281171A patent/JP2010109234A/ja active Pending
-
2009
- 2009-10-22 US US12/604,385 patent/US20100109148A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH08236685A (ja) * | 1994-12-14 | 1996-09-13 | Anam Ind Co Inc | 半導体パッケージのリードフレーム構造 |
JP2000049272A (ja) * | 1998-07-31 | 2000-02-18 | Hitachi Ltd | リードフレーム及びそれを用いた半導体装置の製造方法並びに半導体装置 |
JP2002124626A (ja) * | 2000-10-16 | 2002-04-26 | Hitachi Ltd | 半導体装置 |
JP2004312053A (ja) * | 2004-08-09 | 2004-11-04 | Renesas Technology Corp | 半導体装置 |
JP2008034696A (ja) * | 2006-07-31 | 2008-02-14 | Mitsumi Electric Co Ltd | 半導体集積回路装置および不揮発性メモリ装置 |
WO2008114374A1 (ja) * | 2007-03-19 | 2008-09-25 | Renesas Technology Corp. | 半導体装置及びその製造方法 |
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