JP2008034696A - 半導体集積回路装置および不揮発性メモリ装置 - Google Patents
半導体集積回路装置および不揮発性メモリ装置 Download PDFInfo
- Publication number
- JP2008034696A JP2008034696A JP2006207902A JP2006207902A JP2008034696A JP 2008034696 A JP2008034696 A JP 2008034696A JP 2006207902 A JP2006207902 A JP 2006207902A JP 2006207902 A JP2006207902 A JP 2006207902A JP 2008034696 A JP2008034696 A JP 2008034696A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- voltage
- terminal
- microcontroller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
【解決手段】 1つの配線基板(51)上に、第1の電圧で電気的にデータを書込み可能な不揮発性メモリ装置(15B)と、第1の電圧よりも低い第2の電圧で動作する半導体集積回路基板(10E)とが搭載された半導体集積回路装置(20E)において、不揮発性メモリ装置は、第1の電圧が供給される第1の端子(15−3)と第2の電圧を出力する第2の端子(15−4)とを持ち、半導体集積回路基板(10E)は、第2の端子と電気的に接続された第3の端子(RES#)を持つ。不揮発性メモリ装置(15B)は、第1の端子と第2の端子との間に設けられて、第1の電圧を第2の電圧に変換する電圧変換回路を有する。不揮発性メモリ装置(15B)は、半導体集積回路基板(10E)上に積層されている。
【選択図】 図22
Description
一方、上記特許文献1、2に開示されているように、最終製品として、1つの半導体チップではなく、2つの半導体チップを積層して1つの樹脂封止体で封止したマイクロコントローラを製造することも考えられる。しかしながら、上述したように、EEPROM(フラッシュメモリ)はマスクROMに比べて非常に高価であるので、マイクロコントローラを大量生産する場合には不向きである。
ユーザでは、図4に示されるように、半導体メーカから提供された複数の仮のマイクロコントローラ20の中の1つに対して、EPROMプログラマ(ライタ)22を使用して、仮のプログラム(すなわち、ソフトエミュレータを使用してデバッグされたプログラム)をプログラマブルROM(OTP)15に記憶する。詳述すると、EPROMプログラマ(ライタ)22にアドレス、データ他の信号線24を介して接続されたICソケット26に、1個の仮のマイクロコントローラ20を差し込んで、EPROMプログラマ(ライタ)22から信号線24及びICソケット26を介して仮のプログラムを転送することにより、仮のプログラムをプログラマブルROM(OTP)15に記憶する。
10−1 ベース用ボンディングパッド(基板接続端子)
11 マスクROM
11A マスクROM領域
12 その他の集積回路
121 CPU
122 RAM
123 周辺回路(入出力制御LSI)
13 内部バス
132 内部アドレスバス
132−1 内部アドレス用ボンディングパッド(バス接続端子)
134 内部データバス
134−1 内部データ用ボンディングパッド(バス接続端子)
15、15A、15B プログラマブルROM(OTP)
15−1 アドレス用ボンディングパッド(ROM接続端子)
15A−1 アドレス用バンプ(ROM接続端子)
15−2 データ用ボンディングパッド(ROM接続端子)
15A−2 データ用バンプ(ROM接続端子)
15−3 電源用ボンディングパッド(電源供給端子)
15−4 リセット出力端子
151 EPROM本体
152 高耐圧用入力バッファ
152−1 第1のC−MOSインバータ
152−1N 第1のnチャネルFET
152−1P 第1のpチャネルFET
152−2 第2のC−MOSインバータ
152−2N 第2のnチャネルFET
152−2P 第2のpチャネルFET
153 電流増幅用バッファ
17 半導体パッケージ
18 電源線
19 制御信号線
20、20A、20B、20C、20D、20E 第1の半導体集積回路装置(第1のマイクロコントローラ)
22 EPROMプログラマ(ライタ)
24 アドレス、データ他の信号線
26 ICソケット
28 評価用基板(ターゲットボード)
30 アドレス、データ他の信号線
32 インサーキットエミュレータ
40 マスクROMのメモリセル
41 P型基板
42 ソース(N+領域)
43 ドレイン(N+領域)
44 絶縁酸化膜
45 ゲート(金属電極)
46 高濃度不純物領域
51 リードフレーム(ダイパッド、配線基板)
52 ダイスボンド材
53 ダイスボンド材
55 リード(外部接続端子、パッケージピン)
55−1 電源用ボンディングパッド(電源/リセット用ボンディングパッド)
57 Alマスタスライス
61、62、63、65 ボンディングワイヤ
70 パッド専用配線層
71 メタル層間膜
72、73 コンタクトホール
74 パッシベーション膜
80 プログラマブルROMのメモリセル
81 P型基板
82 ソース(N領域)
83 ドレイン(N領域)
85 フローティングゲート
87 コントロールゲート
100 第2の半導体集積回路基板(第2のマイクロコントローラ基板)
110 第2のマスクROM
120 その他の集積回路
130 第2の内部バス
141 内部アドレス用パッド領域
142 内部データ用パッド領域
200 第2の半導体集積回路装置(第2のマイクロコントローラ)
VPP 電源供給端子
RES# リセット端子(リセット出力端子、リセット入力端子)
VPP/RES# 電源供給/リセット端子
Claims (10)
- 1つの配線基板上に、第1の電圧で電気的にデータを書込み可能な不揮発性メモリ装置と、前記第1の電圧よりも低い第2の電圧で動作する半導体集積回路基板とが搭載された半導体集積回路装置であって、前記不揮発性メモリ装置は前記第1の電圧が供給される第1の端子を持つ、前記半導体集積回路装置において、
前記不揮発性メモリ装置は、前記第2の電圧を出力する第2の端子を持ち、
前記半導体集積回路基板は、前記第2の端子と電気的に接続された第3の端子を持つ、ことを特徴とする半導体集積回路装置。 - 前記不揮発性メモリ装置は、前記第1の端子と前記第2の端子との間に設けられて、前記第1の電圧を前記第2の電圧に変換する電圧変換回路を有することを特徴とする請求項1記載の半導体集積回路装置。
- 前記不揮発性メモリ装置へのデータの書込み時には、前記第1の端子に前記第1の電圧が印加され、前記半導体集積回路基板の動作時には、前記第1の端子に前記第2の電圧が印加されることを特徴とする請求項1又は2に記載の半導体集積回路装置。
- 前記不揮発性メモリ装置は、前記半導体集積回路基板上に積層されていることを特徴とする請求項1乃至3のいずれか1つに記載の半導体集積回路装置。
- 前記不揮発性メモリ装置と前記半導体集積回路基板とは、前記配線基板上の同一平面上に搭載されていることを特徴とする請求項1乃至4のいずれか1つに記載の半導体集積回路装置。
- 前記配線基板は、複数の外部導出リードを持つリードフレームであることを特徴とする請求項4又は5に記載の半導体集積回路装置。
- 前記第2の端子と前記第3の端子とは、ワイヤボンディング技術によって電気的接続がなされることを特徴とする請求項4乃至6のいずれか1つに記載の半導体集積回路装置。
- 請求項1乃至7のいずれか1つに記載の半導体集積回路装置を搭載してなる電子装置。
- 第1の電圧が供給される第1の端子を持ち、前記第1の電圧によって電気的にデータを書込み可能な不揮発性メモリ装置において、
前記第1の電圧よりも低い第2の電圧を出力するための第2の端子を持ち、
前記第1の端子と前記第2の端子との間に設けられて、前記第1の電圧を前記第2の電圧に変換する電圧変換回路を有することを特徴とする不揮発性メモリ装置。 - 前記第1の端子から前記不揮発性メモリ装置の内部に延在している電源配線と、該電源配線から分岐した特定の配線とを持ち、
前記特定の配線は、前記電圧変換回路を介して前記第2の端子に接続されていることを特徴とする請求項9に記載の不揮発性メモリ装置。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006207902A JP5110247B2 (ja) | 2006-07-31 | 2006-07-31 | 半導体集積回路装置 |
TW096118960A TW200807700A (en) | 2006-07-31 | 2007-05-28 | Semiconductor integrated circuit device including nonvolatile memory device |
TW100103427A TW201123434A (en) | 2006-07-31 | 2007-05-28 | Semiconductor integrated circuit device, nonvolatile memory device and electronic device |
KR1020070058237A KR100881624B1 (ko) | 2006-07-31 | 2007-06-14 | 반도체 집적회로 장치 및 불휘발성 메모리 장치 |
US11/881,227 US8046599B2 (en) | 2006-07-31 | 2007-07-26 | Semiconductor integrated circuit device including semiconductor integrated circuit board supplied with no high voltage |
KR1020080109005A KR100895685B1 (ko) | 2006-07-31 | 2008-11-04 | 반도체 집적회로 장치, 불휘발성 메모리 장치 및 전자 장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006207902A JP5110247B2 (ja) | 2006-07-31 | 2006-07-31 | 半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008034696A true JP2008034696A (ja) | 2008-02-14 |
JP5110247B2 JP5110247B2 (ja) | 2012-12-26 |
Family
ID=39113225
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006207902A Expired - Fee Related JP5110247B2 (ja) | 2006-07-31 | 2006-07-31 | 半導体集積回路装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8046599B2 (ja) |
JP (1) | JP5110247B2 (ja) |
KR (2) | KR100881624B1 (ja) |
TW (2) | TW200807700A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010109234A (ja) * | 2008-10-31 | 2010-05-13 | Renesas Technology Corp | 半導体装置 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5080762B2 (ja) | 2006-07-31 | 2012-11-21 | ミツミ電機株式会社 | 半導体集積回路装置 |
JP2008033724A (ja) * | 2006-07-31 | 2008-02-14 | Mitsumi Electric Co Ltd | シングル・チップ半導体集積回路装置の製造方法、プログラムデバッグ方法、マイクロコントローラの製造方法 |
JP5646415B2 (ja) * | 2011-08-31 | 2014-12-24 | 株式会社東芝 | 半導体パッケージ |
JP5906931B2 (ja) * | 2012-05-08 | 2016-04-20 | 凸版印刷株式会社 | 半導体集積回路 |
US9391032B2 (en) * | 2013-11-27 | 2016-07-12 | Samsung Electronics Co., Ltd. | Integrated circuits with internal pads |
KR20190075722A (ko) | 2017-12-21 | 2019-07-01 | (주)바이트소프트웨어 | 여러 참여자들의 협업을 통한 디지털 저작물 제작 및 수익 분배 방법 및 시스템 |
CN109215719B (zh) * | 2018-11-22 | 2023-08-25 | 四川知微传感技术有限公司 | 一种用于otp编程的多功能电压切换电路 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06259617A (ja) * | 1993-03-08 | 1994-09-16 | Sharp Corp | Icカード |
JPH0944467A (ja) * | 1995-07-27 | 1997-02-14 | Sharp Corp | マイクロコンピュータ |
JP2001051903A (ja) * | 1999-08-05 | 2001-02-23 | Sony Corp | 半導体記憶装置及び半導体記憶装置の動作設定方法 |
JP2002124626A (ja) * | 2000-10-16 | 2002-04-26 | Hitachi Ltd | 半導体装置 |
JP2005159111A (ja) * | 2003-11-27 | 2005-06-16 | Matsushita Electric Ind Co Ltd | マルチチップ型半導体装置 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57124463A (en) * | 1981-01-26 | 1982-08-03 | Nec Corp | Semiconductor device |
US5606710A (en) * | 1994-12-20 | 1997-02-25 | National Semiconductor Corporation | Multiple chip package processor having feed through paths on one die |
JPH09152979A (ja) | 1995-09-28 | 1997-06-10 | Matsushita Electric Ind Co Ltd | 半導体装置 |
US5594686A (en) * | 1995-12-29 | 1997-01-14 | Intel Corporation | Method and apparatus for protecting data stored in flash memory |
KR19990071743A (ko) | 1996-10-01 | 1999-09-27 | 씨. 필립 채프맨 | 고전압레벨시프팅cmos버퍼 |
US6512401B2 (en) * | 1999-09-10 | 2003-01-28 | Intel Corporation | Output buffer for high and low voltage bus |
JP3737333B2 (ja) * | 2000-03-17 | 2006-01-18 | 沖電気工業株式会社 | 半導体装置 |
JP2002076248A (ja) * | 2000-08-29 | 2002-03-15 | Oki Micro Design Co Ltd | マルチチップパッケージ |
JP2002231882A (ja) * | 2001-02-06 | 2002-08-16 | Mitsubishi Electric Corp | 半導体装置 |
JP2003141097A (ja) | 2001-11-01 | 2003-05-16 | Matsushita Electric Ind Co Ltd | 不揮発性ワンチップマイクロコンピュータ |
US6720210B1 (en) * | 2002-10-17 | 2004-04-13 | Macronix International Co., Ltd | Mask ROM structure and manufacturing method thereof |
KR100541655B1 (ko) * | 2004-01-07 | 2006-01-11 | 삼성전자주식회사 | 패키지 회로기판 및 이를 이용한 패키지 |
CN1918581A (zh) * | 2004-02-20 | 2007-02-21 | 株式会社瑞萨科技 | Ic卡及其制造方法 |
JP2008033724A (ja) * | 2006-07-31 | 2008-02-14 | Mitsumi Electric Co Ltd | シングル・チップ半導体集積回路装置の製造方法、プログラムデバッグ方法、マイクロコントローラの製造方法 |
JP5080762B2 (ja) * | 2006-07-31 | 2012-11-21 | ミツミ電機株式会社 | 半導体集積回路装置 |
-
2006
- 2006-07-31 JP JP2006207902A patent/JP5110247B2/ja not_active Expired - Fee Related
-
2007
- 2007-05-28 TW TW096118960A patent/TW200807700A/zh not_active IP Right Cessation
- 2007-05-28 TW TW100103427A patent/TW201123434A/zh not_active IP Right Cessation
- 2007-06-14 KR KR1020070058237A patent/KR100881624B1/ko not_active IP Right Cessation
- 2007-07-26 US US11/881,227 patent/US8046599B2/en not_active Expired - Fee Related
-
2008
- 2008-11-04 KR KR1020080109005A patent/KR100895685B1/ko not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06259617A (ja) * | 1993-03-08 | 1994-09-16 | Sharp Corp | Icカード |
JPH0944467A (ja) * | 1995-07-27 | 1997-02-14 | Sharp Corp | マイクロコンピュータ |
JP2001051903A (ja) * | 1999-08-05 | 2001-02-23 | Sony Corp | 半導体記憶装置及び半導体記憶装置の動作設定方法 |
JP2002124626A (ja) * | 2000-10-16 | 2002-04-26 | Hitachi Ltd | 半導体装置 |
JP2005159111A (ja) * | 2003-11-27 | 2005-06-16 | Matsushita Electric Ind Co Ltd | マルチチップ型半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010109234A (ja) * | 2008-10-31 | 2010-05-13 | Renesas Technology Corp | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
KR100895685B1 (ko) | 2009-04-30 |
US20080049483A1 (en) | 2008-02-28 |
TW201123434A (en) | 2011-07-01 |
JP5110247B2 (ja) | 2012-12-26 |
US8046599B2 (en) | 2011-10-25 |
TW200807700A (en) | 2008-02-01 |
KR100881624B1 (ko) | 2009-02-04 |
KR20080012135A (ko) | 2008-02-11 |
TWI360221B (ja) | 2012-03-11 |
KR20080113319A (ko) | 2008-12-30 |
TWI374538B (ja) | 2012-10-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100856438B1 (ko) | 싱글·칩 반도체 집적회로 장치의 제조방법, 프로그램디버그 방법, 마이크로 컨트롤러의 제조방법 | |
JP5110247B2 (ja) | 半導体集積回路装置 | |
US7177171B2 (en) | Semiconductor device | |
JP5080762B2 (ja) | 半導体集積回路装置 | |
JP3737333B2 (ja) | 半導体装置 | |
JPH09152979A (ja) | 半導体装置 | |
JP5293940B2 (ja) | 半導体集積回路装置およびその試験方法 | |
JP2006351664A (ja) | 半導体装置 | |
JP5311078B2 (ja) | 半導体集積回路装置およびその製造方法 | |
JP5234298B2 (ja) | シングル・チップ半導体集積回路装置の製造方法、プログラムデバッグ方法、マイクロコントローラの製造方法 | |
JP4093259B2 (ja) | 半導体装置 | |
JP3981126B2 (ja) | 半導体装置の製造方法 | |
JP4392482B2 (ja) | 半導体装置 | |
JP3981060B2 (ja) | 半導体装置 | |
JP2004007017A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090323 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120418 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120419 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120530 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120711 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120731 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120912 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120925 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151019 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |