JP5080762B2 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
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- JP5080762B2 JP5080762B2 JP2006207826A JP2006207826A JP5080762B2 JP 5080762 B2 JP5080762 B2 JP 5080762B2 JP 2006207826 A JP2006207826 A JP 2006207826A JP 2006207826 A JP2006207826 A JP 2006207826A JP 5080762 B2 JP5080762 B2 JP 5080762B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Microcomputers (AREA)
- Wire Bonding (AREA)
Description
一方、上記特許文献1、2に開示されているように、最終製品として、1つの半導体チップではなく、2つの半導体チップを積層して1つの樹脂封止体で封止したマイクロコントローラを製造することも考えられる。しかしながら、上述したように、EEPROM(フラッシュメモリ)はマスクROMに比べて非常に高価であるので、マイクロコントローラを大量生産する場合には不向きである。
ユーザでは、図4に示されるように、半導体メーカから提供された複数の仮のマイクロコントローラ20の中の1つに対して、EPROMプログラマ(ライタ)22を使用して、仮のプログラム(すなわち、ソフトエミュレータを使用してデバッグされたプログラム)をプログラマブルROM(OTP)15に記憶する。詳述すると、EPROMプログラマ(ライタ)22にアドレス、データ他の信号線24を介して接続されたICソケット26に、1個の仮のマイクロコントローラ20を差し込んで、EPROMプログラマ(ライタ)22から信号線24及びICソケット26を介して仮のプログラムを転送することにより、仮のプログラムをプログラマブルROM(OTP)15に記憶する。
10−1 ベース用ボンディングパッド(基板接続端子)
11 マスクROM
11A マスクROM領域
12 その他の集積回路
121 CPU
122 RAM
123 周辺回路(入出力制御LSI)
13 内部バス
132 内部アドレスバス
132−1 内部アドレス用ボンディングパッド(バス接続端子)
134 内部データバス
134−1 内部データ用ボンディングパッド(バス接続端子)
15、15A、15B プログラマブルROM(OTP)
15−1 アドレス用ボンディングパッド(ROM接続端子)
15A−1 アドレス用バンプ(ROM接続端子)
15−2 データ用ボンディングパッド(ROM接続端子)
15A−2 データ用バンプ(ROM接続端子)
15−3 電源用ボンディングパッド(電源供給端子)
15−4 リセット出力端子
151 EPROM本体
152 高耐圧用入力バッファ
152−1 第1のC−MOSインバータ
152−1N 第1のnチャネルFET
152−1P 第1のpチャネルFET
152−2 第2のC−MOSインバータ
152−2N 第2のnチャネルFET
152−2P 第2のpチャネルFET
153 電流増幅用バッファ
17 半導体パッケージ
18 電源線
19 制御信号線
20、20A、20B、20C、20D、20E 第1の半導体集積回路装置(第1のマイクロコントローラ)
22 EPROMプログラマ(ライタ)
24 アドレス、データ他の信号線
26 ICソケット
28 評価用基板(ターゲットボード)
30 アドレス、データ他の信号線
32 インサーキットエミュレータ
40 マスクROMのメモリセル
41 P型基板
42 ソース(N+領域)
43 ドレイン(N+領域)
44 絶縁酸化膜
45 ゲート(金属電極)
46 高濃度不純物領域
51 リードフレーム(ダイパッド、配線基板)
52 ダイスボンド材
53 ダイスボンド材
55 リード(外部接続端子、パッケージピン)
55−1 電源用ボンディングパッド(電源/リセット用ボンディングパッド)
57 Alマスタスライス
61、62、63、65 ボンディングワイヤ
70 パッド専用配線層
71 メタル層間膜
72、73 コンタクトホール
74 パッシベーション膜
80 プログラマブルROMのメモリセル
81 P型基板
82 ソース(N領域)
83 ドレイン(N領域)
85 フローティングゲート
87 コントロールゲート
100 第2の半導体集積回路基板(第2のマイクロコントローラ基板)
110 第2のマスクROM
120 その他の集積回路
130 第2の内部バス
141 内部アドレス用パッド領域
142 内部データ用パッド領域
200 第2の半導体集積回路装置(第2のマイクロコントローラ)
VPP 電源供給端子
RES# リセット端子(リセット出力端子、リセット入力端子)
VPP/RES# 電源供給/リセット端子
Claims (6)
- 複数の外部導出配線と、
プログラムが記憶されていないマスクROMが形成されるべきマスクROM領域、複数の機能回路が接続されてなる内部バス、前記内部バスに接続された複数のバス接続端子、及び複数の外部接続端子を持つ半導体集積回路基板と、
前記半導体集積回路基板上に積層され、複数のROM接続端子を持つプログラマブルROMとを有し、
前記複数の外部接続端子と前記複数の外部導出配線とが電気的に接続され、
前記マスクROMが前記内部バスと電気的に切り離されており、
前記複数のROM接続端子と前記複数のバス接続端子とがワイヤボンディング又はフェイスダウンボンディングによりそれぞれ直接電気的に接続されてなる、ことを特徴とする半導体集積回路装置。 - 前記複数の機能回路は、CPUとRAMと入出力制御LSIとから成ることを特徴とする請求項1記載の半導体集積回路装置。
- 前記複数のバス接続端子が、前記半導体集積回路基板の外周に設けられていることを特徴とする請求項1記載の半導体集積回路装置。
- 前記複数のバス接続端子が、前記マスクROM領域上に設けられていることを特徴とする請求項1に記載の半導体集積回路装置。
- 前記複数のバス接続端子が、前記内部バス上に設けられていることを特徴とする請求項1に記載の半導体集積回路装置。
- 前記複数のバス接続端子は、前記半導体集積回路基板上で、前記複数のROM接続端子の配置のミラー反転配置で設けられていることを特徴とする請求項1に記載の半導体集積回路装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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JP2006207826A JP5080762B2 (ja) | 2006-07-31 | 2006-07-31 | 半導体集積回路装置 |
TW96118958A TWI400786B (zh) | 2006-07-31 | 2007-05-28 | Semiconductor integrated circuit device |
KR20070056027A KR100881929B1 (ko) | 2006-07-31 | 2007-06-08 | 반도체 집적회로 장치 |
US11/881,224 US7576420B2 (en) | 2006-07-31 | 2007-07-26 | Semiconductor integrated circuit device having reduced terminals and I/O area |
KR1020080114072A KR100895683B1 (ko) | 2006-07-31 | 2008-11-17 | 반도체 집적회로 장치, 반도체 집적회로 장치의 제조방법 및 반도체 집적회로 장치에 프로그램을 기억하는 방법 |
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JP2006207826A JP5080762B2 (ja) | 2006-07-31 | 2006-07-31 | 半導体集積回路装置 |
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JP2011085031A Division JP5311078B2 (ja) | 2011-04-07 | 2011-04-07 | 半導体集積回路装置およびその製造方法 |
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JP2008034690A JP2008034690A (ja) | 2008-02-14 |
JP5080762B2 true JP5080762B2 (ja) | 2012-11-21 |
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US (1) | US7576420B2 (ja) |
JP (1) | JP5080762B2 (ja) |
KR (2) | KR100881929B1 (ja) |
TW (1) | TWI400786B (ja) |
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KR20030001462A (ko) * | 2000-05-01 | 2003-01-06 | 씨에프피에이치, 엘. 엘. 씨. | 이벤트 결과에 대한 실시간 대화식 베팅 |
JP5110247B2 (ja) * | 2006-07-31 | 2012-12-26 | ミツミ電機株式会社 | 半導体集積回路装置 |
JP2008033724A (ja) * | 2006-07-31 | 2008-02-14 | Mitsumi Electric Co Ltd | シングル・チップ半導体集積回路装置の製造方法、プログラムデバッグ方法、マイクロコントローラの製造方法 |
US8451014B2 (en) * | 2009-09-09 | 2013-05-28 | Advanced Micro Devices, Inc. | Die stacking, testing and packaging for yield |
US8756135B2 (en) | 2012-06-28 | 2014-06-17 | Sap Ag | Consistent interface for product valuation data and product valuation level |
US9191343B2 (en) | 2013-03-15 | 2015-11-17 | Sap Se | Consistent interface for appointment activity business object |
TWI602278B (zh) * | 2015-11-05 | 2017-10-11 | 凌陽科技股份有限公司 | 半導體裝置 |
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JPS6173359A (ja) * | 1984-09-18 | 1986-04-15 | Fujitsu Ltd | 半導体装置 |
JPS6441947A (en) * | 1987-08-07 | 1989-02-14 | Hitachi Ltd | Semiconductor integrated circuit |
JPH025455A (ja) * | 1988-06-24 | 1990-01-10 | Hitachi Ltd | チップオンチップの半導体装置 |
JPH04291096A (ja) * | 1991-03-20 | 1992-10-15 | Fujitsu Ltd | 半導体装置 |
JPH0540836A (ja) * | 1991-08-02 | 1993-02-19 | Nec Corp | シングルチツプマイクロコンピユータ |
JPH05343609A (ja) * | 1992-06-04 | 1993-12-24 | Nec Corp | 半導体集積回路装置 |
JPH09152979A (ja) | 1995-09-28 | 1997-06-10 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2000094874A (ja) * | 1998-09-22 | 2000-04-04 | Canon Inc | 電子部品内蔵カードとその製造方法 |
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JP2002076248A (ja) | 2000-08-29 | 2002-03-15 | Oki Micro Design Co Ltd | マルチチップパッケージ |
JP2002124626A (ja) | 2000-10-16 | 2002-04-26 | Hitachi Ltd | 半導体装置 |
JP2003022430A (ja) * | 2001-07-06 | 2003-01-24 | Hitachi Ltd | メモリカード |
JP3668165B2 (ja) * | 2001-09-11 | 2005-07-06 | 松下電器産業株式会社 | 半導体装置 |
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JP2008033724A (ja) | 2006-07-31 | 2008-02-14 | Mitsumi Electric Co Ltd | シングル・チップ半導体集積回路装置の製造方法、プログラムデバッグ方法、マイクロコントローラの製造方法 |
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Also Published As
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KR100881929B1 (ko) | 2009-02-04 |
US7576420B2 (en) | 2009-08-18 |
JP2008034690A (ja) | 2008-02-14 |
US20080088000A1 (en) | 2008-04-17 |
TWI400786B (zh) | 2013-07-01 |
KR20090004808A (ko) | 2009-01-12 |
KR20080012134A (ko) | 2008-02-11 |
KR100895683B1 (ko) | 2009-04-30 |
TW200807680A (en) | 2008-02-01 |
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