JP4186894B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4186894B2 JP4186894B2 JP2004247887A JP2004247887A JP4186894B2 JP 4186894 B2 JP4186894 B2 JP 4186894B2 JP 2004247887 A JP2004247887 A JP 2004247887A JP 2004247887 A JP2004247887 A JP 2004247887A JP 4186894 B2 JP4186894 B2 JP 4186894B2
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- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor
- semiconductor device
- mounting region
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
図1は、本発明の第1実施形態に係る半導体装置100の概略構成を示す図であり、(a)は概略断面図、(b)は概略平面図である。
次に、本実施形態の種々の変形例を図4、図5、図6を参照して示しておく。なお、各図4〜図6では、第1の半導体チップ10と第2の半導体チップ20とは、図示しないボンディングワイヤなどにより電気的に接続されている。
図7は、本発明の第2実施形態に係る半導体装置の要部を示す概略断面図であり、本半導体装置における第1および第2の半導体チップ10、20の部分拡大断面図である。本実施形態の半導体装置は、上記実施形態の半導体装置の一部を変形したものであり、上記実施形態との相違点を中心に述べる。
図8は、本発明の第3実施形態に係る半導体装置の要部を示す概略断面図であり、本半導体装置における第1および第2の半導体チップ10、20の部分拡大断面図である。本実施形態の半導体装置は、上記第1実施形態と第2実施形態とを組み合わせたものであり、上記実施形態との相違点を中心に述べる。
なお、上記溝22は、上記した各図示例に限定されるものではない。つまり、溝22は、第1の半導体チップ10の一面における第2の半導体チップ20の搭載領域の外周に、当該搭載領域を取り囲むように形成されていればよく、その形状や位置は必要に応じて任意のものを適宜採用できる。
11a…第1の半導体チップの保護膜における一番下地側の層としてのSiN化膜、
11b…第1の半導体チップの保護膜における表層側の層としてのポリイミド膜、
12…溝、20…第2の半導体チップ、30…ダイマウント材、
41…リードフレームのリード、50…ボンディングワイヤ、60…モールド樹脂。
Claims (3)
- 第1の半導体チップ(10)の一面上に、ダイマウント材(30)を介して第2の半導体チップ(20)が搭載され、これら両半導体チップ(10、20)がモールド樹脂(60)により封止されてなる半導体装置において、
前記第1の半導体チップ(10)の一面に溝(12)が格子状のパターンに形成されており、該格子状のパターンに形成された溝(12)により前記第2の半導体チップ(20)の搭載領域の外周に、当該搭載領域を取り囲むように溝(12)が形成されていることを特徴とする半導体装置。 - 前記第1の半導体チップ(10)の一面側には、2層以上の積層された保護膜(11)が設けられており、
前記溝(12)は、前記保護膜(11)のうち少なくとも一番下地側の層(11a)を残して表層側の層(11b)を除去したものとして構成されていることを特徴とする請求項1に記載の半導体装置。 - 前記第1の半導体チップ(10)の一面における前記第2の半導体チップ(20)の搭載領域は、当該一面における当該搭載領域以外の部位よりも鏡面に近い面となっていることを特徴とする請求項1または2に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004247887A JP4186894B2 (ja) | 2004-08-27 | 2004-08-27 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004247887A JP4186894B2 (ja) | 2004-08-27 | 2004-08-27 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006066670A JP2006066670A (ja) | 2006-03-09 |
JP4186894B2 true JP4186894B2 (ja) | 2008-11-26 |
Family
ID=36112868
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004247887A Expired - Fee Related JP4186894B2 (ja) | 2004-08-27 | 2004-08-27 | 半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP4186894B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4846515B2 (ja) | 2006-10-18 | 2011-12-28 | 株式会社東芝 | 光半導体装置及び光半導体装置の製造方法 |
-
2004
- 2004-08-27 JP JP2004247887A patent/JP4186894B2/ja not_active Expired - Fee Related
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JP2006066670A (ja) | 2006-03-09 |
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