KR100204753B1 - 엘오씨 유형의 적층 칩 패키지 - Google Patents

엘오씨 유형의 적층 칩 패키지 Download PDF

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KR100204753B1
KR100204753B1 KR1019960006069A KR19960006069A KR100204753B1 KR 100204753 B1 KR100204753 B1 KR 100204753B1 KR 1019960006069 A KR1019960006069 A KR 1019960006069A KR 19960006069 A KR19960006069 A KR 19960006069A KR 100204753 B1 KR100204753 B1 KR 100204753B1
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South Korea
Prior art keywords
chip
inner leads
package
electrical connection
bonding pads
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KR1019960006069A
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English (en)
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KR970067783A (ko
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안민철
정도수
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윤종용
삼성전자주식회사
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Priority to KR1019960006069A priority Critical patent/KR100204753B1/ko
Priority to JP8347854A priority patent/JPH09246465A/ja
Priority to US08/811,150 priority patent/US5804874A/en
Publication of KR970067783A publication Critical patent/KR970067783A/ko
Application granted granted Critical
Publication of KR100204753B1 publication Critical patent/KR100204753B1/ko

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Abstract

본 발명은 적층 칩 패키지에 관한 것으로, LOC 기술을 적용하여 칩들 간의 상호 전기적 연결되도록 적층함으로써, 리드프레임의 내부리드의 과도한 절곡 및 횟수가 감소되고, 각 전기적 연결 구조들의 순차적 적층에 있어서, 그 구조들 간의 전기적 간섭을 최소화할 수 있는 동시에 그 구조들 간의 적층 높이가 최소화되어 패키지의 두께가 박형화될 수 있고, 패키지의 제조 단가를 낮출 수 있는 동시에 신뢰성이 보장된 패키지를 제조할 수 있는 장점을 갖는다.

Description

LOC(lead on chip) 유형의 적층 칩 패키지
제1도는 종래 기술에 의한 LOC 유형의 적층 칩 패키지를 나타내는 단면도.
제2도는 본 발명의 일 실시예에 의한 LOC 유형의 적층 칩 패키지를 나타내는 평면도.
제3도는 제2도의 A-A선을 따라 자른 단면도.
제4도는 제3도의 하부 전기적 연결 구조를 나타내는 평면도.
제5도는 제3도의 상부 전기적 연결 구조를 나타내는 평면도.
제6도∼제12도는 본 발명의 패키지가 제조되는 단계를 나타내는 단면도.
제13도는 본 발명의 다른 실시예에 의한 LOC 유형의 적층 칩 패키지를 나타내는 단면도.
* 도면의 주요부분에 대한 부호의 설명
110, 210 : 칩 120, 220 : 내부리드
130, 230 : 폴리이미드 테이프 150 : 절연 필름
200 : 하부 전기적 연결 구조 300 : 상부 전기적 연결 구조
330 : 외부리드 360 : 성형 수지
400 : 패키지
본 발명은 적층 칩 패키지에 관한 것으로, 더욱 상세하게는 LOC 기술을 적용하여 칩들을 상호 전기적 연결되도록 적층함으로써, 종래의 반도체 제조 장비를 그대로 이용할 수 있는 동시에 그 적층 칩 패키지의 두께를 줄일 수 있는 LOC(lead on chip) 기술을 적용한 적층 칩 패키지에 관한 것이다.
소위, LOC 기술은 리드프레임의 다이패드를 제거하고, 그 리드프레임의 내부리드들을 실장될 칩의 액티브 영역 상부면까지 연장하여, 그 내부리드들을 상기 칩의 상부면과 접착한 후, 그 내부리드들에 각기 대응된 상기 칩의 본딩 패드들과 각기 전기적 연결하는 기술을 말한다.
또한, 적층 칩 기술은 하나의 패키지 내부에 복수개의 칩들을 수직구조로 적층하는 기술을 의미하며, 이 기술은 주로 DRAM 패키지의 용량을 증대시키는 방법으로 사용되고 있다.
제1도는 종래 기술에 의한 LOC 유형의 적층 칩 패키지를 나타내는 단면도이다.
제1도를 참조하면, 종래 기술에 의한 패키지(100)는 하부 칩(10)과 상부칩(20)이 각기 마주보고 실장되어 있으며, 그 칩들(10)(20)에 각기 대응된 내부리드들(30)(40)이 각기 폴리이미드 테이프(50)(60)에 의해 상기 칩들(10)(20)의 엑티브 영역에 접착되어 있는 구조를 갖는다.
그리고, 상기 각 칩들(10)(20)의 본딩 패드들에 각기 대응된 내부리드들(30)(40)은 각기 본딩 와이어들(70)(80)에 의해 각기 전기적 연결되어 있으며, 상기 각 칩들(10)(20), 내부리드들(30)(40) 및 본딩 와이어들(70)(80)을 포함하는 전기적 연결 부분을 외부의 환경으로부터 보호하기 위해 성형 수지(90)에 의해 봉지된 구조를 갖는다.
그리고, 상기 하부 칩(10)에 전기적 연결된 내부리드들(30)은 외부리드들(35)과 일체형으로 형성되어 있으며, 그 외부리드들(35)은 상기 성형수지(90)에 대하여 노출되어 인쇄회로기판과 같은 전자 장치에 실장되어 전기적 접속을 할 수 있도록 형성되어 있다.
또한, 상기 칩들(10)(20)간의 상호 전기적 연결을 위하여, 상기 상부칩(20)과 전기적 연결된 내부리드들(40)은 상기 하부 칩(10)과 전기적 연결된 내부리드들(30)의 상부면 상에 YAG 레이저에 의해서 전기적 연결된 구조를 갖는다.
그러나, 이와 같은 구조를 갖는 적층 칩 패키지는,
① 상기 본딩 와이어들(70)(80)간의 기계적 접촉에 의한 전기적 고장을 방지하기 위하여, 패키지의 크기가 더 두껍게 제조되어야 하기 때문에 그 패키지의 박형화가 곤란하고,
② 상기 ①의 이유로 인하여 상기 리드프레임이 수회 절곡되어야 하기 때문에 패키지의 제조 공정 횟수가 증가되는 단점을 갖는다.
따라서 본 발명의 목적은 통상적인 리드프레임과 적층을 위해 절곡된 리드프레임을 사용하여 적층 칩 패키지를 구현함으로써, 그 패키지의 제조 공정을 단축하는 동시에 그로 인하여 그 패키지의 두께를 줄일 수 있는 LOC 유형의 적층 칩 패키지를 제공하는데 있다.
상기 목적을 달성하기 위하여, 복수개의 본딩 패드들을 갖는 상부 칩, 및 그 상부 칩의 본딩 패드들이 형성된 면까지 연장되어 그 상부 칩과 접착되어 있으며, 각기 대응된 상기 본딩 패드들에 각기 전기적 연결된 상부 내부리드들을 포함하는 상부 전기적 연결 구조; 복수개의 본딩 패드들을 갖는 하부 칩, 그 하부 칩의 본딩 패드들이 형성된 면까지 연장되어 그 하부 칩과 접착되어 있으며, 각기 대응된 상기 본딩 패드들에 각기 전기적 연결된 하부 내부리드들, 및 그 하부 내부리드들에 일체로 형성된 외부리드들을 포함하는 하부 전기적 연결 구조; 및 상기 하부 내부리드들과 상기 상부 칩간에 개재·접착된 절연 필름을 포함하며, 상기 상부 내부리드들이 절곡되어 그 상부 내부리드들에 각기 대응된 상기 하부 내부리드들의 상부면에 전기적 연결된 것을 특징으로 하는 LOC 유형의 적층 칩 패키지를 제공한다.
이하, 첨부 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다.
제2도는 본 발명의 일 실시예에 의한 LOC 유형의 적층 칩 패키지를 나타내는 평면도이다.
제3도는 제2도의 A-A선을 따라 자른 단면도이다.
제4도는 제3도의 하부 전기적 연결 구조를 나타내는 평면도이다.
제5도는 제3도의 상부 전기적 연결 구조를 나타내는 평면도이다. 제2도∼제5도를 참조하면, 본 발명에 의한 패키지(400)는 실제적으로 16M 2DRAM을 2개 적층한 실시예로써, 하부 전기적 연결 구조(200)와 상기 전기적 연결 구조(300)의 내부리드들(120)(220)이 각기 솔더(solder), 금(Au) 및 구리(Cu)들과 같은 전도성 재질의 범프들(310)에 의해 각기 전기적 연결된 구조를 갖는다.
또한, 하부 전기적 연결 구조(200)의 외부리드들(330)은 상기 각기 전기적 연결된 내부리드들(120)(220)과 각기 공통 전기적 연결되어 있으며, 상기 하부 전기적 연결 구조(200)의 내부리드들(120)과 일체형으로 형성되어 있다.
그리고, 상기 상하부 전기적 연결 구조(200)(330)의 외부리드들(330)을 제외한 부분이 에폭시 성형 수지(360)에 의해 봉지되어 있다.
상기 상하부 전기적 연결 구조(200)(300)간의 기계적 접촉을 방지하기 위하여, 상기 하부 전기적 연결 구조(200)의 내부리드들(120) 상부면과 상기 상부 전기적 연결 구조(300)의 칩(210) 하부면에 폴리이미드 재질의 절연 필름(150)이 개재되어 있다.
이 때, 상기 개재된 절연 필름(150)은 상기 하부 전기적 연결 구조(200)의 본딩 와이어들(140)과 상기 상부 전기적 연결 구조(300)의 칩(210)이 하부면이 기계적 접촉되지 않도록 적절한 두께를 갖는다.
좀 더 상세히 설명하면, 상기 하부 전기적 연결 구조(200)는, 칩(110)의 엑티브 영역의 상부면까지 리드프레임의 내부리드들(120)이 길게 연장되어 있으며, 그 내브리드들(120)의 하부면과 상기 칩(110)의 상부면이 폴리이미드 테이프(130)에 으해 접착되어 있다.
그리고, 그 칩(110)의 중심 부분에 형성된 본딩 패드들(112)은 그들(112)에 각기 대응된 내부리드들(120)과 각기 본딩 와이어들(140)에 의해 각기 전기적 연결되어 있는 구조를 갖는다.
또한, 상기 상부 전기적 연결 구조(300)는, 칩(210)의 엑티브 영역의 상부면까지 리드프레임의 내부리드들(220)이 길게 연장되어 있으며, 그 내부리드들(220)의 하부면과 상기 칩(210)의 상부면이 폴리이미드 테이프(230)에 의해 접착되어 있다.
그리고, 그 칩(210)의 중심 부분에 형성된 본딩 패드들(212)은 그들(212)에 각기 대응된 내부리드들(220)과 각기 본딩 와이어들(240)에 의해 각기 전기적 연결되어 있는 구조를 갖는다.
더욱이, 상기 상부 전기적 연결 구조(300)의 내부리드들(220) 선단부들은 각기 하부 전기적 연결 구조(200)의 내부리드들(120)과 각기 전기적 연결되기 위하여 아래로 절곡(down set)되어 형성된 구조를 갖는다.
제6도∼제12도는 본 발명의 패키지가 제조되는 단계를 나타내는 단면도이다.
제6도∼제12도를 참조하면, 전술된 제2도∼제5도에서 설명된 패키지의 제조 단계는 다음과 같다.
여기서, 번호 매김은 생략하기로 한다.
① 우선, 상하부 전기적 연결 구조에 이용되는 리드프레임이 준비된다.
② 그 각 리드프레임들과 그들에 각기 대응된 칩이 본딩 와이어들에 의해 각기 전기적 연결된다.
③ 상기 상하부 전기적 연결 구조가 적층되고, 계속해서 열압착기(410)에 의해 그 기계적으로 접촉된 그 각 구조들의 내부리드들간이 열압착되어 각기 전기적 연결되낟.
④ 그런 다음, 상기 열압착기(410)가 제거되고, 그 적층된 상하부 전기적 연결 구조가 성형 공정을 거치게 되고, 계속해서 그 성형 공정 이후의 공정인 소위 백-앤드 공정을 거쳐서 적층 칩 패키지가 제조된다.
그리고, 제13도의 적층 칩 패키지(500)는 전기적 연결 구조가 복수개 적층된 구조를 나타내고 있는 본 발명의 다른 실시예로써, 제6도∼제11도의 단계를 복수번 반복된 것이기 때문에 상세한 설명을 생략하기로 한다.
또한, 상기 적층 칩 패키지(500)의 번호는 제3도를 참조하여 생략하기로 한다.
이와 같은 구조를 갖는 패키지는,
① 리드프레임의 내부리드의 과도한 절곡 및 횟수가 감소되고,
② 각 전기적 연결 구조들의 순차적 적층에 있어서, 그 구조들 간의 전기적 간섭을 최소화할 수 있는 동시에 그 구조들 간의 적층 높이가 최소화되어 패키지의 두께가 박형화될 수 있고,
③ 그 전기적 연결 구조들 간의 적층에 있어서, 그 구조들의 본딩 와이어들이 손상되는 것을 방지하기 위하여 절연 필름을 개재함으로써, 전기적 연결 공정 외의 성형 공정 등에 의해 발생되는 외력으로부터 그 구조들의 신뢰성을 보장할 수 있으며,
④ 결과적으로, 패키지의 제조 단가를 낮출 수 있는 동시에 신뢰성이 보장된 패키지를 제조할 수 있는 이점(利點)이 있다.

Claims (5)

  1. 복수개의 본딩 패드들을 갖는 상부 칩과, 그 상부 칩의 본딩 패드들이 형성된 면까지 연장되어 그 상부 칩과 접착수단으로써 접착되어 있으며 각기 대응된 상기 본딩 패드들에 각기 전기적 연결된 상부 내부리드들을 포함하는 상부 전기적연결 구조; 복수개의 본딩 패드들을 갖는 하부 칩과, 그 하부 칩의 본딩 패드들이 형성된 면까지 연장되어 그 하부 칩과 접착수단으로써 접착되어 있으며 각기 대응된 상기 본딩 패드들에 각기 전기적 연결된 하부 내부리드들과, 그 하부 내부리드들에 일체로 형성된 외부리드들을 포함하는 하부 전기적연결 구조; 및 상기 하부 내부리드들과 상기 상부 칩 사이의 간격을 일정간격 떨어뜨리기 위하여 접착된 절연 필름을 포함하며, 상기 상부 내부리드들이 절곡되어 그 상부 내부리드들에 각기 대응된 상기 하부 내부리드들이 상부면에 연결수단을 통하여 전기적으로 연결되고, 상기 각 구성요소가 성형수지에 의해 몰딩되고 하부연결 구조의 외부리드가 성형수지 몰드물 밖으로 노출된 것을 특징으로 하는 LOC 유형의 적층 칩 패키지.
  2. 제1항에 있어서, 상기 상부 칩 접착수단과 하부 칩 접착수단은 폴리이미드 테이프인 것을 특징으로 하는 LOC 유형의 적층 칩 패키지.
  3. 제1항에 있어서, 상기 상부 내부리드들과 그들에 각기 대응된 상기 하부 내부리드들을 연결하는 연결수단이 전도성 재질인 범프인 것을 특징으로 하는 LOC 유형의 적층 칩 패키지.
  4. 제1항에 있어서, 상기 범프의 재질이 솔더인 것을 특징으로 하는 LOC 유형의 적층 칩 패키지.
  5. 제3, 4항중 어느 한 항에 있어서, 상기 절연 필름의 재질이 양면 접착성 폴리이미드인 것을 특징으로 하는 LOC 유형의 적층 칩 패키지.
KR1019960006069A 1996-03-08 1996-03-08 엘오씨 유형의 적층 칩 패키지 KR100204753B1 (ko)

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JP8347854A JPH09246465A (ja) 1996-03-08 1996-12-26 Ｌｏｃ型半導体チップの積層チップパッケージ
US08/811,150 US5804874A (en) 1996-03-08 1997-03-04 Stacked chip package device employing a plurality of lead on chip type semiconductor chips

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