KR100470897B1 - 듀얼 다이 패키지 제조 방법 - Google Patents
듀얼 다이 패키지 제조 방법 Download PDFInfo
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- KR100470897B1 KR100470897B1 KR10-2002-0042539A KR20020042539A KR100470897B1 KR 100470897 B1 KR100470897 B1 KR 100470897B1 KR 20020042539 A KR20020042539 A KR 20020042539A KR 100470897 B1 KR100470897 B1 KR 100470897B1
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Abstract
Description
Claims (11)
- 듀얼 다이 패키지 제조 방법으로,(a) 제 1 칩과, 상기 제 1 칩의 활성면에 부착되어 상기 제 1 칩과 전기적으로 연결되는 제 1 리드로, 상기 제 1 칩 외곽에 위치하는 부분이 상기 제 1 칩의 배면에 대응되게 단차지게 형성된 제 1 리드와, 제 1 리드의 끝단을 연결하는 제 1 사이드 프레임을 포함하는 제 1 리드 프레임과,상기 제 2 칩과, 상기 제 2 칩의 활성면에 부착되어 상기 제 2 칩과 전기적으로 연결되는 제 2 리드로, 상기 제 2칩의 외곽에 위치하는 부분이 상기 제 2 칩의 배면에 대응되게 단차지게 형성된 제 2 리드와, 상기 제 2 리드를 수직으로 가로질러 연결하며 상기 제 1 사이드 프레임의 위치에 대응되는 위치에 형성된 제 2 댐바를 포함하는 제 2 리드 프레임을 준비하는 단계와;(b) 제 1 칩과 제 2 칩의 배면끼리 서로 접하도록 배치할 때 상기 제 1 및 제 2 리드 프레임이 겹치는 양쪽 면에 성형 공정의 온도에서 내산화성이 있고, 금속 간 확산력이 양호한 도금층을 형성하는 단계와;(c) 상기 도금층과 성형 공정의 온도에서 금속 접합을 이루는 접합 부재를 상기 제 1 또는 제 2 리드 프레임의 도금층에 형성하는 단계와;(d) 제 1 칩과 제 2 칩의 배면끼리 서로 접하도록 제 1 및 제 2 리드 프레임을 겹치게 성형 금형에 투입하여 패키지 몸체를 형성하는 성형 단계;를 포함하며,상기 (d) 단계에서 상기 성형 금형이 상기 제 1 리드 프레임과 상기 제 2 리드 프레임을 클램핑 할 때 작용하는 열과 압력에 의해 상기 접합 부재는 상기 제 2 리드 프레임과 제 2 리드 프레임의 겹치는 면에서 상기 도금층과 금속 접합을 이루어 전기적으로 접합되는 것을 특징으로 하는 듀얼 다이 패키지의 제조 방법.
- 제 1항에 있어서, 상기 제 1 리드 프레임과 제 2 리드 프레임의 겹치는 제 1 사이드 프레임과 제 2 댐바를 포함하는 부분은 상기 접합 부재와 양호한 접합성을 갖는 도금층이 형성된 것을 특징으로 하는 듀얼 다이 패키지의 제조 방법.
- 제 2항에 있어서, 상기 도금층은 은 또는 솔더 도금층인 것을 특징으로 하는 듀얼 다이 패키지의 제조 방법.
- 제 3항에 있어서, 상기 (c) 단계의 상기 접합 부재는 상기 제 1 리드 프레임과 상기 제 2 리드 프레임이 겹치는 상기 제 1 사이드 프레임과 제 2 댐바의 적어도 한쪽 면을 따라서 형성되는 것을 특징으로 하는 듀얼 다이 패키지의 제조 방법.
- 제 4항에 있어서, 상기 접합 부재는 상기 (d) 단계의 성형 온도에서 상기 도금층과 확산에 의한 금속 접합을 이루는 금(Au) 또는 솔더(solder) 소재인 것을 특징으로 하는 듀얼 다이 패키지의 제조 방법.
- 제 5항에 있어서, 상기 접합 부재는 상기 제 1 리드 프레임과 상기 제 2 리드 프레임이 겹치는 상기 제 1 사이드 프레임과 제 2 댐바의 적어도 한쪽 면을 따라서 불연속적으로 와이어 본딩된 금(Au) 소재의 본딩 와이어인 것을 특징으로 하는 듀얼 다이 패키지의 제조 방법.
- 제 5항에 있어서, 상기 접합 부재는 상기 제 1 리드 프레임과 상기 제 2 리드 프레임이 겹치는 상기 제 1 사이드 프레임과 제 2 댐바의 적어도 한쪽 면을 따라서 소정의 간격을 두고 형성된 금 범프(Au bump)인 것을 특징으로 하는 듀얼 다이 패키지의 제조 방법.
- 제 5항에 있어서, 상기 접합 부재는 상기 제 1 리드 프레임과 상기 제 2 리드 프레임이 겹치는 상기 제 1 사이드 프레임과 제 2 댐바의 적어도 한쪽 면을 따라서 소정의 간격을 두고 형성된 솔더 범프(solder bump)인 것을 특징으로 하는 듀얼 다이 패키지의 제조 방법.
- 제 5항에 있어서, 상기 접합 부재는 상기 제 1 리드 프레임과 상기 제 2 리드 프레임이 겹치는 상기 제 1 사이드 프레임과 제 2 댐바의 적어도 한쪽 면을 따라서 불연속적으로 형성된 금 막대(Au bar)인 것을 특징으로 하는 듀얼 다이 패키지의 제조 방법.
- 제 5항에 있어서, 상기 접합 부재는 상기 제 1 리드 프레임과 상기 제 2 리드 프레임이 겹치는 상기 제 1 사이드 프레임과 제 2 댐바의 적어도 한쪽 면을 따라서 불연속적으로 형성된 솔더 막대(solder bar)인 것을 특징으로 하는 듀얼 다이 패키지의 제조 방법.
- 제 7항 내지 제 10항의 어느 한 항에 있어서, 상기 접합 부재는 제 1 리드 프레임과 제 2 리드 프레임의 겹치는 제 1 사이드 프레임과 제 2 댐바에 모두 형성되며, 서로 어긋난 위치에 형성되는 것을 특징으로 하는 듀얼 다이듀얼 다이의 제조 방법.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0042539A KR100470897B1 (ko) | 2002-07-19 | 2002-07-19 | 듀얼 다이 패키지 제조 방법 |
| US10/382,591 US7148080B2 (en) | 2002-07-19 | 2003-03-07 | Method for joining lead frames in a package assembly, method for forming a chip stack package, and a chip stack package |
| JP2003271610A JP2004056138A (ja) | 2002-07-19 | 2003-07-07 | パッケージ組立体においてリードフレームを接合する方法、チップ積層パッケージの製造方法及びチップ積層パッケージ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0042539A KR100470897B1 (ko) | 2002-07-19 | 2002-07-19 | 듀얼 다이 패키지 제조 방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20040008827A KR20040008827A (ko) | 2004-01-31 |
| KR100470897B1 true KR100470897B1 (ko) | 2005-03-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR10-2002-0042539A Expired - Fee Related KR100470897B1 (ko) | 2002-07-19 | 2002-07-19 | 듀얼 다이 패키지 제조 방법 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7148080B2 (ko) |
| JP (1) | JP2004056138A (ko) |
| KR (1) | KR100470897B1 (ko) |
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| JP2007142050A (ja) * | 2005-11-16 | 2007-06-07 | Mitsui High Tec Inc | 積層リードフレームの製造方法及び積層リードフレーム |
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| US7868440B2 (en) | 2006-08-25 | 2011-01-11 | Micron Technology, Inc. | Packaged microdevices and methods for manufacturing packaged microdevices |
| US7701042B2 (en) * | 2006-09-18 | 2010-04-20 | Stats Chippac Ltd. | Integrated circuit package system for chip on lead |
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| US8063470B1 (en) * | 2008-05-22 | 2011-11-22 | Utac Thai Limited | Method and apparatus for no lead semiconductor package |
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| JP5857755B2 (ja) * | 2012-01-24 | 2016-02-10 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
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| US9029198B2 (en) | 2012-05-10 | 2015-05-12 | Utac Thai Limited | Methods of manufacturing semiconductor devices including terminals with internal routing interconnections |
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| US10242953B1 (en) | 2015-05-27 | 2019-03-26 | Utac Headquarters PTE. Ltd | Semiconductor package with plated metal shielding and a method thereof |
| US10242934B1 (en) | 2014-05-07 | 2019-03-26 | Utac Headquarters Pte Ltd. | Semiconductor package with full plating on contact side surfaces and methods thereof |
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-
2002
- 2002-07-19 KR KR10-2002-0042539A patent/KR100470897B1/ko not_active Expired - Fee Related
-
2003
- 2003-03-07 US US10/382,591 patent/US7148080B2/en not_active Expired - Fee Related
- 2003-07-07 JP JP2003271610A patent/JP2004056138A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JP2004056138A (ja) | 2004-02-19 |
| KR20040008827A (ko) | 2004-01-31 |
| US20040014257A1 (en) | 2004-01-22 |
| US7148080B2 (en) | 2006-12-12 |
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